JP2002111767A - Receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a common receiver for BS/CS digital broadcast. SOLUTION: A carrier synchronizing part 134 in a demodulation part is provided with a timing control circuit 141, a BS phase error detecting circuit 142, a CS phase error detecting circuit 143, a filter 144 and NCO 145. In carrier synchronism 134, the two detection parts of phase error quantity are installed for BS and CS. Subsequent filter 144 and NCO 145 are shared. In the case of the reception of BS digital broadcast, the phase error quantity of transmission data is calculated based on the modulation system of BPSK and only TMCC, TAB and a burst signal are intermittently detected. In the case of the reception of CS digital broadcast, the phase error quantity of transmission data is calculated based on a QPSK modulation system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving apparatus for receiving digital broadcasting.

[0002]

2. Description of the Related Art In a general transmission system for transmitting digital data by performing digital quadrature modulation, a carrier generated from a local oscillator between a transmitting side and a receiving side has a phase error and a frequency error. Therefore, the reception signal point rotates by an angle corresponding to the error phase and the frequency error with respect to the transmission signal.

For this reason, the receiving side performs a carrier synchronization process such as detecting a phase error amount from a received signal point and correcting a phase error and a frequency error, thereby removing a phase error and a frequency error of the received signal point.

[0004]

By the way, at present, as a digital broadcasting medium in Japan, a communication satellite (C
There is CS digital broadcasting using S), and in addition to this service, digital satellite broadcasting (BS digital broadcasting) using a broadcasting satellite (BS) has been proposed as a new digital broadcasting medium.

[0005] Therefore, in recent years, there has been a demand for a shared receiving device that can receive BS digital broadcasts as well as CS digital broadcasts.

[0006] However, in the CS digital broadcasting system, which has already started the service in Japan,
While the QPSK modulation method is adopted, the BPSK, Q
Three types of modulation schemes, PSK and 8PSK, are employed, and each modulation scheme dynamically changes over time.

[0007] Therefore, when detecting the phase error amount of the received signal point to perform carrier wave synchronization, the phase error detection range is 4 because CS digital broadcasting uses the QPSK modulation method.
Although it is 5 degrees, BPSK,
Since three types of modulation schemes, QPSK and 8PSK, are employed, the detection schemes are different, and it has been difficult to share a carrier synchronization unit.

[0008] The present invention has been made in view of such circumstances, and has as its object to provide a receiving device that is shared between CS digital broadcasting and BS digital broadcasting.

[0009]

In order to solve the above-mentioned problems, digital broadcasting of a first broadcasting system in which synchronization symbols are BPSK-modulated and digital broadcasting of a second broadcasting system in which all symbols are QPSK-modulated Receiving means for synchronizing the symbol timing of the transmission data, and detecting a synchronization word from the transmission data synchronized with the timing when receiving the first broadcast digital broadcast. Frame synchronization means for detecting the frame synchronization timing of the transmission data, and a carrier synchronization means for performing the synchronization processing of the carrier wave, the carrier synchronization means, for the transmission data consisting of orthogonal coordinate signals, the rotation correction signal A carrier correction unit that corrects a carrier error by performing complex multiplication, and a carrier correction unit that is used when receiving a digital broadcast of the first broadcast system. , BPSK phase rotation error amount of the transmission data carrier error is corrected by the carrier compensation unit
A first phase error calculator for calculating based on a modulation scheme, and a phase rotation error amount of transmission data, which is used when receiving a digital broadcast of the second broadcast system and whose carrier error is corrected by the carrier corrector, is QPSK-modulated. A second phase error calculating unit that calculates the number of symbols from the frame synchronization timing to specify at least the symbol position of the synchronization word when receiving digital broadcasting of the first broadcasting method, And a filter for filtering the phase rotation error amount of all symbols when digital broadcasting of the second broadcast system is received, and a filter for filtering the phase rotation error amount according to the filtered phase rotation error amount. A rotation correction signal generation unit that generates the rotation correction signal whose frequency and phase are controlled. That.

In this receiving apparatus, two calculation units for calculating the phase error amount of the carrier synchronization unit are provided for the first broadcast system and the second broadcast system. The first phase error calculator for the first broadcast system calculates the phase rotation error amount of the transmission data based on the BPSK modulation method. On the other hand, the second error calculator for the second broadcast system calculates the phase rotation error amount of the transmission data by QP
It is calculated based on the SK modulation method. A common filter and rotation correction signal generator are used in the first broadcast system and the second broadcast system.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a BS according to an embodiment of the present invention will be described.
A description will be given of a / CS digital broadcast shared receiving device.

[0012] Overall Configuration FIG 1 shows a block diagram of the shared receiver of BS / CS digital broadcasting, a description is given of the shared receiver of the BS / CS digital broadcasting.

The receiving apparatus 100 includes a demodulation unit 101 and a first
A demultiplexer 102, an inner code decoding unit 103,
The second demultiplexer 104 and the deinterleaver 10
5, BS inverse energy spreading section 106, frame reconstruction section 107, main signal RS decoding section 108, CS reverse energy spreading section 109, and TMCC reverse energy spreading section 1
10, a third demultiplexer 111, a TMCC Reed-Solomon decoding unit 112, and a TMCC control unit 113.

The receiving apparatus 100 receives a BS / CS selection signal indicating whether to receive a BS digital broadcast or a CS digital broadcast. The BS / CS selection signal is selected by a user, determined based on a data coding rate, or determined based on whether or not a superframe synchronization signal defined in BS digital broadcasting is detected. . When the coding rate is detected and determined, the BS / CS identification is unknown until the demodulation of the received signal is completed. Or a broadcast system that can be received by trial.

The demodulation unit 101 receives, for example, an RF signal received and received by a parabolic antenna or the like. The demodulation unit 101 multiplies the RF signal by the carrier signal to demodulate the quadrature modulated I and Q signals. The demodulation unit 101 also receives a BS / CS selection signal,
According to the selection of CS, the carrier frequency, the symbol timing frequency, the filter parameter, the carrier-synchronized phase error detection circuit, and the like are switched. This demodulation unit 101
Performs frequency conversion, carrier synchronization, and timing synchronization. When receiving a BS digital broadcast, the demodulation unit 101 detects a superframe and a frame start position from a BPSK-modulated TAB signal (synchronization word). The demodulated I signal data and Q signal data are
The data is sent to the first demultiplexer 102.

When receiving a BS digital broadcast, the first demultiplexer 102 counts the number of symbols from the frame start position detected by the demodulation unit 101, and outputs a burst signal at a predetermined symbol position. It is separated from main signal data and TMCC data (including the TAB signal). The main signal data and the TMCC data are sent to the inner code decoder 103, and the burst signal is read and discarded as it is. When CS digital broadcasting is being received, all data is not separated from the inner code decoding unit 1 without separating the data.
03.

The inner code decoder 103 performs depuncturing and Viterbi decoding according to the modulation scheme and inner code rate of each symbol. The inner code decoded data is sent to the second demultiplexer 104. Further, when receiving the CS digital broadcast, the inner code decoding unit 103 also estimates the coding rate (RATE) and detects the 0xB8 synchronization byte indicating the CS initialization position.

The second demultiplexer 104 separates the main signal data from the TMCC data (including the TAB signal) when receiving the BS digital broadcast. The separated main signal data is sent to the deinterleaver 105. The separated TMCC data (including the TAB signal)
It is sent to CC reverse energy diffusion processing section 106. Also, when receiving the CS digital broadcast, the second demultiplexer 104 transmits all data to the deinterleaver 105 without separating the data because there is no TMCC.

The deinterleaver 105 deinterleaves the main signal data according to a rule reverse to the interleaving process performed on the transmitting side. The deinterleaver 105 uses the BS
When receiving digital broadcasts, block deinterleaving is performed with superframes as interleaved blocks.
When receiving CS digital broadcasting, convolutional deinterleaving is performed. The deinterleaved main signal is sent to BS inverse energy spreading section 106.

At the time of receiving a BS digital broadcast, BS inverse energy spreading section 106 adds a 15th-order sequence pseudo-random sequence (PRBS) to the main signal data one bit at a time to obtain the energy transmitted on the transmission side. Performs reverse processing to the diffusion processing. Note that a pseudo random code sequence (PRB
S) is initialized at the beginning of the superframe. Also,
Energy spreading is not performed on the first byte of each slot, but PRBS continues to be generated during this time. The main signal data subjected to inverse energy spreading is sent to frame reconstructing section 107. It should be noted that the BS inverse energy spreading section 106 does not perform any processing at the time of receiving the CS digital broadcast, and transmits it to the frame reconstructing section 107 as it is.

The frame reconstructing unit 107 reconstructs the data structure into a frame structure corresponding to the data frame on the transmission side such as a process of adding a synchronization word (0x47) of the transport packet (TSP) deleted at the time of transmission. I do. The reconstructed main signal data is sent to the main signal Reed-Solomon decoding unit 109.

The main signal Reed-Solomon decoding unit 108
At the time of receiving a BS digital broadcast, RS decoding of the RS (204, 188) is performed in units of 204-byte transmission packets, and the TSP is output. Further, when receiving the CS digital broadcast, the main signal Reed-Solomon decoding unit 108 outputs the RS (20) as in the case of the main signal data of the BS.
4,188). In the case of CS digital broadcasting, the code start position of the RS code is the head position of the TSP.

At the time of receiving a CS digital broadcast, CS inverse energy spreading section 109 adds a 15th-order sequence pseudo-random sequence (PRBS) to main signal data one bit at a time, and performs energy conversion performed on the transmission side. Performs reverse processing to the diffusion processing. The data subjected to the inverse energy spreading is transmitted to the outside as a transport stream. Note that the CS reverse energy spreading section 109 does not perform any processing when receiving the BS digital broadcast, and sends the transport stream to the outside as it is.

TMCC inverse energy diffusion processing unit 110
Stores a superframe of TMCC data and a TAB signal in a buffer when receiving a BS digital broadcast, and then transmits a ninth-order pseudo random sequence (PRBS) to the TM
The CC data and the TAB signal are added one bit at a time, and inverse processing is performed on the energy spreading processing performed on the transmission side. Note that this pseudo random code sequence (PRB
S) is initialized at the beginning of the superframe. Also,
No energy spreading is performed on the TAB signal.
The occurrence of RBS continues. Energy spread TMC
The C data and the TAB signal are output to the third demultiplexer 1
11 is sent. Note that the TMCC inverse energy spread processing unit 110 does not operate when receiving CS digital broadcasting.

The third demultiplexer 111 separates the TMCC data and the TAB signal when receiving the BS digital broadcast. The separated TAB signal is discarded. The separated TMCC data is sent to TMCC Reed-Solomon decoding section 112. Note that the third demultiplexer 111 does not operate when receiving CS digital broadcast.

TMCC Reed-Solomon decoding section 112
Converts the TMCC data consisting of 64 bytes into RS (6
4, 48), and outputs TMCC information. The RS-decoded TMCC information is transmitted to the TMCC controller 1
13 is sent. Note that the TMCC Reed-Solomon decoding unit 112 does not operate when receiving CS digital broadcasting.

The TMCC control unit 113 extracts TMCC data necessary for transmission path decoding from the TMCC information, obtains TMCC information corresponding to each transport stream (TS), and transmits information necessary for decoding to each functional block. To deliver. Note that the TMCC control unit 113 does not operate when receiving CS digital broadcasting.

The receiving apparatus 100 having the above configuration receives a BS digital broadcast or a CS digital broadcast and demodulates a transport stream conforming to the MPEG-2 system.

[0029] Configuration Figure 2 demodulator, showing the configuration of a demodulator 101 of the receiving apparatus 100,
The demodulation unit 101 will be further described.

The demodulation unit 101 includes a first multiplier 121,
A second multiplier 122, a local oscillator 123, a 90-degree phase shifter 124, a first low-pass filter 125,
, A first analog / digital (A / D) converter 127, a second analog / digital (A / D) converter 128, a carrier correction unit 129,
First waveform shaping filter 130, second waveform shaping filter 131, timing synchronization unit 132, frame synchronization unit 133, carrier synchronization unit 134, third multiplier 1
35, a fourth multiplier 136, a parallel / serial (P / S) converter 137, and a slicer 138.

For example, an RF signal received by a parabolic antenna or the like is input to a first multiplier 121 and a second multiplier 122.

The local oscillator 123 generates a carrier wave which is a cos wave having a frequency fc 'and an initial phase th'. The carrier is switched to a service corresponding to the selected channel of the BS digital broadcast when receiving the BS digital broadcast, and is switched to the CS digital broadcast when receiving the CS digital broadcast.
The service is switched to a service corresponding to the selected channel of digital broadcasting. Frequency fc 'and initial phase th'
Are different from the carrier on the transmitting side and do not match.
The generated carrier is supplied to the 90-degree phase shifter 124 and the first multiplier 121.

The 90-degree phase shifter 124 delays the phase of the carrier wave, which is a cos wave, by 90 degrees to generate a -sin wave. The generated −sine wave is supplied to the second multiplier 122.

[0034] The first multiplier 121 calculates the cos
The I signal is quadrature-demodulated by multiplying the signal by a wave. Second multiplier 1
Reference numeral 22 multiplies the received signal by the −sin wave and quadrature-demodulates the Q signal. The demodulated I signal is supplied to a first A / D converter 127 after a high-frequency component is removed by a first low-pass filter 125. The demodulated Q signal is
The high-frequency component is removed by the second low-pass filter 126 and supplied to the second A / D converter 128.

The first A / D converter 127 digitizes the I signal. Further, the second A / D converter 128
Digitize the signal. The first A / D converter 127 and the second A / D converter 128 include a timing synchronization unit 132
I by the sampling clock CLK output from
The signal and the Q signal are sampled. At this time, the sampling frequency is controlled by the timing synchronization unit 132 so that the frequency and the phase are synchronized with the transmission symbol clock on the transmission side. Digitized I signal data and Q
The signal data is supplied to the carrier correction unit 129, respectively.

The carrier correction unit 129 includes the carrier synchronization unit 13
4 outputs the rotational phase correction signals (RI, RQ)
The I signal data and the Q signal data output from the first and second A / D converters 127 and 128 are subjected to complex multiplication.
The I signal data and the Q signal data are subjected to complex multiplication of the rotational phase correction signals (RI, RQ) to obtain the frequency fc 'and phase th' of the carrier generated by the local oscillator 123 on the receiving side and the phase th 'on the transmitting side. The frequency shift and the phase shift occurring between the frequency fc and the phase th of the carrier are corrected. That is, the carrier frequency error and the phase error are corrected. After the corrected I signal data is subjected to waveform shaping by the first waveform shaping filter 130,
Is supplied to the multiplier 135. The phase-corrected Q signal data is supplied to a fourth multiplier 136 after the waveform is shaped by a second waveform shaping filter 131.

The timing synchronizing section 132 is a circuit for performing a timing synchronizing process by controlling the sampling clock of the A / D converters 127 and 128. The timing synchronizer 132 includes the waveform shaping filters 130 and 13
A clock error of the received data whose waveform has been shaped by 1 is detected, and a sampling clock such that the clock error becomes 0, that is, a sampling clock whose phase and frequency are synchronized with the symbol clock of the transmission symbol on the transmission side is generated. I do. The timing synchronization unit 132 detects a clock error by using, for example, the 0-crossing method. The generated clock is used as a sampling clock for the first A / D converter 127 and the second A / D converter 128. Note that the sampling frequency is 2 in a state where timing is synchronized when receiving BS digital broadcasting.
8.86 × N MHz, and when receiving CS digital broadcasting, 21.09 with the timing synchronized.
6 × N MHz.

The frame synchronizing section 133 is a circuit for performing a frame synchronizing process for detecting a start position of a frame by detecting a TAB signal (synchronization word) in transmission data.

Here, in BS digital broadcasting, a data structure called a super frame is defined. As shown in FIG. 3, the superframe is composed of eight frames (frame # 0 to frame # 7).
Each frame is composed of a control signal section (TMCC signal and TAB signal (synchronization word)) and a main signal section (main signal and burst signal).

As shown in FIG. 4, the main signal section has 48 slots (slot # 0 to slot #) per frame.
47). The main signal section is configured by alternately arranging main signal data of 203 symbols and burst signals of 4 symbols subjected to BPSK modulation (r = １ ／).

The control signal section has a transmission and multiplexing configuration (TMCC) of 8 bytes per frame.
ation Control) signal and a 2-byte TAB signal (synchronization word) added before and after the signal.
The TMCC signal and the TAB signal are each subjected to BPSK modulation (r = １ ／), and in terms of the number of transmission symbols,
128 symbols for TMCC and 32 symbols for TAB signal
Become a symbol. Here, the value of the TAB signal attached to the stage preceding the TMCC is W1 (0x1B95). Also, the TA attached after the TMCC
The value of the B signal is W2 for the first frame # 0.
(0xA340), and the value is W3 (0x5CBF) for the second to eighth frames. W
2 and W3 have a bit-inverted relationship.

Therefore, by detecting the TAB signal (synchronization word), the frame can be synchronized, and by detecting the signals W2 and W3 separately, the superframe can be synchronized. . Note that the 2-byte TAB signal is actually convolutionally coded to be a 32-bit transmission symbol. Among them, the first 12 bits are affected by the last main signal data of the previous frame and the value is undefined, but the latter 20 bits are in a range that is not affected by the previous frame. Become. On the receiving side, this convolutionally coded fixed value (w1 for W1, w2 / w3 for W2 / W3)
Is detected as a synchronization signal.

The frame synchronization section 133 performs this frame synchronization processing in a state where timing synchronization is performed but carrier wave synchronization is not performed. Specifically, a difference operation between symbols is performed on transmission data synchronized with timing. Then, a correlation between the bit string subjected to the difference operation and the synchronization word subjected to the difference operation is obtained. Then, a symbol position having the highest correlation (or a symbol having a correlation value higher than a certain threshold value) is detected, and the symbol position is set as a frame synchronization position. Since the TAB signal W2 and W3 are in a bit-inverted relationship, the value becomes the same when a difference operation between symbols is performed.

The frame synchronizing unit 133 performs such a TA
The B signal is detected, and a frame start flag (FST flag) indicating a frame start position and a superframe start flag (SFST flag) indicating a start position of a superframe are set.
Flag). Also, the frame synchronization unit 133
Not only FST flag and SFST flag, but also SFS
By counting the number of symbols from the T flag, TA
TAB flag indicating the symbol position of B signal (synchronization word), TMC flag indicating the symbol position of TMCC
Flag, which is a flag indicating the symbol position of the main signal
An N flag and a BRST flag indicating the symbol position of the burst signal may also be generated and output. The frame start signal (FST) and the superframe start flag (S
FST) is supplied to the carrier synchronizer 134.

The frame synchronization section 133 also generates a 180-degree phase inversion signal. Carrier synchronizer 134 described later
Adopts a carrier synchronization method that allows a 180-degree phase uncertainty (a method in which the phase may be rotated by 180 degrees when synchronization is performed and synchronization may be applied). Therefore, the frame synchronization unit 133 uses the synchronization word (TAB
Signal), and a 180 ° carrier phase error is detected. If a 180-degree carrier phase error is detected, the 180-degree phase-inverted signal is output as -1. If no 180-degree carrier phase error is detected, the 180-degree phase-inverted signal is output as +1. This 180 degree phase inversion signal is supplied to the third multiplier 135 and the fourth multiplier 135.
Is supplied to the multiplier 136.

If the carrier synchronizer 134 can perform carrier synchronization without leaving the phase uncertainty of 180 degrees, 1
Either always keep the 80 degree phase inverted signal +1 or
The third multiplier 135, the fourth multiplier 136, and the 180-degree phase inversion signal may be omitted. Further, the frame synchronization unit 133 performs a frame synchronization operation in a state where the timing is synchronized by the timing synchronization unit 132.

The carrier synchronizer 134 generates a rotation phase correction signal (RI, RQ) according to the carrier frequency error and the phase error of the received data, and performs the carrier synchronization process. The carrier frequency error and the phase error of the received data are caused by the frequency shift and the phase shift of the carrier of the local oscillator 123.

Specifically, the carrier synchronizer 134 converts the received data in the rectangular coordinate system into angle data, and detects a rotation phase error indicating how much the angle data is rotated from the original reception point. I do. Then, the rotational phase error is filtered to detect a frequency component and a phase component of the rotational phase error. Then, the carrier synchronizer 134
Generates a rotational phase correction signal (RI, RQ) having a frequency and a phase by the VCO or the like to cancel the frequency component and the phase component of the detected rotational phase error.
The carrier correction unit 129 outputs the rotational phase correction signal (RI,
RQ) by complex multiplication of the received data to cancel the carrier frequency error and phase error.

In the case of receiving a BS digital broadcast, the carrier synchronizer 134 is synchronized with the timing by the timing synchronizer 132 and the frame synchronizer 1
33, the frame is synchronized.
Carrier synchronous operation is performed.

The third multiplier 135 multiplies the I signal data whose waveform has been shaped by the first waveform shaping filter 130 with the 180-degree phase inverted signal supplied from the frame synchronization section 133. If the 180-degree phase inversion signal is +1, the I signal data is output as it is. If the 180 degree phase inversion signal is -1, the sign of the I signal data is inverted and output. The output I signal data is supplied to the P / S converter 137.

The fourth multiplier 136 multiplies the Q signal data whose waveform has been shaped by the second waveform shaping filter 131 by the 180 degree phase inverted signal supplied from the frame synchronizing section 133. If the 180 degree phase inversion signal is +1 then
The Q signal data is output as it is. If the 180-degree phase inversion signal is -1, the sign of the Q signal data is inverted and output. The output Q signal data is supplied to the P / S converter 137.

The P / S converter 137 outputs I signal data, Q signal
The received data is selected in the order of the signal data and converted into serial data. The generated serial data is supplied to the slicer 138.

The slicer 138 outputs 0 when the input data is larger than a predetermined value, and outputs 1 when the input data is smaller than a predetermined value.

The demodulated data is output from the slicer 138 and supplied to the inner code decoder 103.

(Carrier synchronizer) Next, the carrier synchronizer 1
34 will be described in further detail.

As shown in FIG. 5, the carrier synchronizer 134 includes a timing control circuit 141, a BS phase error detection circuit 142, a CS phase error detection circuit 143, a filter 144, and an NCO 145. .

At the time of receiving a BS digital broadcast, the timing control circuit 141 receives a frame start flag (FST flag) from the frame synchronization circuit 134 shown in FIG. The timing control circuit 141 uses the FST
By counting the number of symbols from the flag,
It specifies the symbol timing that is always BPSK-modulated in BS digital broadcasting such as TMCC data, TAB signal (synchronization word), and burst signal. The timing control circuit 141 generates a BPSK flag that becomes valid (1) when the symbol is a TMCC data, a TAB signal, or a burst signal.
To supply. Further, the timing control circuit 141 controls the CS
When receiving a digital broadcast, the BPSK flag is always valid (1) and supplied to the filter 144.

The BS phase error detection circuit 142 is used only when receiving a BS digital broadcast. The BS phase error detection circuit 142 detects a phase error component included in the transmission data (I ″, Q ″) output from the second complex multiplier 131. Specifically, the BS phase error detection circuit 142 determines that the transmission data (I ″, Q ″) is BPSK
The phase error amount Δθ indicating how much the phase is shifted from the signal point of the original transmission symbol is calculated. The calculated phase error amount Δθ is supplied to the filter 144.

The CS phase error detection circuit 143 is used only when receiving a CS digital broadcast. The CS phase error detection circuit 143 detects a phase error component included in the transmission data (I ″, Q ″) output from the second complex multiplier 131. Specifically, the CS phase error detection circuit 143 determines that the transmission data (I ″, Q ″) is QPSK
The phase error amount Δθ indicating how much the phase is shifted from the signal point of the original transmission symbol is calculated. The calculated phase error amount Δθ is supplied to the filter 144.

The filter 144 is, for example, an IIR (Infini
It is composed of a loop filter such as a te Impulse Response filter and has the characteristics of an LPF (Low pass filter). The filter 144 receives the phase error amount Δθ, averages the input phase error amount Δθ, and outputs the averaged phase error amount Δθ.

For example, as shown in FIG. 6, the filter 144 includes a first multiplier 154 for multiplying the phase error Δθ by a gain G and a second multiplier 154 for multiplying the phase error Δθ by a coefficient K for determining a band. 155 and a coefficient (1
−K), an adder 157 that adds the output of the second multiplier 155 and the output of the third multiplier 156, and a register 158 that delays the output of the adder 157. It is composed of The filter 144 having such a configuration performs loop filtering on the input phase error amount Δθ with the coefficient K and the gain G, and averages the phase error amount Δθ.
θ is output from the register 158.

Here, the register 158 holds the averaged phase error amount Δθ at that time.
The register 158 updates the internal data only when the BPSK flag supplied from the timing control circuit 141 is input as an enable signal and the BPSK flag is valid (1). Therefore, the filter 14
4 is TMCC, TA for BS digital broadcast reception.
B, phase error amount Δθ obtained at burst symbol position
, And retains the last filter output value in other symbol positions. That is, the filter 144 intermittently performs filtering by extracting only the phase error amount Δθ of the symbol modulated by BPSK. At the time of receiving a CS digital broadcast, filtering is not performed intermittently, but is performed on all symbols.

The NCO 145 receives the averaged phase error Δθ from the filter 144. NCO145
Is the phase error correction signal (R
I, RQ) are generated and output.

The NCO 145 includes a cumulative adder 181 and a rectangular coordinate conversion circuit 182 as shown in FIG.

The accumulator 181 includes an adder 183 and a register.
And a star 184. The adder 183 outputs
And the phase error amount Δθ input from the
An addition operation is performed with the stored value of 84. Register 184 stores
Update the stored value with the addition result of. The accumulator 181
1 symbol by the adder 183 and the register 184
The cumulative addition of the phase error amount Δθ is performed for each clock. This
By cumulatively adding the phase error Δθ as shown in FIG.
The phase correction amount θ at that time. _TwoIs stored
Will be done. The accumulator 181 has the register 1
The phase correction amount θ at that time stored in
It is supplied to the intersection coordinate conversion circuit 182.

Here, register 184 of accumulator 181
(Register that holds the phase correction amount θ at that time)
Is the BPSK supplied from the timing control circuit 171.
The flag is input as an enable signal EN, and BPSK
Only when the flag is valid (1), the internal data is updated.

Therefore, updating of the phase error correction signals (RI, RQ) output from the NCO 174 is based on TAB, TM
This is performed only at the CC and burst positions, and the remaining phase correction amount is held at other positions. That is, this N
The CO 174 performs an intermittent operation such as changing the phase error correction signals (RI, RQ) only for the symbols modulated by BPSK.

The BPS input to the register 184
The K flag is input by the register 185 with a delay of one timing. This is because the register 184 is updated using the phase error amount Δθ ₂ updated by the filter 173 at the previous stage.

The orthogonal coordinate conversion circuit 182 performs a process of converting the phase correction amount θ output as angle data into a rectangular coordinate signal. For example, register 184 is
The quadrature coordinate signal is generated by using a conversion table configured to perform a remainder operation in degrees and convert the data output from the register 184 into rectangular coordinate data. The orthogonal coordinate conversion circuit 182 supplies the carrier correction unit 129 with a rotational phase correction signal (RI, RQ) obtained by converting the phase correction amount θ into a rectangular coordinate signal.

As described above, the carrier synchronizer 134 detects the phase error Δθ, filters and averages the detected phase error Δθ. Then, after accumulating the averaged phase error amount Δθ and converting it into a phase correction amount θ at that time, a rotational phase correction signal (RI, RQ) is generated. The carrier data error included in the transmission data (I, Q) is corrected by rotating the phase of the transmission data (I, Q) by the rotation phase correction signal (RI, RQ) obtained in this manner. It will be. When the carrier error is completely corrected, the phase error amount Δθ output from the filter 135 becomes 0, and the phase correction amount θ output from the accumulating circuit 181 keeps outputting a constant value. Become.

As described above, according to the embodiment of the present invention, BS /
In the CS digital broadcast shared receiving apparatus 100, two calculation of the phase error amount of the carrier synchronizer 134 are provided for BS and CS, and the subsequent filter 144 and NCO 145 are shared. In the case of receiving a BS digital broadcast, the phase error amount of the transmission data is calculated based on the BPSK modulation method, and only the TMCC, TAB, and burst signals are intermittently detected. On the other hand, in the case of receiving CS digital broadcasting, the phase error amount of the transmission data is set to QPSK.
It is calculated based on the modulation method.

As a result, shared receiving apparatus 100
Thus, the carrier waves of both the BS digital broadcast and the CS digital broadcast can be synchronized.

The embodiment in which the phase synchronization of the carrier is shared is described above. Similarly, by intermittently processing the carrier synchronization, the synchronization circuit of the carrier frequency can also be used for the BS digital broadcasting and the CS digital broadcasting. It can be shared with both broadcasting.

[0074]

In the receiving apparatus according to the present invention, the calculating unit for calculating the phase error amount of the carrier synchronizing unit is different from the one for the first broadcasting system and the one for the second broadcasting system.
And two for the broadcasting system. The first for the first broadcast system
The phase error calculation unit calculates the phase rotation error amount of the transmission data based on the BPSK modulation method. On the other hand, the second error calculator for the second broadcast system calculates the phase rotation error amount of the transmission data based on the QPSK modulation system. And
A common filter and rotation correction signal generator are used for the first broadcast system and the second broadcast system.

As a result, according to the present invention, the carrier waves of both the first broadcast system and the second broadcast system can be synchronized. For example, it is possible to synchronize the carrier waves of both the BS digital broadcast and the CS digital broadcast.

[Brief description of the drawings]

FIG. 1 is a block diagram of a BS / CS shared receiving apparatus to which the present invention is applied.

FIG. 2 is a configuration diagram of a demodulation unit of the BS / CS shared receiving device.

FIG. 3 is a diagram for explaining a superframe structure of BS digital broadcasting.

FIG. 4 is a diagram for explaining a frame structure of BS digital broadcasting.

FIG. 5 is a block diagram of a carrier synchronization section of the demodulation section.

FIG. 6 is a configuration diagram of a filter of the carrier synchronization unit.

FIG. 7 is a configuration diagram of an NCO of the carrier synchronization unit.

[Explanation of symbols]

101 demodulation unit, 134 carrier synchronization unit, 142 BS
Phase error detection circuit, 143 CS phase error detection circuit, 144 filter, 145 NCO

 ──────────────────────────────────────────────────の Continued on the front page F term (reference) 5C025 BA30 DA01 DA04 5K004 AA01 AA05 BA02 FA03 FA05 FA06 FG02 FH08 FJ17 5K047 AA15 CC08 EE02 HH01 HH12 MM13

Claims (2)

[Claims] 1. A first BPSK-modulated synchronization symbol.
A receiver for receiving digital broadcasting of the second broadcasting system in which all symbols are QPSK-modulated and timing synchronization means for performing synchronization processing of symbol timing of transmission data; and a first broadcasting system. When receiving a digital broadcast, a synchronization word is detected from transmission data that has been timing-synchronized, a frame synchronization unit that detects a frame synchronization timing of the transmission data, and a carrier synchronization unit that performs a synchronization process of a carrier, The carrier synchronization unit is a carrier correction unit that corrects a carrier error by complexly multiplying a transmission data consisting of a rectangular coordinate signal by a rotation correction signal, and is used when receiving a digital broadcast of the first broadcast system. The phase rotation error amount of the transmission data whose carrier error has been corrected by the carrier correction unit is BPSK modulated. A first phase error calculator that calculates the phase rotation error amount of the transmission data that is used when receiving a digital broadcast of the second broadcast system and has a carrier error corrected by the carrier correction unit; And a second phase error calculator that calculates the number of symbols from the frame synchronization timing, specifies at least the symbol position of the synchronization word, and determines the symbol position of the specified symbol. Filter the phase rotation error amount,
At the time of receiving the digital broadcast of the second broadcasting system, a filter for filtering the phase rotation error amount of all symbols, and the rotation correction signal whose frequency and phase are controlled according to the filtered phase rotation error amount, And a rotation correction signal generating unit for generating the rotation correction signal. 2. The digital broadcast of the first broadcast system is B
The receiving apparatus according to claim 1, wherein the receiving apparatus is an S digital broadcasting, and the digital broadcasting of the second broadcasting method is a CS digital broadcasting.