JP4098096B2 - Spread spectrum receiver - Google Patents

Description

【００３０】
そして、行列乗算部６では、上記部分相関複素信号ｅ_jと上記行列Ｄとを、下記（２）式に従い乗算し、直交符号系列ｄ₁〜ｄ_Pに関する直交相関複素信号ｉ_p（ｉ₁〜ｉ_P）を算出する。
【００３１】
【数２】

【００３２】
遅延器７−ｐ（ｐ∈｛１，２，…，Ｐ｝）では、上記直交相関複素信号ｉ_pに対してΔ時間だけ遅延を付加する。なお、Δは、０＜Δ＜２Ｔ_c´の値を有する。また、遅延器８−ｐ（ｐ∈｛１，２，…，Ｐ｝）では、上記直交相関複素信号ｉ_pに対してΔ／２時間だけ遅延を付加する。
【００３３】
一方、シンボル同期回路５では、部分相関器４−ｊから出力される部分相関複素信号ｅ₁〜ｅ_Jに基づいて、上記スペクトル拡散送信装置で用いたＰＮ符号との符号同期を行い、ＰＮ符号の発生周期に同期した再生シンボルクロックを出力する。
【００３４】
そして、ラッチ９では、行列乗算部６から出力された遅延が付加されていない直交相関複素信号ｉ₁〜ｉ_P，遅延器７−ｐから出力されたΔ時間だけ遅延が付加された直交相関複素信号ｉ₁〜ｉ_P，遅延器８−ｐから出力されたΔ／２時間だけ遅延が付加された直交相関複素信号ｉ₁〜ｉ_Pを、それぞれ上記再生シンボルクロックの立ち上がりエッジでラッチする。このとき、ＬＡＴＥ複素相関信号ＬＡ₁〜ＬＡ_P，ＥＡＲＬＹ複素相関信号ＥＡ₁〜ＥＡ_P，ＣＵＲＲＥＮＴ複素相関信号ＣＵ₁〜ＣＵ_Pを出力する。
【００３５】
ビタビ復号部１０では、上記ＣＵＲＲＥＮＴ複素相関信号ＣＵ₁〜ＣＵ_Pの実数成分を枝メトリックとして用いてビタビ復号を行い、その復号結果を復号データとして出力する。また、ビタビ復号部１０では、最尤状態および最尤状態から１シンボルトレースバックした時の状態から再符号化を行うことにより、受信信号に乗算されている直交符号系列の系列番号を推定し、その推定結果を第１の直交符号系列番号として出力する。なお、ここでいう直交符号系列番号は、直交符号系列ｄ₁〜ｄ_Pの添え字の数字を意味する。
【００３６】
最大電力検出部１１では、上記ＣＵＲＲＥＮＴ複素相関信号ＣＵ₁〜ＣＵ_Pの中から、絶対値の二乗値が最大となるものを選択し、選択したＣＵＲＲＥＮＴ複素相関信号の添え字の数字を第２の直交符号系列番号として出力する。
【００３７】
ＤＬＬ１２では、上記第１の直交符号系列番号または上記第２の直交符号系列番号のいずれかに対応するＬＡＴＥ複素相関信号とＥＡＲＬＹ複素相関信号とを用いて再生２倍チップクロックの進み／遅れを判定する。そして、その判定結果に基づいてクロック位相制御実施後の再生２倍チップクロックを出力する。
【００３８】
また、ＡＦＣ１３では、上記第１の直交符号系列番号または上記第２の直交符号系列番号のいずれかに対応するＣＵＲＲＥＮＴ複素相関信号を用いてキャリア周波数偏差を推定する。そして、その推定結果に基づいてキャリア周波数誤差信号を更新する。
【００３９】
また、ＣＲ１４では、上記第１の直交符号系列番号または上記第２の直交符号系列番号のいずれかに対応するＣＵＲＲＥＮＴ複素相関信号を用いてキャリア位相を推定する。そして、その推定結果に基づいてキャリア位相誤差信号を更新する。
【００４０】
つぎに、上記スペクトル拡散受信装置を構成する各回路の動作を、図面を用いて詳細に説明する。
【００４１】
図３は、上記同期検波部２の一構成例を示す図である。本実施の形態の同期検波部２は、搬送波発生器３１と、移相器（π／２）３２と、乗算器３３，３４と、ローパスフィルタ（ＬＰＦ）３５，３６と、アナログ／ディジタル変換器（Ａ／Ｄ）３７，３８と、位相回転部３９から構成される。
【００４２】
図３に示す同期検波部２では、搬送波発生器３１が、前述したスペクトル拡散送信装置の周波数変換部２８にて用いた搬送波とほぼ等しい周波数を有する正弦波を発生する。そして、乗算器３３にて搬送波発生器３１から出力される正弦波とアンテナ１で受信した信号とを乗算し、ＬＰＦ３５にてこの乗算により生成された信号の高調波成分を除去し、さらに、Ａ／Ｄ３７にてサンプリングする。これにより、複素スペクトル拡散信号の同相成分を生成する。同様に、乗算器３４にて、移相器３２でπ／２だけ移相された搬送波発生器３１出力の正弦波とアンテナ１で受信した信号とを乗算し、ＬＰＦ３６にてこの乗算により生成された信号の高調波成分を除去し、さらに、Ａ／Ｄ３８にてサンプリングする。これにより、複素スペクトル拡散信号の直交成分を生成する。
【００４３】
最後に、位相回転部３９が、複素スペクトル拡散信号に対する位相回転処理として、後述する高精度に生成されたキャリア周波数誤差信号に基づく周波数補正と、後述する高精度に生成されたキャリア位相誤差信号に基づく位相補正と、を行うことにより、複素ベースバンド信号を生成する。
【００４４】
このように、本実施の形態の同期検波部２では、ＡＦＣ１３から出力されたキャリア周波数誤差信号およびＣＲ１４から出力されたキャリア位相誤差信号を用いて同期検波を行うこととした。これにより、高精度なキャリア周波数同期特性およびキャリア位相同期特性を実現できる。
【００４５】
図４は、上記シンボル同期回路５の一構成例を示す図である。本実施の形態のシンボル同期回路５は、ラッチ４１と、電力算出回路（｜・｜²）４２−１〜４２−Ｊと、第１の加算器（Σ）４３と、第２の加算器４４と、フレームメモリ４５と、ピーク検出部４６と、遅延器（Δ／２）４７から構成される。
【００４６】
図４に示すシンボル同期回路５では、まず、ラッチ４１が、後述するＤＬＬ１２から出力される再生２倍チップクロックの立ち上がりエッジで、部分相関器４−１〜４−Ｊから出力される信号をラッチする。そして、電力算出回路４２−１〜４２−Ｊが、ラッチ４１から出力されるＪ個の信号の絶対値の二乗値を算出し、その算出結果として部分相関電力信号を出力する。
【００４７】
つぎに、第１の加算器４３が、上記部分相関電力信号の総和として相関電力信号を算出し、出力する。そして、第２の加算器４４とフレームメモリ４５が、相関電力信号に対して、受信側で用いたＰＮ符号の１繰返し周期で累積加算（巡回加算）を行う。
【００４８】
つぎに、ピーク検出部４６が、巡回加算結果がＰＮ符号の１繰返し周期内で最大となる位置に立ち上がりエッジを持つクロックを生成する。そして、遅延器４７が、受け取ったクロックに対してΔ／２だけ遅延を付加する。これにより、ＰＮ符号の１繰り返し周期と同じ周期を持ち、かつＣＵＲＲＥＮＴ複素相関信号のピークタイミングで立ち上がりエッジを有する、再生シンボルクロックを生成する。
【００４９】
このように、本実施の形態のシンボル同期回路５では、部分相関器４−１〜４−Ｊから出力される部分相関信号を、ＤＬＬ１２から出力される再生２倍チップクロックの立ち上がりエッジでラッチした信号を用いて、スペクトル拡散送信装置で用いたＰＮ符号との符号同期を行うこととした。これにより、ＣＵＲＲＥＮＴ複素相関信号のピークタイミングに高精度に同期した再生シンボルクロックを生成できる。
【００５０】
図５は、上記ビタビ復号部１０の一構成例を示す図である。本実施の形態のビタビ復号部１０は、実数成分抽出部（Ｒｅ（・））５１−１〜５１−Ｐと、パスメトリック算出部５２と、パスメモリ５３と、パスメトリックメモリ５４と、最尤状態検出部５５と、トレースバック部５６と、再符号化部５７から構成される。
【００５１】
図５に示すビタビ復号部１０では、まず、実数成分抽出部５１−１〜５１−Ｐが、ラッチ９から出力されるＣＵＲＲＥＮＴ複素相関信号ＣＵ₁〜ＣＵ_Pの実数成分である枝メトリック値をそれぞれ出力する。
【００５２】
つぎに、パスメトリック算出部５２が、各状態遷移における１シンボル前のパスメトリック値と各状態遷移に対応する枝メトリック値とを加算し、１シンボル前の状態から遷移するパスの中から最尤パスを選択し、その最尤パスの各状態のパスメトリック値をパスメトリックメモリ５４に格納する。また、各々の状態で選択された最尤パスへ到達するためのパス情報をパスメモリ５３に格納する。
【００５３】
つぎに、最尤状態検出部５５が、全状態に対するパスメトリック値に基づいて最尤状態を検出する。そして、トレースバック部５６が、最尤状態検出部５５にて検出された最尤状態を起点として、パスメモリ５３内のパス情報を用いてＱシンボル分のトレースバックを行い、復号データを出力する。なお、Ｑは、１以上の自然数であり、前述したスペクトル拡散送信装置の畳込み符号化部２２で用いられる拘束長の４〜５倍程度の値である。また、トレースバック部５６は、最尤状態の状態番号と最尤状態から１シンボル分トレースバックした時の状態番号を出力する。
【００５４】
最後に、再符号化部５７が、トレースバック部５６から出力される最尤状態の状態番号と最尤状態から１シンボル分トレースバックした時の状態の状態番号から得られるデータ系列を、上記畳込み符号化部２２で畳込み符号化を行う際に用いた生成多項式で再符号化することにより、受信信号に乗算されている直交符号系列番号を推定し、その推定結果として第１の直交符号系列番号を出力する。
【００５５】
このように、本実施の形態のビタビ復号部１０は、ＣＵＲＲＥＮＴ複素相関信号ＣＵ₁〜ＣＵ_Pを用いて、Ｋビット毎にブロック化したビタビ復号を行うこととした。これにより、復号データとともに、受信信号に乗算されている直交符号系列の系列番号を得ることができる。
【００５６】
図６は、上記最大電力検出部１１の一構成例を示す図である。本実施の形態の最大電力検出部１１は、電力算出回路（｜・｜²）６１−１〜６１−Ｐと、最大状態番号検出部６２から構成される。
【００５７】
図６に示す最大電力検出部１１では、まず、電力算出回路６１−１〜６１−Ｐが、ラッチ９から出力されるＣＵＲＲＥＮＴ複素相関信号（ＣＵ₁〜ＣＵ_Pのいずれか）の絶対値の二乗値を算出し、その算出結果としてＣＵＲＲＥＮＴ相関電力信号を出力する。
【００５８】
つぎに、最大状態番号検出部６２が、電力算出回路６１−１〜６１−Ｐにて算出されたＰ個のＣＵＲＲＥＮＴ相関電力信号から相関電力が最大となる信号を検出し、その最大信号に対応する直交符号系列の系列番号を第２の直交符号系列番号として出力する。
【００５９】
このように、本実施の形態の最大電力検出部１１では、ＣＵＲＲＥＮＴ複素相関信号ＣＵ₁〜ＣＵ_Pから相関電力が最大となる信号を検出し、その信号に対応する直交符号系列の系列番号を出力することとした。これにより、前述のビタビ復号部１０とは異なる処理で、受信信号に乗算されている直交符号系列の系列番号を得ることができる。
【００６０】
図７は、遅延ロックループ（ＤＬＬ）１２の一構成例を示す図である。本実施の形態の遅延ロックループ１２は、直交符号系列番号選択部７１と、電力算出回路（｜・｜）７２−１〜７２−Ｐ，７３−１〜７３−Ｐと、セレクタ７４，７５と、減算器７６と、ループフィルタ７７と、電圧制御発振器（ＶＣＯ）７８から構成される。
【００６１】
図７に示すＤＬＬ１２では、まず、直交符号系列番号選択部７１が、ビタビ復号部１０から出力される第１の直交符号系列番号、または最大電力検出部１１から出力される第２の直交符号系列番号、のいずれか一方を適切に選択し、選択した番号を選択直交符号系列番号として出力する。
【００６２】
一方、電力算出回路７２−１〜７２−Ｐが、ラッチ９から出力されるＬＡＴＥ複素相関信号（ＬＡ₁〜ＬＡ_Pのいずれか）の絶対値の二乗値を算出し、その算出結果としてＬＡＴＥ相関電力信号を出力する。同様に、電力算出回路７３−１〜７３−Ｐが、ラッチ９から出力されるＥＡＲＬＹ複素相関信号（ＥＡ₁〜ＥＡ_Pのいずれか）の絶対値の二乗値を算出し、その算出結果としてＥＡＲＬＹ相関電力信号を出力する。
【００６３】
つぎに、セレクタ７４が、直交符号系列番号選択部７１から出力される選択直交符号系列番号に対応するＬＡＴＥ相関電力信号を選択して出力する。同様に、セレクタ７５が、上記選択直交符号系列番号に対応するＥＡＲＬＹ相関電力信号を選択して出力する。
【００６４】
つぎに、減算器７６が、セレクタ７４出力のＬＡＴＥ相関電力信号からセレクタ７５出力のＥＡＲＬＹ相関電力信号を減算し、その結果としてクロック誤差信号を生成する。たとえば、フェージングや熱雑音が無いという条件において、クロック誤差信号の値が０より大きい場合は、ＶＣＯ７８が出力している再生２倍チップクロックのクロック位相が進んでいることを表し、また、クロック誤差信号の値が０より大きい場合は、再生２倍チップクロックのクロック位相が進んでいることを表し、また、クロック誤差信号の値が０の場合は、再生２倍チップクロックのクロック位相が受信信号に乗算されている直交符号系列周期に対して完全に同期していることを表す。
【００６５】
つぎに、ループフィルタ７７が、上記のような特性を有するクロック誤差信号の平均化を行い、上記再生２倍チップクロックのクロック位相の進みまたは遅れを高精度に求める。つぎに、ＶＣＯ７８が、高精度に求められたクロック位相の進みまたは遅れに基づいて、再生２倍チップクロックが受信信号に乗算されている直交符号系列周期に同期するようにクロック位相制御を行う。そして、その結果として、チップクロックの２倍のクロック速度を有する再生２倍チップクロックを出力する。
【００６６】
このように、本実施の形態のＤＬＬ１２では、適切に選択された選択直交符号系列番号のＬＡＴＥ相関電力信号とＥＡＲＬＹ相関電力信号とを用いて再生２倍チップクロックのクロック位相の進みまたは遅れを算出することとした。これにより、高精度に符号同期追従を行うことができる。また、高精度な符号同期追従を実現できるため、良好な復号特性を得ることができる。
【００６７】
図８は、上記直交符号系列番号選択部７１の一構成例を示す図である。本実施の形態の直交符号系列番号選択部７１は、カウンタ８１と、しきい値比較部８２と、セレクタ８３から構成される。
【００６８】
図８に示す直交符号系列番号選択部７１では、まず、カウンタ８１が、シンボル同期回路５における拡散符号初期同期完了時からの時間をカウントする。
【００６９】
つぎに、しきい値比較部８２は、カウンタ値がしきい値Ｔ_thより小さい場合、最大電力検出部１１から出力される第２の直交符号系列番号を選択するための選択信号を出力し、一方、カウンタ値がしきい値Ｔ_th以上の場合は、ビタビ復号部１０から出力される第１の直交符号系列番号を選択するための選択信号を出力する。すなわち、第１の直交符号系列番号は、キャリア位相同期が確立されるまで正しい出力結果が得られないため、キャリア位相非同期時は、キャリア位相の同期／非同期に関係なく直交符号系列の推定が可能な第２の直交符号系列番号を選択する。また、キャリア位相同期時は、第１の直交符号系列番号の方が第２の直交符号系列番号よりも、符号化利得により誤判定確率が小さくなるため、第１の直交符号系列番号を選択する。したがって、しきい値Ｔ_thは、シンボル同期回路５における拡散符号初期同期完了からＣＲ１４におけるキャリア位相同期成立までに要する時間程度が適切である。
【００７０】
最後に、セレクタ８３が、しきい値比較部８２から出力される選択信号に従い、第１の直交符号系列番号または第２の直交符号系列番号のいずれか一方を選択して出力する。
【００７１】
図９は、直交符号系列番号選択部７１の動作を示すタイミングチャートである。図９で示されるように、直交符号系列番号選択部７１は、拡散符号初期同期完了時を起点としたしきい値Ｔ_thを用いて、第１の直交符号系列番号と第２の直交符号系列番号の出力を切り換える。
【００７２】
このように、本実施の形態の直交符号系列番号選択部７１では、拡散符号初期同期完了からキャリア位相同期成立までに要する時間を所定のしきい値とし、このしきい値に基づいて第１の直交符号系列番号と第２の直交符号系列番号の出力を切り換えることとした。これにより、常に適切な直交符号系列番号を選択することができる。
【００７３】
図１０は、上記自動周波数制御回路（ＡＦＣ）１３の一構成例を示す図である。本実施の形態のＡＦＣ１３は、先に説明した直交符号系列番号選択部７１と、セレクタ１０１と、遅延器（Ｔ_s´）１０２と、複素共役算出部（＊）１０３と、複素乗算器１０４と、ループフィルタ１０５と、逆正接部（Ｔａｎ^-1）１０６から構成される。
【００７４】
図１０に示すＡＦＣ１３では、まず、直交符号系列番号選択部７１が、ビタビ復号部１０から出力される第１の直交符号系列番号、または最大電力検出部１１から出力される第２の直交符号系列番号、のいずれか一方を適切に選択し、選択した番号を選択直交符号系列番号として出力する。
【００７５】
つぎに、セレクタ１０１が、ＣＵＲＲＥＮＴ複素相関信号ＣＵ₁〜ＣＵ_Pの中から、直交符号系列番号選択部７１から出力される選択直交符号系列番号に対応するＣＵＲＲＥＮＴ複素相関信号を選択して出力する。
【００７６】
つぎに、遅延器１０２が、セレクタ１０１から出力される信号に対して１シンボルに相当する遅延を付加する。そして、複素共役算出部１０３が、１シンボル遅延付加後の信号の複素共役を出力する。
【００７７】
つぎに、複素乗算器１０４が、セレクタ１０１から出力される現在の信号と、１シンボル前の信号の複素共役値と、を複素乗算することにより、１シンボル遅延検波を行う。なお、１シンボル遅延検波結果である遅延検波複素信号の位相は、周波数偏差による１シンボル当りの位相回転量を意味する。
【００７８】
つぎに、ループフィルタ１０５が、複素乗算器１０４から出力される遅延検波複素信号の平均化を行い、さらに、逆正接部１０６が、平均化後の遅延検波複素信号の位相を算出することにより、周波数偏差による１シンボル当りの位相回転量を示すキャリア周波数誤差信号を高精度に求める。
【００７９】
このように、本実施の形態のＡＦＣ１３では、適切に選択された選択直交符号系列番号に対応するＣＵＲＲＥＮＴ複素相関信号を用いて周波数誤差推定を行うこととした。これにより、高精度にキャリア周波数誤差信号を算出することができる。また、同期検波部２がこの高精度なキャリア周波数誤差信号を用いて周波数同期制御を行っているため、良好な周波数同期特性を得ることができる。さらに、同期検波部２において良好な周波数同期特性を実現できるため、さらに良好な復号特性を得ることができる。
【００８０】
図１１は、キャリア再生回路（ＣＲ）１４の一構成例を示す図である。本実施の形態のＣＲ１４は、先に説明した直交符号系列番号選択部７１およびセレクタ１０１と、ループフィルタ１１１と、逆正接部（Ｔａｎ^-1）１１２から構成される。
【００８１】
図１１に示すＣＲ１４では、まず、直交符号系列番号選択部７１が、ビタビ復号部１０から出力される第１の直交符号系列番号、または最大電力検出部１１から出力される第２の直交符号系列番号、のいずれか一方を適切に選択し、選択した番号を選択直交符号系列番号として出力する。
【００８２】
つぎに、セレクタ１０１が、ＣＵＲＲＥＮＴ複素相関信号ＣＵ₁〜ＣＵ_Pの中から、直交符号系列番号選択部７１から出力される選択直交符号系列番号に対応するＣＵＲＲＥＮＴ複素相関信号を選択して出力する。なお、このセレクタ１０１から出力される複素信号の位相は、同期検波部２で用いているキャリア位相に対する位相誤差を意味する。
【００８３】
つぎに、ループフィルタ１１１が、セレクタ１０１から出力される複素信号の平均化を行い、逆正接部１１２が、平均化後の複素信号の位相を算出することにより、キャリア位相誤差を示すキャリア位相誤差信号を高精度に求める。
【００８４】
このように、本実施の形態のＣＲ１４では、適切に選択された選択直交符号系列番号に対応するＣＵＲＲＥＮＴ複素相関信号を用いてキャリア位相推定を行う。これにより、高精度にキャリア位相誤差信号を算出することができる。また、同期検波部２がこの高精度なキャリア位相誤差信号を用いてキャリア位相同期を行っているため、良好なキャリア位相同期特性を得ることができる。さらに、同期検波部２において良好なキャリア位相同期特性を実現できるため、さらに良好な復号特性を得ることができる。
【００８５】
以上、本実施の形態においては、ビタビ復号により得られるデータ系列を送信側で用いた生成多項式により再符号化した信号に基づいて推定された直交符号系列の系列番号（第１の直交符号系列番号）と、相関電力が最大となるＣＵＲＲＥＮＴ複素相関信号に対応する直交符号系列の系列番号（第２の直交符号系列番号）と、のいずれか一方を適切に選択して、符号同期追従処理，周波数同期制御，キャリア位相同期制御を行うこととした。これにより、高精度な同期追従特性、高精度なキャリア周波数同期特性および高精度なキャリア位相同期特性を実現できる。
【００８６】
なお、本実施の形態のスペクトル拡散受信装置においては、各直交符号系列ｄ₁〜ｄ_Pについて特定していないが、たとえば、Ｗａｌｓｈ関数によって特定されるＷａｌｓｈ系列を適用することとしてもよい。これにより、行列乗算部６における行列演算に高速アダマール変換を適用することが可能となり、スペクトル拡散受信装置の回路規模を削減することができる。
【００８７】
また、本実施の形態のスペクトル拡散受信装置においては、符号同期追従を行うクロックとして、チップクロックの２倍のクロック速度を有する再生２倍チップクロックを用いたが、これに限らず、チップレートの２倍以上のクロック速度であれば、他のクロックを用いてもよい。
【００８８】
また、本実施の形態のスペクトル拡散受信装置の遅延ロックループ１２においては、ＬＡＴＥ複素相関信号ＬＡ₁〜ＬＡ_PとＥＡＲＬＹ複素相関信号ＥＡ₁〜ＥＡ_Pの絶対値の二乗値を算出後に、選択直交符号系列番号に対応したＬＡＴＥ相関電力信号とＥＡＲＬＹ相関電力信号を選択しているが、これに限らず、選択直交符号系列番号に対応するＬＡＴＥ複素相関信号とＥＡＲＬＹ複素相関信号を選択した後に、選択された信号の絶対値の二乗値を算出することとしてもよい。
【００８９】
また、本実施の形態のスペクトル拡散受信装置のＡＦＣ１３においては、遅延器１０２の遅延量を１シンボルとしたが、これに限らず、たとえば、遅延量をｈシンボル（ｈは２以上の自然数）としてもよい。この場合は、ｈシンボル遅延検波を行った結果からキャリア周波数誤差信号を生成する。
【００９０】
また、本実施の形態のスペクトル拡散受信装置のビタビ復号部１０においては、最尤状態からＵシンボル分トレースバックした時の状態番号と、最尤状態から（Ｕ＋１）シンボル分トレースバックした時の状態番号と、からＵシンボル前の受信信号に乗算されている直行符号系列番号を推定することとしてもよい。ただし、Ｕは１以上の自然数とする。
【００９１】
実施の形態２．
図１２は、実施の形態２の同期検波部２の一構成例を示す図である。なお、本実施の形態では、先に説明した実施の形態１とは動作の異なる、同期検波部２の動作についてのみ説明する。その他の構成については、実施の形態１と同様であるため同一の符号を付してその説明を省略する。
【００９２】
図１２に示す同期検波部２では、まず、搬送波発生器１２１が、ＡＦＣ１３から出力されるキャリア周波数誤差信号を打ち消す周波数補正と、ＣＲ１４から出力されるキャリア位相誤差信号を打ち消す位相補正と、が行われた後の正弦波を出力する。
【００９３】
そして、乗算器３３にて搬送波発生器１２１から出力される正弦波とアンテナ１で受信した信号とを乗算し、ＬＰＦ３５にてこの乗算により生成された信号の高調波成分を除去し、さらに、Ａ／Ｄ３７にてサンプリングする。これにより、複素スペクトル拡散信号の同相成分を生成する。同様に、乗算器３４にて、移相器３２でπ／２だけ移相された搬送波発生器１２１出力の正弦波とアンテナ１で受信した信号とを乗算し、ＬＰＦ３６にてこの乗算により生成された信号の高調波成分を除去し、さらに、Ａ／Ｄ３８にてサンプリングする。これにより、複素スペクトル拡散信号の直交成分を生成する。そして、同期検波部２では、上記同相成分と直交成分からなる複素ベースバンド信号を出力する。
【００９４】
このように、本実施の形態の同期検波部２では、ＡＦＣ１３から出力されたキャリア周波数誤差信号およびＣＲ１４から出力されたキャリア位相誤差信号を用いて同期検波を行うこととした。これにより、実施の形態１と同様に、高精度なキャリア周波数同期特性およびキャリア位相同期特性を実現できる。
【００９５】
実施の形態３．
図１３は、実施の形態３の直交符号系列番号選択部７１の一構成例を示す図である。本実施の形態の直交符号系列番号選択部７１は、実数成分抽出部１３１−１〜１３１−Ｐと、セレクタ１３２，１３５と、平均化部１３３と、しきい値比較部１３４から構成される。なお、本実施の形態では、先に説明した実施の形態１および２とは動作の異なる、直交符号系列番号選択部７１の動作についてのみ説明する。その他の構成については、実施の形態１または２と同様であるため同一の符号を付してその説明を省略する。
【００９６】
図１３に示す直交符号系列番号選択部７１では、まず、実数成分抽出部１３１−１〜１３１−Ｐが、ラッチ９から出力されるＣＵＲＲＥＮＴ複素相関信号（ＣＵ₁〜ＣＵ_Pのいずれか）の実数成分を出力する。
【００９７】
つぎに、セレクタ１３２が、ビタビ復号部１０から出力される第１の直交符号系列番号に対応するＣＵＲＲＥＮＴ複素相関信号の実数成分を出力する。そして、平均化部１３３が、セレクタ１３２の出力信号に対して平均化を行い、平均結果として平均ＣＵＲＲＥＮＴ実数信号ＡＣ_rを出力する。この平均ＣＵＲＲＥＮＴ実数信号は、キャリア位相同期成立前のときに小さい値を有し、キャリア位相同期成立後には大きい値を有する。
【００９８】
つぎに、しきい値比較部１３４が、上記平均ＣＵＲＲＥＮＴ実数信号値ＡＣ_rと所定の閾値ＡＣ_thとを比較する。たとえば、「ＡＣ_r＜ＡＣ_th（キャリア位相非同期）」の場合には、キャリア位相の同期／非同期に関係なく直交符号系列の推定が可能な第２の直交符号系列番号を選択するための選択信号を出力する。一方、ＡＣ_r≧ＡＣ_th（キャリア位相同期）」の場合には、第１の直交符号系列番号の方が第２の直交符号系列番号よりも、符号化利得により誤判定確率が小さくなるため、第１の直交符号系列番号を選択するための選択信号を出力する。
【００９９】
最後に、セレクタ１３５が、しきい値比較部１３４から出力される選択信号に従い、第１の直交符号系列番号または第２の直交符号系列番号のいずれか一方を選択して出力する。
【０１００】
図１４は、上記直交符号系列番号選択部７１の動作を示すタイミングチャートである。図１４で示されるように、キャリア位相の同期／非同期を判定し、その判定結果に基づいて第１の直交符号系列番号と第２の直交符号系列番号を切り換える。
【０１０１】
このように、本実施の形態における直交符号系列番号選択部７１では、キャリア位相の同期／非同期を判定し、この判定結果に基づいて第１の直交符号系列番号と第２の直交符号系列番号の出力を切り換えることとした。これにより、常に適切な直交符号系列番号を選択することができる。
【０１０２】
なお、本実施の形態のスペクトル拡散受信装置の直交符号系列番号選択部７１においては、ＣＵＲＲＥＮＴ複素相関信号ＣＵ₁〜ＣＵ_Pの実数成分抽出後に、選択直交符号系列番号に対応するＣＵＲＲＥＮＴ複素相関信号の実数成分を選択したが、これに限らず、選択直交符号系列番号に対応するＣＵＲＲＥＮＴ複素相関信号を選択した後に、選択したＣＵＲＲＥＮＴ複素相関信号の実数成分を抽出することとしてもよい。
【０１０３】
【発明の効果】
以上、説明したとおり、本発明によれば、復号データを送信側で用いた生成多項式により再符号化した信号に基づいて推定された直交符号系列の系列番号と、相関電力が最大となる標本化後の第３の直交相関値（ＣＵＲＲＥＮＴ複素相関信号）に対応する直交符号系列の系列番号と、のいずれか一方を適切に選択し、その選択結果に基づいて符号同期追従処理、周波数同期制御、キャリア位相同期制御を行うこととした。これにより、高精度な同期追従特性、高精度なキャリア周波数同期特性および高精度なキャリア位相同期特性を実現できる、という効果を奏する。
【図面の簡単な説明】
【図１】 本発明にかかるスペクトル拡散受信装置の構成を示す図である。
【図２】 スペクトル拡散送信装置の構成を示す図である。
【図３】 実施の形態１の同期検波部の一構成例を示す図である。
【図４】 シンボル同期回路の一構成例を示す図である。
【図５】 ビタビ復号部の一構成例を示す図である。
【図６】 最大電力検出部の一構成例を示す図である。
【図７】 遅延ロックループ（ＤＬＬ）の一構成例を示す図である。
【図８】 実施の形態１の直交符号系列番号選択部の一構成例を示す図である。
【図９】 直交符号系列番号選択部の動作を示すタイミングチャートである。
【図１０】 自動周波数制御回路（ＡＦＣ）の一構成例を示す図である。
【図１１】 キャリア再生回路（ＣＲ）の一構成例を示す図である。
【図１２】 実施の形態２の同期検波部の一構成例を示す図である。
【図１３】 実施の形態３の直交符号系列番号選択部の一構成例を示す図である。
【図１４】 直交符号系列番号選択部の動作を示すタイミングチャートである。
【符号の説明】
１ 受信アンテナ、２ 同期検波部、３−１，３−２，３−（Ｊ−１），７−１，７−２，７−Ｐ，８−１，８−２，８−Ｐ 遅延器、４−１，４−Ｊ 部分相関器、５ シンボル同期回路、６ 行列乗算部、９ ラッチ、１０ ビタビ復号部、１１ 最大電力検出部、１２ 遅延ロックループ（ＤＬＬ）、１３ 自動周波数制御回路（ＡＦＣ）、１４ キャリア再生回路（ＣＲ）、３１ 搬送波発生器、３２ 移相器（π／２）、３３，３４ 乗算器、３５，３６ ローパスフィルタ（ＬＰＦ）、３７，３８ アナログ／ディジタル変換器（Ａ／Ｄ）、３９位相回転部、４１ ラッチ、４２−１，４２−２，４２−Ｊ 電力算出回路（｜・｜²）、４３ 第１の加算器（Σ）、４４ 第２の加算器、４５ フレームメモリ、４６ ピーク検出部、４７ 遅延器（Δ／２）、５１−１，５１−２，５１−Ｐ 実数成分抽出部（Ｒｅ（・））、５２ パスメトリック算出部、５３パスメモリ、５４ パスメトリックメモリ、５５ 最尤状態検出部、５６ トレースバック部、５７ 再符号化部、６１−１，６１−２，６１−Ｐ 電力算出回路（｜・｜²）、６２ 最大状態番号検出部、７１ 直交符号系列番号選択部、７２−１，７２−２，７２−Ｐ，７３−１，７３−２，７３−Ｐ 電力算出回路（｜・｜）、７４，７５ セレクタ、７６ 減算器、７７ ループフィルタ、７８ 電圧制御発振器（ＶＣＯ）、８１ カウンタ、８２ しきい値比較部、８３ セレクタ、１０１ セレクタ、１０２ 遅延器（Ｔ_s´）、１０３ 複素共役算出部（＊）、１０４ 複素乗算器、１０５ ループフィルタ、１０６ 逆正接部（Ｔａｎ^-1）、１１１ ループフィルタ、１１２ 逆正接部（Ｔａｎ^-1）、１２１ 搬送波発生器、１３１−１，１３１−２，１３１−Ｐ 実数成分抽出部、１３２，１３５ セレクタ、１３３ 平均化部、１３４ しきい値比較部。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a spread spectrum receiver used in a spread spectrum wireless communication system, and in particular, can achieve highly accurate clock synchronization tracking, carrier frequency synchronization, and carrier phase synchronization in the M-ary / SS system. The present invention relates to a spread spectrum receiver.
[0002]
[Prior art]
A conventional spread spectrum receiver will be described below. In recent years, in a mobile communication system and a satellite communication system, a spread spectrum system (hereinafter referred to as an SS system, SS: Spread Spectrum) has attracted attention as one of transmission systems for images, sounds, data, and the like. Among the SS systems, the “M-ary / SS system”, which is a transmission system suitable for increasing the transmission speed, has been actively studied.
[0003]
In the M-ary / SS system, 2 ^K A plurality of orthogonal code sequences (hereinafter referred to as orthogonal code sequences) are stored in advance in both the transmission device and the reception device. At this time, the transmission apparatus sequentially generates a data sequence of K bit units (K ≧ 2) from the information signal, and performs wireless transmission by replacing each data sequence with a predetermined orthogonal code sequence associated in advance. In the M-ary / SS system, a K-bit information signal can be transmitted in one cycle of the orthogonal code sequence.
[0004]
Here, a conventional transmission apparatus adopting the M-ary / SS system will be described. In a conventional M-ary / SS transmission apparatus, first, binary information data is generated, and the generated binary information data is converted into parallel binary information data of K (K is a natural number of 2 or more) bits. Here, the generation speed of the binary information data is called an information rate, and the value of the generation speed of the binary information data is R _i Is written. The generation rate of K-bit parallel binary information data is called a symbol rate, and the symbol rate value is R _s (= R _i / K). And symbol rate R _s The period of the clock with the symbol period T _s (= 1 / R _s ).
[0005]
Thereafter, in the transmission device, T _s Each time, an orthogonal code sequence having a length of J bits corresponding to the parallel binary information data (K bits) is ^K Send from among. Therefore, the transmission signal is 1 / (R _s A signal having a signal change point with a period of × J). In the following, the speed having this signal change point is expressed as the chip rate R. _c (= R _s XJ), and the period having this signal change point is the chip period T _c (= 1 / (R _s × J)).
[0006]
Thus, the conventional transmission apparatus can perform K-bit data transmission per symbol by performing spread spectrum transmission using the J-bit orthogonal code sequence.
[0007]
On the other hand, a conventional receiving apparatus performs code synchronization tracking on an orthogonal code sequence multiplied by a received signal using a delay lock loop (DLL) (see Non-Patent Document 1).
[0008]
In the conventional M-ary / SS delay lock loop, the previously stored orthogonal code sequence is output once per symbol with reference to a predetermined reproduction symbol clock. At this time, an orthogonal code sequence delayed by Δ / 2 and Δ time is also output. Δ is 0 <Δ <2T _c Has the value of Then, the orthogonal code sequence and the delayed orthogonal code sequence are multiplied by the received signal. Here, the multiplication result of the orthogonal code sequence delayed by Δ / 2 and the received signal is called a CURRENT signal, and this CURRENT signal is used when performing demodulation processing. The multiplication result of the orthogonal code sequence without delay and the received signal is called a LATE signal, the multiplication result of the orthogonal code sequence delayed by Δ and the received signal is called an EARLY signal, and these LATE signal and EARLY signal Is used when calculating the advance or delay of the clock phase of the reproduced symbol clock.
[0009]
Next, in the delay locked loop, the value of the EARLY signal is subtracted from the value of the LATE signal for each orthogonal code sequence. For example, when the transmitting side transmits an orthogonal code sequence under the condition that there is no fading or thermal noise, the subtraction result indicates that the clock phase of the recovered symbol clock is ahead of the orthogonal code sequence period when greater than 0, In addition, when it is smaller than 0, it indicates that the clock phase is behind the orthogonal code sequence period, and when it is 0, the clock phase is completely synchronized with the orthogonal code sequence period multiplied by the received signal. Represents that On the other hand, despreading is performed by integrating the CURRENT signal for each symbol.
[0010]
In the delay lock loop, when the integration result is equal to or greater than a predetermined threshold value, the subtraction result is output as it is as a clock error signal. On the other hand, when it is smaller than the threshold value, 0 is output as a clock error signal. (Process for determining whether or not a predetermined orthogonal code sequence is included in the received signal). Thereby, the phase control of the reproduction symbol clock can be performed using the LATE signal and the EARLY signal including the signal component.
[0011]
[Non-Patent Document 1]
Transactions of the IEICE 84/5 Vol.J67-B No.5 pp.559-565, "Synchronous loop for code-shift keying modulated spread spectrum communication"
[0012]
[Problems to be solved by the invention]
However, in the conventional M-ary / SS delay lock loop, when the received signal has a low S / N ratio, the above-mentioned “determines whether a predetermined orthogonal code sequence is included in the received signal. In the “processing”, there is a problem in that the synchronization tracking characteristic is deteriorated because an erroneous determination probability increases.
[0013]
The present invention has been made in view of the above, and by reducing the erroneous determination probability of “a process for determining whether or not a predetermined orthogonal code sequence is included in a received signal”, high accuracy can be achieved. An object of the present invention is to obtain a spread spectrum receiver capable of realizing the synchronization tracking characteristic.
[0014]
It is another object of the present invention to obtain a spread spectrum receiver capable of realizing a high-accuracy synchronization tracking characteristic and a higher-accuracy carrier frequency synchronization characteristic and carrier phase synchronization characteristic.
[0015]
[Means for Solving the Problems]
In order to solve the above-described problems and achieve the object, the spread spectrum receiver according to the present invention includes a complex code and a complex code obtained by dividing a spread code by a predetermined number of bits into a specified number of orthogonal code sequences. Correlation value calculation means for calculating the prescribed number of first orthogonal correlation values by multiplying the correlation value with the baseband signal, and the same delay amount is added to each of the first orthogonal correlation values Generating a second orthogonal correlation value and a third orthogonal correlation value to which a half of the delay amount is added, and thereafter, the predetermined number of first, second and third orthogonal correlation values are set at the transmission side Sampling means for sampling using a regenerated symbol clock synchronized with the repetition cycle of the spread code, a decoding process for the third orthogonal correlation value after the sampling, and a signal obtained by re-encoding the decoded data Multiply the received signal based on Sequence number estimating means for estimating a sequence number of the orthogonal code sequence (first orthogonal code sequence number), and an orthogonal code sequence corresponding to the sampled third orthogonal correlation value that maximizes the correlation power A sequence number detecting means for detecting a sequence number (second orthogonal code sequence number) and either the first or second orthogonal code sequence number are selected, and the sampled data corresponding to the selection result Clock adjusting means for adjusting the reproduced symbol clock based on the first and second orthogonal correlation values.
[0016]
According to the present invention, for example, the first orthogonal code sequence number estimated based on the signal obtained by re-encoding the decoded data using the generator polynomial used on the transmission side, and the first sample after sampling that maximizes the correlation power By appropriately selecting any one of the second orthogonal code sequence numbers corresponding to the 3 orthogonal correlation values and performing the code synchronization tracking process, a highly accurate synchronization tracking characteristic is realized.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a spread spectrum receiver according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.
[0018]
Embodiment 1 FIG.
In the present embodiment, a sequence number of an orthogonal code sequence estimated based on a signal obtained by re-encoding (using a generator polynomial used on the transmission side) a data sequence obtained by Viterbi decoding (a first orthogonal code sequence described later) Number) and a sequence number of an orthogonal code sequence corresponding to the CURRENT complex correlation signal with the maximum correlation power (second orthogonal code sequence number to be described later). Realizes highly accurate carrier frequency synchronization characteristics and highly accurate carrier phase synchronization characteristics.
[0019]
FIG. 1 is a diagram showing a configuration of a spread spectrum receiving apparatus according to the present invention. The spread spectrum receiving apparatus of the present embodiment includes a receiving antenna 1, a synchronous detection unit 2, delay units 3-1 to 3- (J-1), 7-1 to 7-P, and 8-1 to 8- P, partial correlators 4-1 to 4-J, symbol synchronization circuit 5, matrix multiplication unit 6, latch 9, Viterbi decoding unit 10, maximum power detection unit 11, and delay locked loop (DLL) 12, an automatic frequency control circuit (AFC) 13, and a carrier reproduction circuit (CR) 14. Note that J represents the code length of the orthogonal code sequence.
[0020]
Here, before explaining the spread spectrum transmission apparatus according to the present invention, the operation on the spread spectrum transmission apparatus side will be described. FIG. 2 is a diagram illustrating a configuration of the spread spectrum transmission apparatus. In the spread spectrum transmitter, first, the data generation unit 21 generates binary information data. Here, the generation speed of the binary information data is called an information rate, and the value of the generation speed of the binary information data is R _i Is written. Then, the convolutional coding unit 22 performs convolutional coding at the coding rate r (0 <r <1) on the binary information data, and the generation rate R _b (= R _i / R) to output binary data.
[0021]
In the serial-parallel converter 23, the generation speed R _b 2 is converted into parallel binary data of K (K is a natural number of 2 or more) bits. Here, the generation rate of parallel binary data of K bits is called a symbol rate, and the symbol rate value is R _s '(= R _b / K). And symbol rate R _s The period of the clock with ′ is the symbol period T _s ′ (= 1 / R _s ')).
[0022]
In the orthogonal function encoding unit 24, T _s ′, An orthogonal code sequence having a length of J bits corresponding to the parallel binary data is represented by 2 ^K Output from the list. On the other hand, in the PN code generator 26, the R generated by the clock generator 25 _s A PN code having a repetition cycle of L chips is generated at a clock cycle having a clock speed of '× L. Here, the speed of the clock generated by the clock generator 25 is set to the chip rate R. _c '(= LR _s ') And chip rate R _c The period of the clock with ′ is the chip period T _c ′ (= 1 / R _c '). Here, for simplification of description, the description will be made assuming that the repetition period L chip of the PN code is an integer multiple of the repetition period J bits of the orthogonal code sequence.
[0023]
The spread modulation unit 27 generates a transmission SS signal by multiplying the orthogonal code sequence output from the orthogonal function encoding unit 24 by the PN code output from the PN code generation unit 26. The frequency conversion unit 28 performs frequency conversion by multiplying the transmission SS signal output from the spread modulation unit 27 by a carrier wave, and the power amplification unit 29 performs power conversion of the transmission SS signal after frequency conversion. The transmission signal generated by amplifying the signal is transmitted from the transmission antenna 30.
[0024]
As described above, the spread spectrum transmission apparatus performs spread spectrum transmission using the orthogonal code sequence, thereby performing the information rate R. _i The binary information data is transmitted to the receiving device.
[0025]
Next, the operation of the spread spectrum receiving apparatus, which is a feature of the present invention, will be described. In the spread spectrum receiver of this embodiment, first, the synchronous detector 2 performs frequency correction so as to cancel a carrier frequency error signal output from the AFC 13 described later, and a carrier phase error signal output from the CR 14 described later. By performing phase correction that cancels out, synchronous detection is performed on the signal received by the receiving antenna 1, and a complex baseband signal is output.
[0026]
In the delay units 3-1 to 3-(J−1), a delay is added to the input signal having a complex value by the L / J chip cycle time and output. That is, the delay amount of the complex baseband signal output from the delay unit 3-1 is L / J chip cycle time, and the delay amount of the complex baseband signal output from the delay unit 3- (J-1) is ( J-1) × L / J chip cycle time.
[0027]
In the partial correlator 4-j (j∈ {1, 2,..., J}), the input signal having a complex value and one repetition period of the PN code used in the spread spectrum transmitter are equally divided into J. The correlation with each jth partial spreading code of the case, and the partial correlation complex signal e _j Is output.
[0028]
The matrix multiplication unit 6 includes all P orthogonal code sequences d used in the orthogonal function encoding unit 24 of the spread spectrum transmission apparatus. ₁ ~ D _P Are stored in a predetermined matrix format. P = 2 ^K It is. Specifically, as shown by the following equation (1), the orthogonal code sequence d ₁ ~ D _P Is a pre-stored orthogonal code matrix D (P rows and J columns).
[0029]
[Expression 1]

[0030]
Then, in the matrix multiplication unit 6, the partial correlation complex signal e _j And the matrix D are multiplied according to the following equation (2) to obtain an orthogonal code sequence d ₁ ~ D _P Quadrature correlation complex signal i _p (I ₁ ~ I _P ) Is calculated.
[0031]
[Expression 2]

[0032]
In the delay device 7-p (pε {1, 2,..., P}), the orthogonal correlation complex signal i _p Is delayed by Δ time. Δ is 0 <Δ <2T _c It has a value of '. In the delay unit 8-p (pε {1, 2,..., P}), the orthogonal correlation complex signal i _p Is delayed by Δ / 2 hours.
[0033]
On the other hand, in the symbol synchronization circuit 5, the partial correlation complex signal e output from the partial correlator 4-j. ₁ ~ E _J Based on the above, code synchronization with the PN code used in the spread spectrum transmitter is performed, and a regenerated symbol clock synchronized with the generation period of the PN code is output.
[0034]
In the latch 9, the orthogonal correlation complex signal i to which the delay output from the matrix multiplier 6 is not added. ₁ ~ I _P , A quadrature correlation complex signal i to which a delay of Δ time output from the delay unit 7-p is added. ₁ ~ I _P , A quadrature correlation complex signal i with a delay of Δ / 2 time output from the delay unit 8-p. ₁ ~ I _P Are respectively latched at the rising edge of the reproduction symbol clock. At this time, the LATE complex correlation signal LA ₁ ~ LA _P , EARLY complex correlation signal EA ₁ ~ EA _P , CURRENT complex correlation signal CU ₁ ~ CU _P Is output.
[0035]
In the Viterbi decoding unit 10, the CURRENT complex correlation signal CU ₁ ~ CU _P Viterbi decoding is performed using the real number component as a branch metric, and the decoding result is output as decoded data. Further, the Viterbi decoding unit 10 estimates the sequence number of the orthogonal code sequence multiplied by the received signal by performing re-encoding from the maximum likelihood state and the state when one symbol traceback is performed from the maximum likelihood state, The estimation result is output as the first orthogonal code sequence number. The orthogonal code sequence number here is the orthogonal code sequence d. ₁ ~ D _P Means the subscript number.
[0036]
In the maximum power detector 11, the CURRENT complex correlation signal CU ₁ ~ CU _P The one with the maximum square value of the absolute value is selected, and the subscript number of the selected CURRENT complex correlation signal is output as the second orthogonal code sequence number.
[0037]
The DLL 12 determines the advance / delay of the reproduced double chip clock using the LATE complex correlation signal and the EARLY complex correlation signal corresponding to either the first orthogonal code sequence number or the second orthogonal code sequence number. To do. Based on the determination result, the reproduced double chip clock after the clock phase control is output.
[0038]
The AFC 13 estimates the carrier frequency deviation using the CURRENT complex correlation signal corresponding to either the first orthogonal code sequence number or the second orthogonal code sequence number. Then, the carrier frequency error signal is updated based on the estimation result.
[0039]
In CR14, the carrier phase is estimated using a CURRENT complex correlation signal corresponding to either the first orthogonal code sequence number or the second orthogonal code sequence number. Then, the carrier phase error signal is updated based on the estimation result.
[0040]
Next, the operation of each circuit constituting the spread spectrum receiver will be described in detail with reference to the drawings.
[0041]
FIG. 3 is a diagram illustrating a configuration example of the synchronous detection unit 2. The synchronous detection unit 2 of the present embodiment includes a carrier wave generator 31, a phase shifter (π / 2) 32, multipliers 33 and 34, low-pass filters (LPF) 35 and 36, and an analog / digital converter. (A / D) 37 and 38 and a phase rotation unit 39.
[0042]
In the synchronous detection unit 2 shown in FIG. 3, the carrier wave generator 31 generates a sine wave having a frequency substantially equal to the carrier wave used in the frequency conversion unit 28 of the spread spectrum transmitter described above. Then, the multiplier 33 multiplies the sine wave output from the carrier wave generator 31 by the signal received by the antenna 1, and the LPF 35 removes the harmonic component of the signal generated by this multiplication. Sampling at / D37. This generates an in-phase component of the complex spread spectrum signal. Similarly, the multiplier 34 multiplies the sine wave of the carrier wave generator 31 output phase-shifted by π / 2 by the phase shifter 32 and the signal received by the antenna 1, and is generated by this multiplication by the LPF 36. The harmonic component of the received signal is removed, and further, sampling is performed at the A / D 38. Thereby, an orthogonal component of the complex spread spectrum signal is generated.
[0043]
Finally, the phase rotation unit 39 performs frequency correction based on a carrier frequency error signal generated with high accuracy, which will be described later, and a carrier phase error signal generated with high accuracy, which will be described later, as phase rotation processing for the complex spread spectrum signal. A complex baseband signal is generated by performing phase correction based on the above.
[0044]
As described above, in the synchronous detection unit 2 of the present embodiment, synchronous detection is performed using the carrier frequency error signal output from the AFC 13 and the carrier phase error signal output from the CR 14. Thereby, highly accurate carrier frequency synchronization characteristics and carrier phase synchronization characteristics can be realized.
[0045]
FIG. 4 is a diagram illustrating a configuration example of the symbol synchronization circuit 5. The symbol synchronization circuit 5 of this embodiment includes a latch 41 and a power calculation circuit (| • | ² ) 42-1 to 42-J, a first adder (Σ) 43, a second adder 44, a frame memory 45, a peak detector 46, and a delay unit (Δ / 2) 47. Is done.
[0046]
In the symbol synchronization circuit 5 shown in FIG. 4, first, the latch 41 latches the signal output from the partial correlators 4-1 to 4-J at the rising edge of the reproduced double chip clock output from the DLL 12 described later. To do. Then, the power calculation circuits 42-1 to 42-J calculate the square value of the absolute value of the J signals output from the latch 41, and output the partial correlation power signal as the calculation result.
[0047]
Next, the first adder 43 calculates and outputs a correlation power signal as the sum of the partial correlation power signals. Then, the second adder 44 and the frame memory 45 perform cumulative addition (cyclic addition) on the correlation power signal in one repetition cycle of the PN code used on the receiving side.
[0048]
Next, the peak detection unit 46 generates a clock having a rising edge at a position where the cyclic addition result becomes maximum within one repetition period of the PN code. The delay unit 47 adds a delay of Δ / 2 to the received clock. As a result, a reproduced symbol clock having the same period as one repetition period of the PN code and having a rising edge at the peak timing of the CURRENT complex correlation signal is generated.
[0049]
Thus, in the symbol synchronization circuit 5 of the present embodiment, the partial correlation signals output from the partial correlators 4-1 to 4-J are latched at the rising edge of the regenerated double chip clock output from the DLL 12. The signal is used to perform code synchronization with the PN code used in the spread spectrum transmitter. As a result, a reproduced symbol clock synchronized with the peak timing of the CURRENT complex correlation signal with high accuracy can be generated.
[0050]
FIG. 5 is a diagram illustrating a configuration example of the Viterbi decoding unit 10. The Viterbi decoding unit 10 of the present embodiment includes real number component extraction units (Re (•)) 51-1 to 51-P, a path metric calculation unit 52, a path memory 53, a path metric memory 54, and a maximum likelihood. The state detection unit 55, the trace back unit 56, and the re-encoding unit 57 are configured.
[0051]
In the Viterbi decoding unit 10 shown in FIG. 5, first, the real number component extraction units 51-1 to 51-P perform the CURRENT complex correlation signal CU output from the latch 9. ₁ ~ CU _P Branch metric values that are real number components of.
[0052]
Next, the path metric calculation unit 52 adds the path metric value of one symbol before each state transition and the branch metric value corresponding to each state transition to obtain the maximum likelihood from the paths that transition from the state one symbol before. A path is selected, and the path metric value of each state of the maximum likelihood path is stored in the path metric memory 54. Further, path information for reaching the maximum likelihood path selected in each state is stored in the path memory 53.
[0053]
Next, the maximum likelihood state detection unit 55 detects the maximum likelihood state based on the path metric values for all states. Then, the trace back unit 56 performs trace back for Q symbols using the path information in the path memory 53, starting from the maximum likelihood state detected by the maximum likelihood state detection unit 55, and outputs decoded data. . Note that Q is a natural number of 1 or more, and is a value about 4 to 5 times the constraint length used in the convolutional encoding unit 22 of the spread spectrum transmission apparatus described above. Further, the traceback unit 56 outputs the state number of the maximum likelihood state and the state number when one symbol is traced back from the maximum likelihood state.
[0054]
Finally, the re-encoding unit 57 converts the data sequence obtained from the state number of the maximum likelihood state output from the traceback unit 56 and the state number of the state when one symbol is traced back from the maximum likelihood state to the tatami mat. The orthogonal code sequence number multiplied by the received signal is estimated by re-encoding with the generator polynomial used when the convolutional encoding is performed in the convolutional encoding unit 22, and the first orthogonal code is obtained as the estimation result. Output the sequence number.
[0055]
As described above, the Viterbi decoding unit 10 according to the present embodiment performs the CURRENT complex correlation signal CU. ₁ ~ CU _P , And Viterbi decoding that is blocked for each K bits. Thereby, the sequence number of the orthogonal code sequence multiplied by the received signal can be obtained together with the decoded data.
[0056]
FIG. 6 is a diagram illustrating a configuration example of the maximum power detection unit 11. The maximum power detection unit 11 of the present embodiment includes a power calculation circuit (| • | ² ) 61-1 to 61-P and a maximum state number detecting unit 62.
[0057]
In the maximum power detection unit 11 illustrated in FIG. 6, first, the power calculation circuits 61-1 to 61-P perform the CURRENT complex correlation signal (CU) output from the latch 9. ₁ ~ CU _P The square value of the absolute value of any one of (2) is calculated, and a CURRENT correlated power signal is output as the calculation result.
[0058]
Next, the maximum state number detector 62 detects a signal having the maximum correlation power from the P CURRENT correlation power signals calculated by the power calculation circuits 61-1 to 61-P, and corresponds to the maximum signal. The sequence number of the orthogonal code sequence to be output is output as the second orthogonal code sequence number.
[0059]
As described above, in the maximum power detection unit 11 of the present embodiment, the CURRENT complex correlation signal CU ₁ ~ CU _P Thus, the signal having the maximum correlation power is detected, and the sequence number of the orthogonal code sequence corresponding to the signal is output. As a result, the sequence number of the orthogonal code sequence multiplied by the received signal can be obtained by a process different from that of the Viterbi decoding unit 10 described above.
[0060]
FIG. 7 is a diagram illustrating a configuration example of the delay lock loop (DLL) 12. The delay lock loop 12 of the present embodiment includes an orthogonal code sequence number selection unit 71, power calculation circuits (| · |) 72-1 to 72-P, 73-1 to 73-P, selectors 74 and 75, , A subtractor 76, a loop filter 77, and a voltage controlled oscillator (VCO) 78.
[0061]
In the DLL 12 illustrated in FIG. 7, first, the orthogonal code sequence number selection unit 71 outputs the first orthogonal code sequence number output from the Viterbi decoding unit 10 or the second orthogonal code sequence output from the maximum power detection unit 11. Any one of the numbers is appropriately selected, and the selected number is output as the selected orthogonal code sequence number.
[0062]
On the other hand, the power calculation circuits 72-1 to 72-P receive the LATE complex correlation signal (LA ₁ ~ LA _P The square value of the absolute value is calculated, and a LATE correlation power signal is output as the calculation result. Similarly, the power calculation circuits 73-1 to 73-P receive the EARLY complex correlation signal (EA) output from the latch 9. ₁ ~ EA _P The square value of the absolute value is calculated, and an EARLY correlation power signal is output as the calculation result.
[0063]
Next, the selector 74 selects and outputs a LATE correlation power signal corresponding to the selected orthogonal code sequence number output from the orthogonal code sequence number selection unit 71. Similarly, the selector 75 selects and outputs the EARLY correlation power signal corresponding to the selected orthogonal code sequence number.
[0064]
Next, the subtractor 76 subtracts the EARLY correlation power signal output from the selector 75 from the LATE correlation power signal output from the selector 74, and generates a clock error signal as a result. For example, if there is no fading or thermal noise and the value of the clock error signal is larger than 0, this indicates that the clock phase of the regenerated double chip clock output from the VCO 78 is advanced, and the clock error When the signal value is larger than 0, it indicates that the clock phase of the regenerated double chip clock is advanced, and when the value of the clock error signal is 0, the clock phase of the regenerated double chip clock is the received signal. Represents the complete synchronization with the orthogonal code sequence period multiplied by.
[0065]
Next, the loop filter 77 averages the clock error signal having the above characteristics, and obtains the advance or delay of the clock phase of the regenerated double chip clock with high accuracy. Next, the VCO 78 performs clock phase control so as to synchronize with the orthogonal code sequence cycle in which the reproduced double-chip clock is multiplied by the received signal, based on the advance or delay of the clock phase obtained with high accuracy. As a result, a reproduced double chip clock having a clock speed twice that of the chip clock is output.
[0066]
As described above, in the DLL 12 of this embodiment, the advance or delay of the clock phase of the regenerated double chip clock is calculated using the LATE correlation power signal and the EARLY correlation power signal of the selected orthogonal code sequence number appropriately selected. It was decided to. As a result, code synchronization tracking can be performed with high accuracy. In addition, since highly accurate code synchronization tracking can be realized, good decoding characteristics can be obtained.
[0067]
FIG. 8 is a diagram illustrating a configuration example of the orthogonal code sequence number selection unit 71. The orthogonal code sequence number selection unit 71 of this embodiment includes a counter 81, a threshold comparison unit 82, and a selector 83.
[0068]
In the orthogonal code sequence number selection unit 71 shown in FIG. 8, first, the counter 81 counts the time from the completion of the spreading code initial synchronization in the symbol synchronization circuit 5.
[0069]
Next, the threshold value comparison unit 82 determines that the counter value is the threshold value T. _th If smaller, a selection signal for selecting the second orthogonal code sequence number output from the maximum power detector 11 is output, while the counter value is the threshold value T _th In the above case, a selection signal for selecting the first orthogonal code sequence number output from the Viterbi decoding unit 10 is output. In other words, since the correct output result cannot be obtained for the first orthogonal code sequence number until the carrier phase synchronization is established, the orthogonal code sequence can be estimated regardless of the synchronization / asynchronization of the carrier phase when the carrier phase is asynchronous. The second orthogonal code sequence number is selected. In carrier phase synchronization, the first orthogonal code sequence number is selected because the first orthogonal code sequence number has a lower error determination probability due to the coding gain than the second orthogonal code sequence number. . Therefore, the threshold T _th The time required from the completion of the spread code initial synchronization in the symbol synchronization circuit 5 to the establishment of carrier phase synchronization in the CR 14 is appropriate.
[0070]
Finally, the selector 83 selects and outputs either the first orthogonal code sequence number or the second orthogonal code sequence number according to the selection signal output from the threshold value comparison unit 82.
[0071]
FIG. 9 is a timing chart showing the operation of the orthogonal code sequence number selection unit 71. As shown in FIG. 9, the orthogonal code sequence number selection unit 71 uses a threshold value T as a starting point when the spreading code initial synchronization is completed. _th Is used to switch the output of the first orthogonal code sequence number and the second orthogonal code sequence number.
[0072]
As described above, in the orthogonal code sequence number selection unit 71 of the present embodiment, the time required from the completion of spreading code initial synchronization to the establishment of carrier phase synchronization is set as a predetermined threshold value, and the first threshold value is based on this threshold value. The output of the orthogonal code sequence number and the second orthogonal code sequence number is switched. This makes it possible to always select an appropriate orthogonal code sequence number.
[0073]
FIG. 10 is a diagram showing a configuration example of the automatic frequency control circuit (AFC) 13. The AFC 13 of the present embodiment includes an orthogonal code sequence number selection unit 71, a selector 101, and a delay unit (T _s ′) 102, complex conjugate calculation unit (*) 103, complex multiplier 104, loop filter 105, and arctangent (Tan) ^-1 ) 106.
[0074]
In the AFC 13 shown in FIG. 10, first, the orthogonal code sequence number selection unit 71 outputs the first orthogonal code sequence number output from the Viterbi decoding unit 10 or the second orthogonal code sequence output from the maximum power detection unit 11. Any one of the numbers is appropriately selected, and the selected number is output as the selected orthogonal code sequence number.
[0075]
Next, the selector 101 receives the CURRENT complex correlation signal CU. ₁ ~ CU _P The CURRENT complex correlation signal corresponding to the selected orthogonal code sequence number output from the orthogonal code sequence number selection unit 71 is selected and output.
[0076]
Next, the delay unit 102 adds a delay corresponding to one symbol to the signal output from the selector 101. Then, the complex conjugate calculation unit 103 outputs the complex conjugate of the signal after adding one symbol delay.
[0077]
Next, the complex multiplier 104 performs one-symbol delayed detection by complex multiplication of the current signal output from the selector 101 and the complex conjugate value of the signal one symbol before. Note that the phase of the delay detection complex signal, which is the result of 1-symbol delay detection, means the amount of phase rotation per symbol due to frequency deviation.
[0078]
Next, the loop filter 105 averages the delayed detection complex signal output from the complex multiplier 104, and the arctangent unit 106 calculates the phase of the averaged delayed detection complex signal, A carrier frequency error signal indicating the amount of phase rotation per symbol due to frequency deviation is obtained with high accuracy.
[0079]
Thus, in the AFC 13 of the present embodiment, frequency error estimation is performed using the CURRENT complex correlation signal corresponding to the appropriately selected selected orthogonal code sequence number. Thereby, the carrier frequency error signal can be calculated with high accuracy. In addition, since the synchronous detector 2 performs frequency synchronization control using this highly accurate carrier frequency error signal, good frequency synchronization characteristics can be obtained. Furthermore, since a good frequency synchronization characteristic can be realized in the synchronous detector 2, a better decoding characteristic can be obtained.
[0080]
FIG. 11 is a diagram illustrating a configuration example of the carrier reproduction circuit (CR) 14. The CR 14 of the present embodiment includes an orthogonal code sequence number selection unit 71 and a selector 101, a loop filter 111, and an arctangent unit (Tan) described above. ^-1 ) 112.
[0081]
In CR14 shown in FIG. 11, first, the orthogonal code sequence number selection unit 71 outputs the first orthogonal code sequence number output from the Viterbi decoding unit 10 or the second orthogonal code sequence output from the maximum power detection unit 11. Any one of the numbers is appropriately selected, and the selected number is output as the selected orthogonal code sequence number.
[0082]
Next, the selector 101 receives the CURRENT complex correlation signal CU. ₁ ~ CU _P The CURRENT complex correlation signal corresponding to the selected orthogonal code sequence number output from the orthogonal code sequence number selection unit 71 is selected and output. Note that the phase of the complex signal output from the selector 101 means a phase error with respect to the carrier phase used in the synchronous detection unit 2.
[0083]
Next, the loop filter 111 averages the complex signal output from the selector 101, and the arc tangent unit 112 calculates the phase of the averaged complex signal, whereby the carrier phase error indicating the carrier phase error is obtained. Obtain signals with high accuracy.
[0084]
As described above, in the CR 14 of the present embodiment, carrier phase estimation is performed using the CURRENT complex correlation signal corresponding to the appropriately selected selected orthogonal code sequence number. Thereby, the carrier phase error signal can be calculated with high accuracy. Further, since the synchronous detector 2 performs carrier phase synchronization using this highly accurate carrier phase error signal, good carrier phase synchronization characteristics can be obtained. Furthermore, since the good carrier phase synchronization characteristic can be realized in the synchronous detection unit 2, a better decoding characteristic can be obtained.
[0085]
As described above, in the present embodiment, the sequence number of the orthogonal code sequence estimated based on the signal obtained by re-encoding the data sequence obtained by Viterbi decoding with the generator polynomial used on the transmission side (the first orthogonal code sequence number) ) And the sequence number of the orthogonal code sequence (second orthogonal code sequence number) corresponding to the CURRENT complex correlation signal that maximizes the correlation power, the code synchronization tracking process, the frequency We decided to perform synchronization control and carrier phase synchronization control. As a result, it is possible to realize a highly accurate synchronization tracking characteristic, a highly accurate carrier frequency synchronization characteristic, and a highly accurate carrier phase synchronization characteristic.
[0086]
In the spread spectrum receiving apparatus of the present embodiment, each orthogonal code sequence d ₁ ~ D _P For example, a Walsh sequence specified by a Walsh function may be applied. As a result, it is possible to apply fast Hadamard transform to the matrix operation in the matrix multiplication unit 6 and reduce the circuit scale of the spread spectrum receiver.
[0087]
In the spread spectrum receiving apparatus of the present embodiment, a reproduced double chip clock having a clock speed twice that of the chip clock is used as the clock for code synchronization tracking. Other clocks may be used as long as the clock speed is twice or more.
[0088]
Further, in the delay locked loop 12 of the spread spectrum receiver of the present embodiment, the LATE complex correlation signal LA ₁ ~ LA _P And EARLY complex correlation signal EA ₁ ~ EA _P After calculating the square value of the absolute value, the LATE correlation power signal and the EARLY correlation power signal corresponding to the selected orthogonal code sequence number are selected. However, the present invention is not limited to this, and the LATE complex correlation corresponding to the selected orthogonal code sequence number is selected. After selecting the signal and the EARLY complex correlation signal, the square value of the absolute value of the selected signal may be calculated.
[0089]
In the AFC 13 of the spread spectrum receiving apparatus of the present embodiment, the delay amount of the delay unit 102 is 1 symbol. However, the delay amount is not limited to this. For example, the delay amount is h symbols (h is a natural number of 2 or more). Also good. In this case, a carrier frequency error signal is generated from the result of h symbol delay detection.
[0090]
Further, in the Viterbi decoding unit 10 of the spread spectrum receiving apparatus of the present embodiment, the state number when U symbols are traced back from the maximum likelihood state, and the state when (U + 1) symbols are traced back from the maximum likelihood state The direct code sequence number multiplied by the number and the received signal before U symbols may be estimated. However, U is a natural number of 1 or more.
[0091]
Embodiment 2. FIG.
FIG. 12 is a diagram illustrating a configuration example of the synchronous detection unit 2 according to the second embodiment. In the present embodiment, only the operation of the synchronous detection unit 2 that is different from the operation of the first embodiment described above will be described. Since other configurations are the same as those in the first embodiment, the same reference numerals are given and description thereof is omitted.
[0092]
In the synchronous detection unit 2 shown in FIG. 12, first, the carrier generator 121 performs frequency correction for canceling the carrier frequency error signal output from the AFC 13 and phase correction for canceling the carrier phase error signal output from the CR 14. The sine wave after breaking is output.
[0093]
Then, the multiplier 33 multiplies the sine wave output from the carrier wave generator 121 by the signal received by the antenna 1, and the LPF 35 removes the harmonic component of the signal generated by this multiplication. Sampling at / D37. This generates an in-phase component of the complex spread spectrum signal. Similarly, the multiplier 34 multiplies the sine wave of the carrier wave generator 121 output phase-shifted by π / 2 by the phase shifter 32 and the signal received by the antenna 1, and is generated by this multiplication by the LPF 36. The harmonic component of the received signal is removed, and further, sampling is performed at the A / D 38. Thereby, an orthogonal component of the complex spread spectrum signal is generated. The synchronous detection unit 2 outputs a complex baseband signal composed of the in-phase component and the quadrature component.
[0094]
As described above, in the synchronous detection unit 2 of the present embodiment, synchronous detection is performed using the carrier frequency error signal output from the AFC 13 and the carrier phase error signal output from the CR 14. Thereby, as in the first embodiment, highly accurate carrier frequency synchronization characteristics and carrier phase synchronization characteristics can be realized.
[0095]
Embodiment 3 FIG.
FIG. 13 is a diagram illustrating a configuration example of the orthogonal code sequence number selection unit 71 according to the third embodiment. The orthogonal code sequence number selection unit 71 of the present embodiment includes real number component extraction units 131-1 to 131-P, selectors 132 and 135, an averaging unit 133, and a threshold comparison unit 134. In the present embodiment, only the operation of orthogonal code sequence number selection section 71, which is different in operation from the above-described first and second embodiments, will be described. Since other configurations are the same as those in the first or second embodiment, the same reference numerals are given and description thereof is omitted.
[0096]
In the orthogonal code sequence number selection unit 71 shown in FIG. 13, first, the real number component extraction units 131-1 to 131-P perform the CURRENT complex correlation signal (CU) output from the latch 9. ₁ ~ CU _P The real component of any one of
[0097]
Next, the selector 132 outputs the real number component of the CURRENT complex correlation signal corresponding to the first orthogonal code sequence number output from the Viterbi decoding unit 10. The averaging unit 133 averages the output signal of the selector 132, and the average CURRENT real signal AC is obtained as an average result. _r Is output. This average CURRENT real signal has a small value before carrier phase synchronization is established, and has a large value after carrier phase synchronization is established.
[0098]
Next, the threshold value comparison unit 134 calculates the average CURRENT real signal value AC. _r And a predetermined threshold AC _th And compare. For example, "AC _r <AC _th In the case of “(carrier phase asynchronous)”, a selection signal for selecting a second orthogonal code sequence number capable of estimating an orthogonal code sequence regardless of the synchronization / asynchronization of the carrier phase is output. On the other hand, AC _r ≧ AC _th In the case of “carrier phase synchronization”, the first orthogonal code sequence number is smaller in the first orthogonal code sequence number than in the second orthogonal code sequence number due to the coding gain. A selection signal for selecting is output.
[0099]
Finally, the selector 135 selects and outputs either the first orthogonal code sequence number or the second orthogonal code sequence number in accordance with the selection signal output from the threshold comparison unit 134.
[0100]
FIG. 14 is a timing chart showing the operation of the orthogonal code sequence number selection unit 71. As shown in FIG. 14, the synchronization / asynchronization of the carrier phase is determined, and the first orthogonal code sequence number and the second orthogonal code sequence number are switched based on the determination result.
[0101]
As described above, the orthogonal code sequence number selection unit 71 in the present embodiment determines the synchronization / asynchronization of the carrier phase, and based on the determination result, the first orthogonal code sequence number and the second orthogonal code sequence number are determined. It was decided to switch the output. This makes it possible to always select an appropriate orthogonal code sequence number.
[0102]
In the orthogonal code sequence number selection unit 71 of the spread spectrum receiver of this embodiment, the CURRENT complex correlation signal CU ₁ ~ CU _P The real component of the CURRENT complex correlation signal corresponding to the selected orthogonal code sequence number is selected after extraction of the real number component of, but not limited to this, the CURRENT complex correlation signal corresponding to the selected orthogonal code sequence number is selected and then selected. The real component of the CURRENT complex correlation signal may be extracted.
[0103]
【The invention's effect】
As described above, according to the present invention, the sequence number of the orthogonal code sequence estimated based on the signal obtained by re-encoding the decoded data with the generator polynomial used on the transmission side, and the sampling that maximizes the correlation power Any one of the orthogonal code sequences corresponding to the subsequent third orthogonal correlation value (CURRENT complex correlation signal) is appropriately selected, and based on the selection result, code synchronization tracking processing, frequency synchronization control, Carrier phase synchronization control was performed. As a result, there is an effect that a highly accurate synchronization tracking characteristic, a highly accurate carrier frequency synchronization characteristic, and a highly accurate carrier phase synchronization characteristic can be realized.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a spread spectrum receiver according to the present invention.
FIG. 2 is a diagram illustrating a configuration of a spread spectrum transmission apparatus.
FIG. 3 is a diagram illustrating a configuration example of a synchronous detection unit according to the first embodiment.
FIG. 4 is a diagram illustrating a configuration example of a symbol synchronization circuit.
FIG. 5 is a diagram illustrating a configuration example of a Viterbi decoding unit.
FIG. 6 is a diagram illustrating a configuration example of a maximum power detection unit.
FIG. 7 is a diagram illustrating a configuration example of a delay locked loop (DLL).
8 is a diagram illustrating a configuration example of an orthogonal code sequence number selection unit according to the first embodiment. FIG.
FIG. 9 is a timing chart showing the operation of the orthogonal code sequence number selection unit.
FIG. 10 is a diagram illustrating a configuration example of an automatic frequency control circuit (AFC).
FIG. 11 is a diagram illustrating a configuration example of a carrier reproduction circuit (CR).
12 is a diagram illustrating a configuration example of a synchronous detection unit according to Embodiment 2. FIG.
13 is a diagram illustrating a configuration example of an orthogonal code sequence number selection unit according to Embodiment 3. FIG.
FIG. 14 is a timing chart showing the operation of the orthogonal code sequence number selection unit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Reception antenna, 2 Synchronous detection part, 3-1, 3-2, 3- (J-1), 7-1, 7-2, 7-P, 8-1, 8-2, 8-P delay device 4-1, 4-J partial correlator, 5 symbol synchronization circuit, 6 matrix multiplication unit, 9 latch, 10 Viterbi decoding unit, 11 maximum power detection unit, 12 delay lock loop (DLL), 13 automatic frequency control circuit ( AFC), 14 carrier recovery circuit (CR), 31 carrier generator, 32 phase shifter (π / 2), 33, 34 multiplier, 35, 36 low pass filter (LPF), 37, 38 analog / digital converter ( A / D), 39 phase rotation unit, 41 latch, 42-1, 42-2, 42-J power calculation circuit (| • | ² ), 43 first adder (Σ), 44 second adder, 45 frame memory, 46 peak detector, 47 delay unit (Δ / 2), 51-1, 51-2, 51-P real component Extraction unit (Re (•)), 52 path metric calculation unit, 53 path memory, 54 path metric memory, 55 maximum likelihood state detection unit, 56 trace back unit, 57 re-encoding unit, 61-1, 61-2, 61-P power calculation circuit (| ・ | ² ), 62 maximum state number detection unit, 71 orthogonal code sequence number selection unit, 72-1, 72-2, 72-P, 73-1, 73-2, 73-P power calculation circuit (| · |), 74 , 75 selector, 76 subtractor, 77 loop filter, 78 voltage controlled oscillator (VCO), 81 counter, 82 threshold comparator, 83 selector, 101 selector, 102 delay (T _s ′), 103 complex conjugate calculation unit (*), 104 complex multiplier, 105 loop filter, 106 arctangent (Tan) ^-1 ), 111 loop filter, 112 arc tangent (Tan ^-1 ), 121 carrier generator, 131-1, 131-2, 131-P real component extraction unit, 132, 135 selector, 133 averaging unit, 134 threshold comparison unit.

Claims (10)

A correlation value for multiplying a prescribed number of orthogonal code sequences by a correlation value between each of the partial spreading codes obtained by dividing the spreading code by a predetermined number of bits and the complex baseband signal, and calculating the prescribed number of first orthogonal correlation values. A calculation means;
A second orthogonal correlation value to which the same delay amount is added and a third orthogonal correlation value to which half the delay amount is added to the first orthogonal correlation value, and then the specified number Sampling means for sampling the first, second and third quadrature correlation values of a minute using a regenerated symbol clock synchronized with the repetition period of the spreading code on the transmission side;
A decoding process is performed on the third orthogonal correlation value after sampling, and the sequence number of the orthogonal code sequence multiplied by the received signal based on the signal obtained by re-encoding the decoded data (first orthogonal value) Sequence number estimation means for estimating (code sequence number);
Sequence number detecting means for detecting a sequence number (second orthogonal code sequence number) of an orthogonal code sequence corresponding to a third orthogonal correlation value after sampling that maximizes correlation power;
The time from the completion of the initial synchronization of the spreading code is counted, and when the counter value is shorter than the time required from the completion of the initial synchronization of the spreading code to the establishment of the carrier phase synchronization, the second orthogonal code sequence number is selected, If the value is equal to or longer than the time required from completion of spreading code initial synchronization to establishment of carrier phase synchronization, the first orthogonal code sequence number is selected, and the first and second orthogonal after sampling corresponding to the selection result Clock adjusting means for adjusting the recovered symbol clock based on a correlation value;
A spread spectrum receiving apparatus comprising: A correlation value for multiplying a prescribed number of orthogonal code sequences by a correlation value between each of the partial spreading codes obtained by dividing the spreading code by a predetermined number of bits and the complex baseband signal, and calculating the prescribed number of first orthogonal correlation values. A calculation means;
  A second orthogonal correlation value to which the same delay amount is added and a third orthogonal correlation value to which half the delay amount is added to the first orthogonal correlation value, and then the specified number Sampling means for sampling the first, second and third quadrature correlation values of a minute using a regenerated symbol clock synchronized with the repetition period of the spreading code on the transmission side;
  A decoding process is performed on the third orthogonal correlation value after sampling, and the sequence number of the orthogonal code sequence multiplied by the received signal based on the signal obtained by re-encoding the decoded data (first orthogonal value) Sequence number estimation means for estimating (code sequence number);
  Sequence number detecting means for detecting a sequence number (second orthogonal code sequence number) of an orthogonal code sequence corresponding to a third orthogonal correlation value after sampling that maximizes correlation power;
A real number component of the sampled third orthogonal correlation value corresponding to the first orthogonal code sequence number is averaged, and the averaged result is a predetermined value for determining whether carrier phase synchronization is established. When the value is smaller than the threshold, the second orthogonal code sequence number is selected. On the other hand, when the average result is a value equal to or larger than the threshold, the first orthogonal code sequence number is selected, Clock adjusting means for adjusting the recovered symbol clock based on the sampled first and second orthogonal correlation values corresponding to a selection result;
  A spread spectrum receiving apparatus comprising: Further, either one of the first or second orthogonal code sequence number is selected, a carrier frequency deviation is estimated using the sampled third orthogonal correlation value corresponding to the selection result, and the estimation Frequency control means for performing carrier frequency synchronization control based on the result,
Spread spectrum receiver according to claim 1 or 2, characterized in that it comprises a. Further, one of the first and second orthogonal code sequence numbers is selected, a carrier phase error is estimated using the sampled third orthogonal correlation value corresponding to the selection result, and the estimation is performed. Phase control means for performing carrier phase synchronization control based on the result,
The spread spectrum receiver according to claim 3 , comprising: Further, an in-phase component of a complex spread spectrum signal is generated using a received signal and a sine wave having a frequency substantially equal to the carrier wave used on the transmitting side, while the received signal and the sine wave are phase-shifted by π / 2. And generating a quadrature component of the complex spread spectrum signal using the generated sine wave, and then, for each complex spread spectrum signal, frequency correction based on the carrier frequency synchronization control and phase correction based on the carrier phase synchronization control. Synchronous detection means for generating the complex baseband signal by executing
The spread spectrum receiver according to claim 4 , comprising: Further, the reception signal and the in-phase component of the complex spread spectrum signal are generated using the received signal, the frequency correction based on the carrier frequency synchronization control, and the sine wave after the phase correction based on the carrier phase synchronization control is performed, A synchronous detection means for generating the complex baseband signal by generating an orthogonal component of a complex spread spectrum signal using the received signal and a sine wave obtained by shifting the sine wave by π / 2.
The spread spectrum receiver according to claim 4 , comprising: Before Symbol frequency control means and said phase control means,
The time from the completion of the initial synchronization of the spreading code is counted, and when the counter value is shorter than the time required from the completion of the initial synchronization of the spreading code to the establishment of the carrier phase synchronization, the second orthogonal code sequence number is selected, If the value is more than the time required for the establishment carrier phase synchronization from the complete spreading code initial synchronization, the spread spectrum receiver according to claim 4, 5 or 6, characterized in that selects the first orthogonal code sequence number . Before Symbol frequency control means and said phase control means,
A real number component of the sampled third orthogonal correlation value corresponding to the first orthogonal code sequence number is averaged, and the averaged result is a predetermined value for determining whether carrier phase synchronization is established. When the value is smaller than a threshold value, the second orthogonal code sequence number is selected. On the other hand, when the average result is equal to or larger than the threshold value, the first orthogonal code sequence number is selected. The spread spectrum receiver according to claim 4, 5 or 6 . The clock adjusting means includes
Subtract the square value of the absolute value of the sampled second orthogonal correlation value corresponding to the selection result from the square value of the absolute value of the sampled first orthogonal correlation value corresponding to the selection result. and spread spectrum receiver according to any one of claims 1-8, characterized in that adjusting the recovered symbol clock based on the subtraction result. Examples orthogonal code sequence, the spread spectrum receiver according to any one of claims 1-9, characterized by applying a Walsh sequence specified by the Walsh function.

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