JP2002009161A5 - - Google Patents

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Publication number
JP2002009161A5
JP2002009161A5 JP2001012789A JP2001012789A JP2002009161A5 JP 2002009161 A5 JP2002009161 A5 JP 2002009161A5 JP 2001012789 A JP2001012789 A JP 2001012789A JP 2001012789 A JP2001012789 A JP 2001012789A JP 2002009161 A5 JP2002009161 A5 JP 2002009161A5
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JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001012789A
Other versions
JP2002009161A (ja
JP4756746B2 (ja
Filing date
Publication date
Priority claimed from JP2001012789A external-priority patent/JP4756746B2/ja
Priority to JP2001012789A priority Critical patent/JP4756746B2/ja
Application filed filed Critical
Priority to US09/828,981 priority patent/US6563148B2/en
Priority to TW090109122A priority patent/TW584929B/zh
Priority to KR10-2001-0020782A priority patent/KR100429111B1/ko
Publication of JP2002009161A publication Critical patent/JP2002009161A/ja
Priority to US10/419,770 priority patent/US6753246B2/en
Publication of JP2002009161A5 publication Critical patent/JP2002009161A5/ja
Publication of JP4756746B2 publication Critical patent/JP4756746B2/ja
Application granted granted Critical
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2001012789A 2000-04-19 2001-01-22 半導体装置およびその製造方法 Expired - Fee Related JP4756746B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2001012789A JP4756746B2 (ja) 2000-04-19 2001-01-22 半導体装置およびその製造方法
US09/828,981 US6563148B2 (en) 2000-04-19 2001-04-10 Semiconductor device with dummy patterns
TW090109122A TW584929B (en) 2000-04-19 2001-04-17 Semiconductor device and dummy pattern placing method
KR10-2001-0020782A KR100429111B1 (ko) 2000-04-19 2001-04-18 반도체 장치 및 더미 패턴의 배치 방법
US10/419,770 US6753246B2 (en) 2000-04-19 2003-04-22 Semiconductor device with a first dummy pattern

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2000117629 2000-04-19
JP2000117629 2000-04-19
JP2000-117629 2000-04-19
JP2001012789A JP4756746B2 (ja) 2000-04-19 2001-01-22 半導体装置およびその製造方法

Publications (3)

Publication Number Publication Date
JP2002009161A JP2002009161A (ja) 2002-01-11
JP2002009161A5 true JP2002009161A5 (ja) 2008-02-21
JP4756746B2 JP4756746B2 (ja) 2011-08-24

Family

ID=26590372

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001012789A Expired - Fee Related JP4756746B2 (ja) 2000-04-19 2001-01-22 半導体装置およびその製造方法

Country Status (3)

Country Link
JP (1) JP4756746B2 (ja)
KR (1) KR100429111B1 (ja)
TW (1) TW584929B (ja)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3479052B2 (ja) 2001-04-23 2003-12-15 沖電気工業株式会社 半導体装置のダミー配置判定方法
JP4620942B2 (ja) 2003-08-21 2011-01-26 川崎マイクロエレクトロニクス株式会社 半導体集積回路のレイアウト方法、そのレイアウト構造、およびフォトマスク
JP4599048B2 (ja) 2003-10-02 2010-12-15 川崎マイクロエレクトロニクス株式会社 半導体集積回路のレイアウト構造、半導体集積回路のレイアウト方法、およびフォトマスク
JP4284202B2 (ja) 2004-02-04 2009-06-24 パナソニック株式会社 面積率／占有率検証プログラム及びパターン生成プログラム
US7269818B2 (en) 2005-01-06 2007-09-11 International Business Machines Corporation Circuit element function matching despite auto-generated dummy shapes
JP4322839B2 (ja) 2005-04-11 2009-09-02 エルピーダメモリ株式会社 半導体装置
KR100650870B1 (ko) 2005-08-08 2008-07-16 주식회사 하이닉스반도체 플래쉬 메모리 소자 및 그의 제조방법
JP2007299898A (ja) 2006-04-28 2007-11-15 Matsushita Electric Ind Co Ltd 半導体装置および半導体装置のレイアウト設計方法
JP2008066716A (ja) * 2006-08-10 2008-03-21 Matsushita Electric Ind Co Ltd 半導体装置
KR100789614B1 (ko) * 2006-08-11 2007-12-27 동부일렉트로닉스 주식회사 더미 패턴 및 그 형성방법
KR20080096215A (ko) * 2007-04-27 2008-10-30 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조방법
US7771901B2 (en) 2007-05-02 2010-08-10 Dongbu Hitek Co., Ltd. Layout method for mask
JP5184003B2 (ja) 2007-08-28 2013-04-17 川崎マイクロエレクトロニクス株式会社 半導体集積回路およびダミーパターンの配置方法
JP6262060B2 (ja) * 2014-04-03 2018-01-17 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
TWI758408B (zh) * 2018-02-09 2022-03-21 聯華電子股份有限公司 半導體結構

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3249317B2 (ja) * 1994-12-12 2002-01-21 富士通株式会社 パターン作成方法
JP3555074B2 (ja) * 1999-11-17 2004-08-18 Ｎｅｃエレクトロニクス株式会社 半導体装置およびその製造方法

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