JP2002009077A - Monolithic integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a monolithic integrated circuit in which high frequency characteristics are enhanced by utilizing unused element regions effectively as a wiring. SOLUTION: Sets of active elements 2, capacitor electrodes 6, and resistor elements 21 are formed in array on a semiconductor substrate 1 to produce a common substrate. A dielectric film 28 of 1 μm thick or above is formed on a ground conductor 25 and a wiring 29 is formed on the dielectric film 28. The wiring 29 is connected with the active elements 2, and the like, on the substrate 1 by means of through holes 31 through holes 24 in a dielectric film 23 and openings 26 in the ground conductor 25 thus constituting a circuit. The openings 26 are made above active elements being used in the circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency monolithic integrated circuit having a semiconductor substrate on which a number of active elements are formed.

[0002]

2. Description of the Related Art With the rapid development of mobile communication in recent years, there is a strong demand for realizing a radio IC with a short development period and a low manufacturing cost. Various proposals have been made for such a request.

FIG. 1 is a plan view of a monolithic integrated circuit as a first conventional example. An active element 2 such as an FET and an inductor 3 are provided on one surface (main surface) of a substrate 1 made of a semiconductor.
Circuit elements such as capacitors and capacitors 4 and wiring patterns 5
Are formed, thereby forming a circuit.

In this conventional monolithic integrated circuit, the arrangement of each element is different for a circuit having a required function, and a photomask required in a semiconductor integrated circuit manufacturing process (hereinafter, referred to as a semiconductor process). Were also required individually for each circuit. A typical semiconductor process for a monolithic integrated circuit requires about 10 photomasks and about 2 months for active device formation, and more than half and 2/3 of the number of photomasks required for the entire semiconductor process. Of time is spent for forming the active device. Therefore, in the case of small-quantity multi-product production, the proportion of the photomask in the production cost is large and the cost is high, and the production takes a long time.

As a second conventional example for solving this problem,
The master slice monolithic integrated circuit is 198
Introduced in the United States in 1980 (E. Turner et a
l. “APPLICATION SPECIFIC MM
IC: A UNIQUEAND AFFORDABLE
APPROACH TO MMIC DEVELOPME
NT ", IEEE 1988 Microwave an
d Millimeter-Wave Circuit
Symposium, pp. 9-14).

As shown in FIG. 2, in the master slice type monolithic integrated circuit, first, an active element 2 such as an FET and a conductor 6 for a lower electrode of a thin film capacitor are formed on one surface of a substrate 1 made of a semiconductor. By using this as a common substrate and forming wiring conductors on the substrate, circuits of various frequency bands or functions are realized.

FIG. 3A shows an example in which a narrow-band amplifier in the 27 GHz band is realized by forming the wiring conductor 5 on the common substrate of FIG. FIG. 3B shows an example in which a 30 GHz band broadband amplifier is realized by forming a wiring conductor 5 'on the common substrate of FIG.

As described above, in the master slice type monolithic integrated circuit, by changing the pattern of the wiring conductor formed on the common substrate on which the active element is formed in advance, not only the amplifier but also various functions such as the oscillator and the frequency converter are provided. The circuits can be realized from the same common substrate. That is, since various circuits are configured with the same active element arrangement, a common photomask for forming the active element can be used,
The above-mentioned problem of the manufacturing cost of the conventional monolithic integrated circuit can be solved. Also, in the semiconductor process, many manufacturing steps and time are required to form active elements. However, by arranging active elements in the same manner, the semiconductor process can be started prior to circuit design, and circuit development can be started. The feature is that the period can be significantly reduced. Further, in a normal semiconductor process, 10
Although more than one wafer is processed simultaneously, a common substrate portion can be mass-produced in a master-slicing monolithic integrated circuit even when the number of wafers is as small as one or two, which is economical. In such a master slice type monolithic integrated circuit, the versatility of the common substrate can be enhanced by forming active elements and the like in an array on the common substrate.

[0009] As a conventional technique similar to the master slice method, a gate array technique in LSI manufacturing and an analog / digital
An analog master slice technique used for a digital embedded ASIC or the like can be given. FIG. 4 (A) and FIG.
(B) shows a CMOS gate array as a third conventional example. This is because Blumberg et al.
“A640K Transistor Sea-of-
Gates 1.2 Micron HCMOS Tech
nology ", 1988, IEEE Interna.
Tional Solid State Circuit
s Confence, 1988, Febru
ary 17. (See “ASIC Handbook” issued by the Industrial Research Council). FIG. 1A is a plan view of an internal basic cell, and a p-type diffusion layer 11, n
A mold diffusion layer 12 and a gate 13 are formed. A master cell is formed by forming such basic cells in an array. By providing the first-layer wiring 14 and the second-layer wiring 15 as shown in FIG.
An input NAND circuit or the like can be realized. The same applies to the case of the analog master slice method. These technologies, like the master slice monolithic integrated circuits described above, implement basic elements such as transistors on the chip in advance, and realize user-specified logic and characteristics by connecting these components through the wiring process. What you want to do.

[0010] As a fourth conventional example, S.I. Banba,
“Small-Size MMIC Amplifier
rs Using Thin Dielectric La
yers ", IEEE, TRANSACTIONS O
N MICROWAVE THEORY AND TECH
NIQUES, VOL. 43, NO. 3, MARCH
1995. This is because a multilayer wiring layer is formed on the substrate, reducing the chip area,
The cost is reduced.

[0011]

In the prior art 1 described above, the ratio of passive elements in each IC circuit is large, and the arrangement of circuit elements greatly affects circuit characteristics.
For the circuit, the circuit element arrangement and the like must be individually designed. This has led to increased development times and manufacturing costs.

Further, in the prior art 2, since the circuit elements are connected in a plane, the intervals between the elements must be widened, and the area where the wiring conductors are formed must be previously provided. The area was large.

When the active elements and the like are arranged in an array, an element necessary for realizing desired characteristics among the active elements arranged in the array is selected and used. For this reason, among the active elements arranged in the above-mentioned array, there are unused ones. However, in a conventional master slice type monolithic integrated circuit, high-frequency devices are placed on unused active elements. Other passive circuits and transmission lines could not be formed. Therefore, in this case, it is necessary to prepare a region for forming the passive element and the wiring in advance, and there is a disadvantage that a useless area on the substrate is further increased. That is, the region of the active element that does not contribute to the circuit function must be left as it is, which has been an obstacle to miniaturization and cost reduction of the circuit. Further, since the above-described active element, passive element, and wiring conductor are formed on the same plane, and the active element is formed at a predetermined position, the degree of freedom for forming the passive element and wiring is increased. Was restricted. Therefore, extra wiring such as bypassing the active element portion is required, and there is a problem that parasitic capacitance, inductance, resistance, and the like are generated to deteriorate circuit characteristics. In order to increase the degree of freedom in wiring, the spacing between the elements must be increased, and the shape becomes large, which is not practical.

The gate array technology in prior art 3 and
In the analog master slice technology as seen in the mixed analog / digital ASIC, the post-process based on the user specification is almost only the wiring process in most cases. In this wiring step, the thickness of the dielectric film used for insulation is as thin as 0.5 μm to 0.7 μm, and there is no planar ground conductor. Therefore, the conductor formed in the wiring step was not a high-frequency transmission line, but could be used only as a simple wiring. In other words, it is impossible to precisely design the characteristic impedance and electrical length of the wiring in a high frequency region where the wiring behaves as a distributed constant line, and there is a limit to the frequency to which a gate array or an analog master slice can be applied. Was. Further, since the above wiring cannot be handled as a distributed constant transmission line, a circuit having a function such as various hybrids used in a high-frequency circuit cannot be added in a later step.

In the prior art 4, although the chip area can be reduced and the manufacturing cost can be reduced, the element arrangement must be individually designed for each functional IC. Have.

An object of the present invention is to provide, for example, a communication MMIC.
(Monolithic Microwave Inte
It is intended to provide a monolithic integrated circuit which can be applied to a graded circuit and the like, and is suitable for shortening the development period and reducing the manufacturing cost.

[0017]

In order to achieve the above object, a monolithic integrated circuit of the present invention comprises a semiconductor substrate having a plurality of active elements formed on a surface thereof, and a semiconductor substrate having a plurality of active elements formed on the active elements. A first dielectric film, and one or more windows and a cover formed on the first dielectric film, wherein the window is formed on a used active element in the active element; Comprises a selection plate that covers unused active elements in the active element, a wiring layer formed on the selection plate, and connection means for connecting the used active element to the wiring layer. Features.

[0018] The selection plate may be formed of a first ground conductor.

The distance between the semiconductor substrate and the first ground conductor may be 1,000 to 5,000 angstroms.

The wiring layer has a first conductor for wiring the active element to be used, and a first wiring layer dielectric film formed between the selection plate and the first conductor. There may be.

[0021] The thickness of the first wiring layer dielectric film may be 1 micron or more.

[0022] The wiring layer may be a multilayer wiring layer.

The wiring layer includes: a first wiring layer dielectric film formed on the selection plate; a first conductor formed on the first wiring layer dielectric film; It may have a second wiring layer dielectric film formed on the conductor, and a second conductor formed on the second wiring layer dielectric film.

The thickness of each of the first wiring layer dielectric film and the second wiring layer dielectric film may be 1 μm or more.

A second dielectric film formed on the first conductor, and a second ground formed between the second dielectric film and the second wiring layer dielectric film. It may further have a conductor.

The thickness of each of the first wiring layer dielectric film, the second wiring layer dielectric film, and the second dielectric film may be 1 μm or more.

[0027] The active element on the semiconductor substrate may be juxtaposed with a passive element on the semiconductor substrate, and the passive element may be connected to the wiring layer.

[0028] The wiring layer may include one or more passive elements connected to the active elements to be used.

The wiring layer may include a coplanar transmission line connected to the active device to be used.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The above-mentioned prior art 4 and Japanese Patent Application Laid-Open No. 5-129803 disclose a technique using a ground conductor. That is, prior art 4 has a ground conductor inserted between two wiring layers, and prevents interference between conductors. Also, JP-A-5-129803 discloses that
A ground conductor is inserted between the first dielectric layer and the second dielectric layer, and a strip conductor formed between the first and second dielectric layers is formed between the first and second dielectric layers. Prevents interference. However, these ground conductors differ from the ground conductor of the present application in the following points.

(1) The ground conductor of the present invention covers unused active elements, thereby selecting and distinguishing between active elements to be used and those not to be used, and forms a passive circuit right above the unused active elements. It is possible to do that.
That is, it is provided to separate unused active elements and passive circuits. On the other hand, the ground conductor of the prior art is for preventing interference between wires arranged above and below. In the present application, the unused active elements include:
Considering that no signal flows, it is clear that the ground conductor of the present application is not intended to prevent interference.

(2) Further, the function of the dielectric layer provided below the ground conductor is different. That is, the dielectric layer under the ground conductor of the present application protects the active element and functions as an insulating film for forming a capacitor. In contrast, the dielectric layer below the ground conductor of the prior art is for separating the ground conductor and the signal line.

(3) The ground conductor of the present invention has a window on the active element used. Prior art ground conductors, on the other hand, have through holes but no such windows. Since the performance of an active element covered with a ground conductor via a thin dielectric film deteriorates, this window is an essential requirement for avoiding deterioration of the performance of the active element used.

[0034]

Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 5 shows an embodiment of the present invention. At least a large number of active elements 2 are formed on one surface (main surface) of the semiconductor substrate 1. In this example, a large number of lower electrode conductors 6 and ion implantation resistance elements 21 are formed as passive elements in addition to the active element 2, respectively. The active element 2 is a source 2S, a gate 2
G, and a drain 2D, in which three FETs are formed, are arranged in rows and columns, and a lower electrode conductor 6 is arranged side by side with the three FETs in each set of three FETs. The middle lower electrode conductor 6 formed is about three times as long as those on both sides. Each resistance element 2
Numeral 1 is formed for each set of FETs at one end of the array of FETs, and the longitudinal direction is perpendicular to the array of FETs. That is, three FETs 2, three lower electrode conductors 6, and one resistance element 21 constitute one set.
They are arranged in rows and columns (array form). The semiconductor substrate on which the active element 2 and the passive elements 6 and 21 are formed is referred to as a common substrate 22.

A dielectric film 23 is formed on the active element forming surface of the semiconductor substrate 1. This dielectric film 23 is a protective film for protecting the active element 2 formed on the semiconductor substrate 1 and the like.
In this example, the thin film capacitor functions as an insulating film for forming a capacitance between electrodes. The active element 2 to be used depends on the circuit layout of the function to be realized.
The connection holes 24 ₁ , 24 ₂ ... Are formed in a portion of the dielectric film 23 facing the lower electrode conductor 6 and each connection electrode portion of the resistance element 21.
To form The dielectric film 23 is, for example, a SiO ₂ film, SiN
_Four films are used, and the thickness is, for example, 1,000 to 5,000.
The connection holes 24 ₁ , 24 ₂ ... Are formed by photoetching, dry etching, or the like. The thickness of the dielectric film 23 is a thickness usually used as an insulating film for a thin film capacitor or a protective film of an active element, and is different from a thickness for distinguishing a signal line of a high-frequency transmission line from a ground conductor. I have.

Next, almost the entire surface of the dielectric film 23 is covered with the ground conductor 25. In this case, use openings 26 ₁ , 26 ₂ ... Are formed corresponding to the active elements 2 and the passive elements 6 and 21 to be used according to the layout of the circuit. The upper electrode conductor 27 for the lower electrode conductor 6 for forming the capacitor is also used at the same time when the ground conductor 25 is formed.
6 Formed in ₁ . Although not shown, the ground conductor 25
May be formed together with the ground conductor 25 to form a central conductor constituting a coplanar transmission line. That is, an opening that is not used for anything is not formed in the ground conductor 25. For example, Au is used as the ground conductor 25, the thickness is set to, for example, about 1 μm, and the openings 26 ₁ , 26 ₂ ... Are formed by ion milling or the like.

A dielectric film 28 having a thickness of, for example, about 1 to 10 microns is formed on the ground conductor 25 by, for example, a polyimide resin. A necessary wiring conductor 29 is formed on the dielectric film 28.
₁ , 29 ₂ ... are formed. These wiring conductors 29 ₁ , 29
Prior to the formation of ₂ ..., The connection electrodes of the active element 2 and the passive elements 6 and 21, the upper electrode conductor 27, and the like are connected to the wiring conductors 29 ₁ , 29 ₂ . The through holes 31 ₁ , 31 ₂ ... To be completed are formed in the dielectric film 28. That is, small holes are formed in advance at positions where the through holes 31 ₁ , 31 ₂ ... Are to be formed in the dielectric film 28, and for example, A
u layer is formed, thereby forming through holes 31 ₁ and 31 _2.
Are formed, and the Au layer is patterned to form wiring conductors 29 ₁ , 29 ₂ . The wiring layer 33 is composed of the dielectric film 28 and the wiring conductors 29 ₁ , 29 ₂ .

FIGS. 6A to 6D show cross sections of respective parts of the monolithic integrated circuit of this embodiment thus constructed.
Is shown. According to this monolithic integrated circuit, FIG.
As shown in the wiring conductor 29 _1, 29 ₂ ... constitutes a microstrip line together with the ground conductor 25. Of use active elements 2, electrodes to be grounded, for example, as shown in FIG. 6 (B), connected to the ground conductor 25 at the source 25 ₁ connection is packed in the hole 24 _first conductor 32 ₁ of the active element 2 And grounded. The connection conductor 32 ₁ is automatically formed when the formation of the ground conductor 25.

FIG. 6C shows an example in which the lower electrode conductor 6 is used.
₁ And a portion facing the ground conductor 25,
And one end of this capacitor, that is, for the lower electrode
Conductor 6₁ But hole 24_Two Connection conductor 32 packed in_Two And su
Rehaul 31₁ And the wiring conductor 29 through_Four Connected to
And the other end of the capacitor is grounded by a ground conductor 25.
Is the case. This connection conductor 32_Two And through hole 31
₁ Is the wiring conductor 29 ₁ , 29_Two A to form ...
It is formed automatically when the u layer is formed.

FIG. 6D shows an example of the upper electrode conductor 2.
7 and conductor 6 for lower electrode_Two And a capacitor composed of
And the upper electrode conductor 27 through the through hole 31._Two Through
Wiring conductor 29_Two To the lower electrode conductor 6_Two The hole
24_Three Connection conductor 32 packed in _Three Through and through
Rule 31_Three Wiring conductor 29 through_Three Example of connecting to
Ball wiring conductor 29_Two , 29_Three Connect a capacitor in between
Is the case.

In the monolithic integrated circuit configured as described above, since the arrangement of the active elements 2 such as FETs is determined in advance, the semiconductor substrate 22 can be shared by various circuits, thereby reducing manufacturing costs. Thus, the development period can be shortened. Further, by covering unused elements with the planar ground conductor 25, wiring or the like can be performed directly above these unused elements, and the circuit can be reduced in size. Furthermore, since the unused elements are covered with the ground conductor 25, the unused active elements 2 and the like do not exist on the ground conductor 25, that is, on the passive circuit formed on the wiring layer 33. Therefore, the degree of freedom in wiring is high, and extra wiring such as bypassing the active element 2 can be avoided, and the influence of parasitic inductance and capacitance can be reduced.

FIGS. 7A and 7B show the characteristic impedance characteristic and the transmission loss characteristic with respect to the line width W of the wiring conductor 29 _i as the signal line of the microstrip line shown in FIG. 6A. 4 shows the results calculated by the finite element method using the thickness h of the dielectric film 28 as a parameter. The calculation conditions are as follows: the relative dielectric constant of the dielectric film 28 is 3.3;
The conductivity of the signal line 29 _i was 4.908 × 10 ⁷ S / m, the thickness of the signal line 29 _i was 1 μm, and the frequency was 10 GHz.

FIG. 7A shows that when the thickness h of the dielectric film 28 is 1 μm or less, the signal line 29 is used to realize a 50Ω transmission line most frequently used in high frequency circuits such as microwaves. It can be seen that the width of _i must be made extremely small. Such narrowing may not be possible depending on the accuracy of the process. Further, as can be seen from FIG. 7B, even if such a thin wiring can be realized, the transmission loss becomes considerably large, and the circuit characteristics deteriorate.

However, in the present invention, the thickness h of the dielectric film 28 is
Is set to 1 μm or more, for example, about 1 to 10 μm.
The fact that a transmission line having a characteristic impedance of about 0Ω can be realized can be estimated from the fact that the characteristic impedance is about 15Ω when h = 2.5 μm and W = 30 μm. In this case, the transmission loss is also a value sufficiently low for practical use.

Further, by using a polyimide resin as the dielectric film 28, a multilayer film having high flatness can be realized by low-temperature processing, and circuit characteristics can be improved. Further, in high frequency circuits such as microwaves, parasitic components due to connection between elements often deteriorate circuit characteristics greatly, and it is necessary to avoid unnecessary wiring as much as possible. By forming an active element, a resistance element, and a capacitor electrode as one unit and forming a plurality of them in an array on a substrate in advance as in this embodiment, each element can be connected at a short distance, and the design is good. A monolithic integrated circuit can be realized.

Embodiment 2 FIG. 8 shows another embodiment of the present invention, in which parts corresponding to those in FIG. In this embodiment, in contrast to the configuration of FIG. 5, (1) a dielectric film 34 having a thickness of about several microns is further formed on the dielectric film 28, and (2) the dielectric film 3
4 to form the wiring conductor 35 on, constitute a wiring layer 36 made of a dielectric film 34 and the wiring conductor 35. The (3) the wiring conductor 29 ₂ of FIG. 5 in this example, 29 ₃ provided that omitted to corresponding thereto as the wiring conductor 35 _1, 35 _2, a case where a multilayer wiring layer 37 with (4) a wiring layer 33.

In other words, the active elements and the passive elements of the common substrate 22 are connected so as to form a desired circuit by using the multilayer wiring layer 37.

In this case, the same operation and effect as those of the embodiment of FIG. 5 are obtained, and furthermore, by using a multi-layer wiring, it is possible to more freely perform line crossing and the like than in the case of FIG.
The degree of freedom in circuit layout can be improved.

Embodiment 3 FIG. 9 shows still another embodiment of the present invention. In the embodiment shown in FIG. 8, the dielectric film 38 and the ground conductor 39 are different from the embodiment shown in FIG.
3 and 36, and above and below the ground conductor 39, which are together a wiring conductor 35 constituting a high-frequency transmission line.
_1, a 35 ₂ ... and 29 _1, 29 ₂ to the case of constituting the. As a result, a wiring having a uniform impedance can be obtained.

Embodiment 4 FIG. 10 shows still another embodiment of the present invention. In this embodiment, only the active elements 2 are formed in an array on the common substrate 22, and three FEs are formed similarly to the active elements 2 in FIG.
T is formed as a set of rows and columns. On the dielectric layer 28, not only the wiring conductor 29 but also an interdigital capacitor 41, a metal resistor 42 formed by printing a high-resistance metal, and a part of the ground conductor 25 as a lower electrode constitute a capacitor. The upper electrode conductor 43 is formed. By forming the passive elements on the dielectric film 28 instead of the common substrate 22 in this manner, the degree of freedom in arranging the passive elements is improved, and miniaturization and high density of the circuit can be realized.

The same applies to the common substrate shown in FIG.
Also, as shown in FIG. 9, a multilayer wiring of a high-frequency transmission line may be used. In this case, the interference in the wiring is reduced in FIG.

In the above description, the active elements are formed in an array of rows and columns, but they may be arranged in any shape. Although the three active elements 2 are provided, two or four or more active elements 2 may be provided. Instead of a plurality of sets, a single set may be arranged.

[0054]

As described above, according to the present invention, the arrangement of active elements and the like on a semiconductor substrate can be determined in advance. In this case, the manufacturing cost and the development period can be reduced.

Further, according to the present invention, since the unused elements are covered with the planar ground conductor, wiring and the like can be performed directly above the unused elements, and the wiring area is accordingly reduced. There is no need to prepare, the area of the semiconductor substrate can be effectively used, and the size of the circuit can be reduced.

Further, since the unused elements are covered with the ground conductor, these unused elements are the same as those that do not exist in the circuit laminated thereon. For this reason, a circuit can be formed without being restricted by the arrangement of active elements formed in advance on the substrate, so that the degree of freedom of wiring is high, and it is possible to avoid extra wiring such as bypassing the active element part. As a result, the influence of parasitic inductance and capacitance can be reduced, so that high performance of the circuit can be realized.

Also, because of the presence of a planar ground conductor,
Wiring formed on the ground conductor via a dielectric film can precisely design the characteristic impedance and electrical length, and can be used as a high-frequency transmission line, as well as a high-frequency functional circuit such as a hybrid. Can be formed.

By forming the passive circuit in the multilayer wiring layer, the passive circuit can be formed with high integration, and the size of the circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view showing a monolithic integrated circuit of Conventional Example 1.

FIG. 2 is a plan view showing a common substrate of a master slice type monolithic integrated circuit of Conventional Example 2.

FIG. 3A is a plan view showing a wiring pattern for realizing a 27 GHz band narrow band amplifier in a master slice type monolithic integrated circuit of Conventional Example 2, and FIG. FIG. 3 is a plan view showing a wiring pattern for realizing a 30 GHz band broadband amplifier in a monolithic integrated circuit.

FIG. 4A is a plan view showing an internal basic cell of a gate array LSI of Conventional Example 3, and FIG. 4B is a plan view showing a two-input NAND circuit realized using the basic internal cell of FIG. .

FIG. 5 shows a first example of the monolithic integrated circuit according to the present invention.
FIG. 3 is an exploded perspective view showing the embodiment of FIG.

FIG. 6A is a cross-sectional view showing a high-frequency transmission line realized in the first embodiment, FIG. 6B is a cross-sectional view showing a state where the electrodes of the active elements are grounded in the first embodiment, and FIG. FIG. 4 is a cross-sectional view illustrating a portion where a grounding capacitor is formed in the first embodiment, and FIG. 4D is a cross-sectional view illustrating a portion where a capacitor inserted in series between wirings is formed in the first embodiment.

FIG. 7A is a graph showing a characteristic impedance of a microstrip line calculated by a finite element method,
(B) is a graph showing the transmission loss of the microstrip line calculated by the finite element method.

FIG. 8 shows a second example of the monolithic integrated circuit according to the present invention.
FIG. 3 is an exploded perspective view showing the embodiment of FIG.

FIG. 9 shows a third example of the monolithic integrated circuit according to the present invention.
FIG. 3 is an exploded perspective view showing the embodiment of FIG.

FIG. 10 is an exploded perspective view showing a fourth embodiment of the monolithic integrated circuit according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Active element 6 Conductor for lower electrode for capacitors (passive element) 21 Resistive element (passive element) 22 Common substrate 23 Dielectric film 24 Connection hole 25 Ground conductor 26 Opening 27 Upper electrode conductor 28 Dielectric film 29 Wiring conductor 31 Through hole 32 Connection conductor 34 Dielectric film 35 Wiring conductor 36 Wiring layer 37 Multilayer wiring layer 38 Dielectric film 39 Ground conductor 41 Interdigital capacitor 42 Metal resistor 43 Upper electrode conductor

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Kenjiro Nishikawa 2-3-1 Otemachi, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Kenji Kamogawa 2-3-3, Otemachi, Chiyoda-ku, Tokyo No. 1 F-term in Nippon Telegraph and Telephone Corporation (reference) EE23 EE32 EE46 EE52

Claims (13)

[Claims] A semiconductor substrate having a plurality of active elements formed on a surface thereof; a first dielectric film formed on the active element; and a first dielectric film formed on the first dielectric film. The above-mentioned window and cover part are provided, and the window is formed on the active element used in the active element, and the cover part covers the unused active element in the active element and does not cover the active element used. A monolithic integrated circuit, comprising: a selected plate; a wiring layer formed on the selected plate; and connecting means for connecting the active element to the wiring layer. 2. The monolithic integrated circuit according to claim 1, wherein said selection plate comprises a first ground conductor. 3. The monolithic integrated circuit according to claim 2, wherein a distance between the semiconductor substrate and the first ground conductor is 1,000 to 5,000 angstroms. 4. The wiring layer has a first conductor for wiring the active element to be used, and a first wiring layer dielectric film formed between the selection plate and the first conductor. The monolithic integrated circuit according to claim 1, wherein: 5. The thickness of the first wiring layer dielectric film is 1
5. The monolithic integrated circuit according to claim 4, wherein the size is at least one micron. 6. The monolithic integrated circuit according to claim 1, wherein said wiring layer is a multilayer wiring layer. 7. The wiring layer includes: a first wiring layer dielectric film formed on the selection plate; a first conductor formed on the first wiring layer dielectric film; 7. The semiconductor device according to claim 6, further comprising: a second wiring layer dielectric film formed on the first conductor, and a second conductor formed on the second wiring layer dielectric film. A monolithic integrated circuit as described. 8. The monolithic integrated circuit according to claim 7, wherein each of the first wiring layer dielectric film and the second wiring layer dielectric film has a thickness of 1 μm or more. 9. A second dielectric film formed on the first conductor, and a second dielectric film formed between the second dielectric film and the second wiring layer dielectric film. The monolithic integrated circuit according to claim 7, further comprising: a ground conductor. 10. The first wiring layer dielectric film and the second wiring layer dielectric film.
10. The monolithic integrated circuit according to claim 9, wherein each of the wiring layer dielectric film and the second dielectric film has a thickness of 1 micron or more. 11. The monolithic integration according to claim 1, wherein the active element on the semiconductor substrate is juxtaposed with the passive element on the semiconductor substrate, and the passive element is connected to the wiring layer. circuit. 12. The monolithic integrated circuit according to claim 1, wherein the wiring layer includes one or more passive elements connected to the active elements used. 13. The monolithic integrated circuit according to claim 1, wherein said wiring layer includes a coplanar transmission line connected to said active device.