JP2001346106A - Image pickup device - Google Patents
Image pickup deviceInfo
- Publication number
- JP2001346106A JP2001346106A JP2000166307A JP2000166307A JP2001346106A JP 2001346106 A JP2001346106 A JP 2001346106A JP 2000166307 A JP2000166307 A JP 2000166307A JP 2000166307 A JP2000166307 A JP 2000166307A JP 2001346106 A JP2001346106 A JP 2001346106A
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- Prior art keywords
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- signal
- analog
- digital
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- 238000006243 chemical reaction Methods 0.000 claims abstract description 42
- 238000003384 imaging method Methods 0.000 claims description 28
- 230000008030 elimination Effects 0.000 claims 1
- 238000003379 elimination reaction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 23
- 230000003321 amplification Effects 0.000 description 13
- 238000003199 nucleic acid amplification method Methods 0.000 description 13
- 238000000034 method Methods 0.000 description 11
- 238000001514 detection method Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
- 230000007423 decrease Effects 0.000 description 3
- 210000003127 knee Anatomy 0.000 description 3
- 238000013139 quantization Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 2
- 101000588067 Homo sapiens Metaxin-1 Proteins 0.000 description 1
- 102100031603 Metaxin-1 Human genes 0.000 description 1
- 108010076504 Protein Sorting Signals Proteins 0.000 description 1
- 101000727837 Rattus norvegicus Reduced folate transporter Proteins 0.000 description 1
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Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は撮像装置に係わり、
特に固体撮像素子内にAD(アナログデジタル)変換器
を内蔵した固体撮像装置に好適に用いられる撮像装置に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an imaging device,
In particular, the present invention relates to an imaging device suitably used for a solid-state imaging device in which an A / D (analog-digital) converter is built in a solid-state imaging device.
【0002】[0002]
【従来の技術】各画素毎にAD変換器を内蔵した撮像装
置としては、特開平6−205307号公報に開示され
た撮像装置がある。この撮像装置では積分された画素電
圧をコンパレータと比較しADデータを得ている。2. Description of the Related Art As an image pickup apparatus having an A / D converter for each pixel, there is an image pickup apparatus disclosed in Japanese Patent Application Laid-Open No. 6-205307. In this imaging device, the integrated pixel voltage is compared with a comparator to obtain AD data.
【0003】また、画素列毎にAD変換器を形成した撮
像装置としては、ISSCC99 SESSION17 PAPERWA17.7にA25
0mW、600Frames/s 1280×720pixel 9b CMOS Digital Ima
ge Sensorがある。本例では画素列毎に読み出した信号
をコンパレータの基準電圧と比較しADデータを得てい
る。[0003] Further, as an imaging device in which an AD converter is formed for each pixel column, ISSCC99 SESSION17 PAPERWA17.7 has A25.
0mW, 600Frames / s 1280 × 720pixel 9b CMOS Digital Ima
There is a ge Sensor. In this example, AD data is obtained by comparing a signal read for each pixel column with a reference voltage of a comparator.
【0004】またISSCC 2000 Session 6 IMAGE Sensors
PAPER MP 6.4 A 60mW 10b CMOS Image Sensor with Co
lumn-to-Column FPN Reductionでは画素信号をランプ信
号と比較することによりADデータを得ている。[0004] ISSCC 2000 Session 6 IMAGE Sensors
PAPER MP 6.4 A 60mW 10b CMOS Image Sensor with Co
In the lumen-to-column FPN Reduction, AD data is obtained by comparing a pixel signal with a ramp signal.
【0005】この様に従来例では画素信号を直接AD変
換するか、アナログゲイン回路で画素信号を増幅制御後
AD変換していた。As described above, in the conventional example, the pixel signal is directly AD-converted, or the analog signal is subjected to A / D conversion after the amplification control of the pixel signal.
【0006】[0006]
【発明が解決しようとする課題】画素信号を直接AD変
換する場合、暗い条件で撮像するとADの定格入力電圧
に対し信号レベルが小さいためSNの劣化とともにAD
の量子化誤差が大きくなってしまう。In the case of direct AD conversion of a pixel signal, if the image is picked up in a dark condition, the signal level is small with respect to the rated input voltage of the AD, so that the AD deteriorates and the AD decreases.
Will have a large quantization error.
【0007】また、信号電圧を大きくするために、アナ
ログゲイン回路でゲインコントロールを行なうが、この
場合列毎のアナログゲイン誤差が画面上では縦方向のス
ジ状ノイズとして、画質を著しく低下させる。Further, in order to increase the signal voltage, gain control is performed by an analog gain circuit. In this case, an analog gain error for each column is displayed as vertical streak noise on a screen, and image quality is significantly reduced.
【0008】また、カラー化を考えた場合、撮影時の光
源により色毎のダイナミックレンジが変わり、AD変換
器の性能をフルに発揮出来ない。例えば光源の色温度が
低い時は赤の画素信号が大きくなり、色温度が高い場合
は青の画素信号が大きくなり、AD入力電圧を制限す
る。また、撮像素子は年々画素サイズの縮小化がはから
れており、列毎に画素ノイズ除去回路、アナログゲイン
回路やコンパレータ、DA変換器を設けることはチップ
サイズが大きくなる欠点がある。また列毎のピッチにそ
れらの回路を回路間の精度をそろえて設計するのは非常
に困難である。これらはいずれにしても画面上は縦方向
のスジ状ノイズとなる。[0008] When colorization is considered, the dynamic range of each color changes depending on the light source at the time of photographing, and the performance of the AD converter cannot be fully exhibited. For example, when the color temperature of the light source is low, the red pixel signal increases, and when the color temperature is high, the blue pixel signal increases, thereby limiting the AD input voltage. Further, the pixel size of the image sensor is reduced year by year, and providing a pixel noise removing circuit, an analog gain circuit, a comparator, and a DA converter for each column has a disadvantage that the chip size becomes large. Also, it is very difficult to design those circuits at the pitch of each column with the precision between the circuits being aligned. In any case, these become vertical streak noises on the screen.
【0009】(発明の目的)本発明の目的は撮像素子内
のAD変換器の性能向上と機能向上、コスト低減にあ
る。(Object of the Invention) It is an object of the present invention to improve the performance, function, and cost of an AD converter in an image sensor.
【0010】[0010]
【課題を解決するための手段】本発明の撮像装置は、複
数の画素と、前記画素からの画素信号レベルと比較基準
レベルとの比較結果に基づいてデジタル信号を出力する
アナログデジタル変換手段と、を備えた撮像装置であっ
て、前記アナログデジタル変換手段は、比較を行う前記
画素からの画素信号のレベルと前記比較基準レベルとを
相対的に可変し、前記可変を行う可変範囲を変化させる
ことを特徴とする撮像装置である。An image pickup apparatus according to the present invention comprises: a plurality of pixels; an analog-to-digital converter for outputting a digital signal based on a comparison result between a pixel signal level from the pixel and a comparison reference level; Wherein the analog-to-digital conversion means relatively varies a level of a pixel signal from the pixel to be compared and the comparison reference level, and changes a variable range in which the variation is performed. An imaging apparatus characterized by the following.
【0011】また、本発明の撮像装置は、複数の画素か
ら列ごとに出力される信号をアナログデジタル信号処理
して出力する撮像装置において、複数の列毎に共通のア
ナログデジタル信号処理手段を設けることを特徴とする
撮像装置である。In the image pickup apparatus according to the present invention, a common analog digital signal processing means is provided for each of a plurality of columns in an image pickup apparatus which performs analog-to-digital signal processing on signals output from a plurality of pixels for each column and outputs the processed signals. An imaging apparatus characterized in that:
【0012】[0012]
【実施例】以下、本発明の実施例について図面を用いて
詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.
【0013】図1に本発明の撮像装置の一実施例の全体
構成図を示す。図1において、100は絞りや撮像レン
ズからなる光学系、110は固体撮像素子である。固体
撮像素子110は、光電変換部と画素アンプと制御スイ
ッチから構成される画素がエリア状に配置された画素部
111、画素部111を走査する垂直走査回路部11
2、画素部111からの画素信号のバラツキを補正する
ノイズ除去回路やゲイン制御回路やAD(アナログデジ
タル)変換回路からなるアナログデジタル信号処理回路
部113、アナログデジタル信号処理回路部113を制
御する水平走査回路部114、タイミングジェネレータ
(TG)部115から構成される。FIG. 1 shows an overall configuration diagram of an embodiment of an imaging apparatus according to the present invention. In FIG. 1, reference numeral 100 denotes an optical system including a stop and an imaging lens, and 110 denotes a solid-state imaging device. The solid-state imaging device 110 includes a pixel unit 111 in which pixels including a photoelectric conversion unit, a pixel amplifier, and a control switch are arranged in an area, and a vertical scanning circuit unit 11 that scans the pixel unit 111.
2. An analog-to-digital signal processing circuit unit 113 including a noise removal circuit, a gain control circuit, and an AD (analog-to-digital) conversion circuit for correcting variations in pixel signals from the pixel unit 111, and a horizontal circuit for controlling the analog-to-digital signal processing circuit unit 113. It comprises a scanning circuit section 114 and a timing generator (TG) section 115.
【0014】タイミングジェネレータ(TG)部115
はカメラCPU130からのパルスにより、固体撮像素
子110内の画素部や各回路部を制御するものである。
固体撮像素子110からのADデータはカメラ信号処理
系120に入力される。Timing generator (TG) section 115
Controls the pixel unit and each circuit unit in the solid-state imaging device 110 by a pulse from the camera CPU 130.
AD data from the solid-state imaging device 110 is input to the camera signal processing system 120.
【0015】カメラ信号処理系120はカメラ信号処理
回路部121、AE(露光)情報検出回路部122、ホ
ワイトバランス情報検出回路部123からなる。The camera signal processing system 120 comprises a camera signal processing circuit 121, an AE (exposure) information detecting circuit 122, and a white balance information detecting circuit 123.
【0016】カメラ信号処理回路部121ではADデー
タから輝度信号処理、色信号処理がなされる。また、A
E(露光)情報検出回路部122ではカメラ信号処理回
路部121の輝度情報から画像信号レベルを検出しAE
(露光)情報を発生させる。このAE情報結果によって
アナログデジタル信号処理回路部113の後述するDA
(デジタルアナログ)変換回路のランプ状基準電圧の範
囲を切換えて、画素信号がAD入力電圧範囲の最適値に
なるよう制御される。後述するように、画素信号が小さ
い時はランプ状基準電圧の振幅を小さくし、画素信号が
大きい時はランプ状基準電圧の振幅を大きい方に切換
え、AD入力電圧を極力大きくする。次にホワイトバラ
ンス(WB)情報検出回路部123はカメラ信号処理回
路部121の色信号R,G,Bのレベルを比較し、その
結果を前述のランプ状基準電圧を色毎に制御する。In the camera signal processing circuit section 121, luminance signal processing and color signal processing are performed from the AD data. Also, A
The E (exposure) information detection circuit section 122 detects an image signal level from the luminance information of the camera signal processing circuit section 121 and performs AE.
(Exposure) information is generated. Based on the AE information result, a DA (to be described later) of the analog / digital signal processing circuit 113 is used.
The range of the ramp reference voltage of the (digital / analog) conversion circuit is switched so that the pixel signal is controlled so as to have an optimum value of the AD input voltage range. As described later, when the pixel signal is small, the amplitude of the ramp-shaped reference voltage is reduced, and when the pixel signal is large, the amplitude of the ramp-shaped reference voltage is switched to the larger one, and the AD input voltage is increased as much as possible. Next, the white balance (WB) information detection circuit unit 123 compares the levels of the color signals R, G, and B of the camera signal processing circuit unit 121, and controls the above-described result for the above-described ramp-shaped reference voltage for each color.
【0017】この様にランプ状基準電圧をAE情報で制
御するか、WB情報で制御するかは撮像装置の仕様によ
って決めることができる。個別に制御しても良いし、A
E情報で全体レベルの制御、WB情報で色毎の信号レベ
ルを制御しても良い。この制御によりAD変換器の入力
信号レベルが大きくなるのでSNは劣化せずに、またA
D変換器による量子化誤差は小さくできる。As described above, whether the ramp reference voltage is controlled by the AE information or the WB information can be determined according to the specifications of the imaging apparatus. It may be controlled individually, or A
The overall level may be controlled by E information, and the signal level of each color may be controlled by WB information. This control increases the input signal level of the AD converter, so that SN does not deteriorate and A
The quantization error caused by the D converter can be reduced.
【0018】130は固体撮像装置の特にカメラ部を制
御するカメラCPUである。140は記録・再生系、1
50は表示系である。Reference numeral 130 denotes a camera CPU for controlling the camera section of the solid-state imaging device. 140 is a recording / reproducing system, 1
50 is a display system.
【0019】図2に画素部111、アナログデジタル信
号処理回路部113、垂直走査回路部112の概略回路
図を示す。図2において、11はコンパレータ、10は
カウンタ、9はDA変換器である。FIG. 2 is a schematic circuit diagram of the pixel section 111, the analog / digital signal processing circuit section 113, and the vertical scanning circuit section 112. In FIG. 2, reference numeral 11 denotes a comparator, 10 denotes a counter, and 9 denotes a DA converter.
【0020】図3は画素部の一画素とノイズ除去・アナ
ログデジタル変換回路部を示す等価回路ブロック図であ
る。DA変換器にはランプ状基準電圧の範囲を切換える
DA出力レンジ切換情報が入力される。FIG. 3 is an equivalent circuit block diagram showing one pixel of the pixel section and a noise removal / analog-to-digital conversion circuit section. DA output range switching information for switching the range of the ramp reference voltage is input to the DA converter.
【0021】図3において、21は光電変換素子、22
は光電変換素子21の信号電荷を増幅トランジスタ23
のゲートに転送する転送トランジスタ、24は画素選択
トランジスタ、25はリセットトランジスタ、26は増
幅トランジスタ23の出力電流をスイッチ27と保存用
コンデンサー28によって電圧として保存し、その電圧
を電流に変換しながら出力する電流源用トランジスタ、
31は電流源トランジスタ26の出力電流と、画素選択
トランジスタ24を介して出力される増幅トランジスタ
23の出力電流との差分を検出するコンパレータ、30
はコンパレーター31の出力をカウントするカウンタ
ー、29はカウンター30から出力されるデジタル信号
により電圧を増幅トランジスタ23のソース(主電極)
端子へ出力するDA変換器である。DA変換器29には
DA出力レンジ切換情報が入力され、DA変換器から出
力されるランプ状基準電圧の範囲を切換えて、画素信号
がAD入力電圧範囲の最適値になるよう制御される。In FIG. 3, reference numeral 21 denotes a photoelectric conversion element;
Represents the signal charge of the photoelectric conversion element 21 and the amplification transistor 23
A transfer transistor for transferring the current to the gate of the transistor, 24 is a pixel selection transistor, 25 is a reset transistor, and 26 is a switch 27 and a storage capacitor 28, which store the output current of the amplification transistor 23 as a voltage, and output the voltage while converting the voltage into a current. Current source transistor,
A comparator 31 detects a difference between the output current of the current source transistor 26 and the output current of the amplification transistor 23 output via the pixel selection transistor 24.
Is a counter for counting the output of the comparator 31, and 29 is a source (main electrode) of the amplifying transistor 23 which amplifies a voltage by a digital signal output from the counter 30.
This is a DA converter that outputs to a terminal. DA output range switching information is input to the DA converter 29, and the range of the ramp-like reference voltage output from the DA converter is switched so that the pixel signal is controlled so as to have an optimum value of the AD input voltage range.
【0022】上記の構成で、例として増幅トランジスタ
がリセットされた後、光電変換素子からの信号電荷によ
る信号電圧を得る方法を図4のタイミングチャートを交
えて説明する。ここで図3の各トランジスタ22,2
3,24,25はPMOSトランジスタとして、トラン
ジスタ26はNMOSトランジスタとして以降説明す
る。DA変換器29はある高電位(VHD)を出力するよ
うに設定する。カウンター30はリセットされ、カウン
ト動作はしていないものとする。端子φRを“L”レベ
ルとして(パルス201)リセットトランジスタ25を
ONさせ、増幅トランジスタ23のゲート端子を所定の
電位にリセットする。その時、同時に端子φXを“L”
レベル(パルス202)にして選択トランジスタ24を
ONさせ、またスイッチ27もONさせる。増幅トラン
ジスタ23のリセット時の出力電流は、トランジスタ2
6がゲート−ドレインが短絡することで発生するゲート
電圧の形で保存用コンデンサ28に保存される(比較基
準電圧が保存される。)。その後、トランジスタ25,
24、スイッチ27はOFFし、光電変換素子に入力し
た光に応じた信号電荷を、端子φT を“L”レベルにす
る(パルス203)ことで転送トランジスタ22がON
し増幅トランジスタ23のゲート端子に転送する。この
時のゲート電位はリセット時よりも低い電圧であったと
すると増幅トランジスタ23の出力電流はそれに応じて
リセット時よりも大きい値となる。一方、トランジスタ
26は保存用コンデンサ28の電圧を受け、増幅トラン
ジスタ23がリセットされた時の電流を出力している。
端子φX を“L”レベルにし(パルス204)再びトラ
ンジスタ24をONさせるとコンパレーター31の入力
電位はある高電位(VH )に上昇する。この後カウンタ
ー30を動作し、そのデジタル出力を増幅させ、それを
受けるDA変換器29の出力電圧は徐々に減少(DA変
換器29はデジタル入力信号に対し負極性のアナログ出
力電圧を発生すると仮定する。)する。ある時点で、増
幅トランジスタ23の出力電流とトランジスタ26の出
力電流が等しくなり、コンパレーター31の入力電圧は
急速に減少するので、その変化を検出し、カウンター3
0のカウント動作を停止させる。A method of obtaining a signal voltage based on the signal charges from the photoelectric conversion element after the amplification transistor is reset in the above configuration will be described with reference to a timing chart of FIG. Here, each of the transistors 22 and 2 in FIG.
3, 24 and 25 are described as PMOS transistors, and the transistor 26 is described as an NMOS transistor. The DA converter 29 is set to output a certain high potential (V HD ). It is assumed that the counter 30 has been reset and no counting operation has been performed. The terminal φR is set to the “L” level (pulse 201), the reset transistor 25 is turned on, and the gate terminal of the amplification transistor 23 is reset to a predetermined potential. At this time, the terminal φX is set to “L” at the same time.
The selection transistor 24 is turned on at the level (pulse 202), and the switch 27 is also turned on. The output current of the amplifying transistor 23 at the time of reset is determined by the transistor 2
6 is stored in the storage capacitor 28 in the form of a gate voltage generated when the gate-drain is short-circuited (the comparison reference voltage is stored). After that, the transistors 25,
24, the switch 27 is turned off, and a signal charge corresponding to the light input to the photoelectric conversion element is turned on by setting the terminal φT to the “L” level (pulse 203), thereby turning on the transfer transistor 22.
Then, the signal is transferred to the gate terminal of the amplification transistor 23. Assuming that the gate potential at this time is lower than that at the time of reset, the output current of the amplification transistor 23 has a value corresponding to that at the time of reset. On the other hand, the transistor 26 receives the voltage of the storage capacitor 28 and outputs a current when the amplification transistor 23 is reset.
When the terminal .phi.X is set to "L" level (pulse 204) and the transistor 24 is turned on again, the input potential of the comparator 31 rises to a certain high potential ( VH ). Thereafter, the counter 30 is operated to amplify the digital output, and the output voltage of the DA converter 29 receiving the output gradually decreases (assuming that the DA converter 29 generates a negative analog output voltage with respect to the digital input signal). Yes.) At some point, the output current of the amplification transistor 23 becomes equal to the output current of the transistor 26, and the input voltage of the comparator 31 decreases rapidly.
The count operation of 0 is stopped.
【0023】このカウンター30のカウント開始から停
止までに変化したデジタル値は増幅トランジスタ23の
ゲート電位の、リセットされた時の電位と信号電荷が転
送された時の電位の差分に等しい値となる。このように
して差分に対応するAD変換が行われたことになる。The digital value changed from the start to the stop of the counter 30 becomes a value equal to the difference between the reset potential and the potential when the signal charge is transferred, of the gate potential of the amplification transistor 23. Thus, the AD conversion corresponding to the difference has been performed.
【0024】図2は図3の構成例を、光電変換部が3行
3列の2次元に配列された場合に適用させたものであ
る。光電変換素子1(1−1−1,1−1−2,…)、
転送トランジスタ2(2−1−1,2−1−2,…)、
増幅トランジスタ3(3−1−1,3−1−2,…)、
画素選択トランジスタ4(4−1−1,4−1−2,
…)、リセットトランジスタ5(5−1−1,5−1−
2,…)、定電流トランジスタ6(6−1,6−2,
…)、増幅トランジスタ3の出力電流によってトランジ
スタ6のゲート−ソース間に発生する電圧を取り込み、
保存するためのスイッチ7(7−1,7−2,…)と容
量8(8−1,8−2,…)、垂直信号線12(12−
1,12−2,…)の電位変化を検出するコンパレータ
ー11(11−1,11−2,…)、DA変換器9(9
−1,9−2,…)にデジタル信号を供給するカウンタ
ー10(10−1,10−2,…)など構成は図3の場
合と同様である。FIG. 2 shows an example in which the configuration example of FIG. 3 is applied to a case where the photoelectric conversion units are arranged two-dimensionally in three rows and three columns. Photoelectric conversion element 1 (1-1-1, 1-1-2,...),
Transfer transistor 2 (2-1-1, 1-2-2,...),
Amplifying transistor 3 (3-1-1, 3-1-2,...),
The pixel selection transistor 4 (4-1-1, 4-1-2,
…), Reset transistor 5 (5-1-1, 5-1
2, constant current transistor 6 (6-1, 6-2,
…), The voltage generated between the gate and the source of the transistor 6 by the output current of the amplification transistor 3 is taken in,
The switch 7 (7-1, 7-2,...) For storage, the capacitor 8 (8-1, 8-2,...), The vertical signal line 12 (12-
, 12-2,...), And a DA converter 9 (9-1, 9-2,...)
-1, 9-2,...) Are the same as those in FIG.
【0025】一行目の画素の出力を得る場合、垂直シフ
トレジスタ15からの駆動線15−1を“L”レベルに
してリセット用トランジスタ5(5−1−1,5−1−
2,5−1−3)をONさせ、その後駆動線14−1を
“L”レベルにして画素選択トランジスタ4(4−1−
1,4−1−2,4−1−3)をONさせて、リセット
状態の増幅トランジスタ3(3−1−1,3−1−2,
3−1−3)の出力電流を垂直信号線12(12−1,
12−2,12−3)へ出力し、駆動線13を“H”レ
ベルにしてスイッチ7(7−1,7−2,7−3)をO
Nさせ、容量8(8−1,8−2,8−3)にトランジ
スタ6にリセット状態の出力電流を供給した時のゲート
−ソース間に発生する電圧を保持する。In order to obtain the output of the pixels in the first row, the drive line 15-1 from the vertical shift register 15 is set to the "L" level to set the reset transistors 5 (5-1-1, 5-1).
2, 5-1-3) is turned on, and then the drive line 14-1 is set to the "L" level to set the pixel selection transistor 4 (4-1-4-1).
1, 4-1-2, 4-1-3) are turned on to reset the amplification transistor 3 (3-1-1, 3-1-2, 3-1-3).
3-1-3) is output to the vertical signal line 12 (12-1,.
12-2, 12-3), the drive line 13 is set to the "H" level, and the switches 7 (7-1, 7-2, 7-3) are turned off.
N, and the voltage generated between the gate and the source when the output current in the reset state is supplied to the transistor 6 to the capacitor 8 (8-1, 8-2, 8-3) is held.
【0026】その後、図3の動作と同様にカウンター1
0(10−1,10−2,10−3)のカウント動作を
開始し、DA変換器9(9−1,9−2,9−3)の出
力電圧を減少させ、垂直信号線12の電位変動をコンパ
レーター11で検出し、カウンター10の動作を停止さ
せて、カウント開始から停止までのデジタル値の変化分
をデジタル出力としてAD変換が完了する。図9はDA
変換器9(9−1,9−2,9−3)に、DA出力レン
ジ切換え情報としてAE情報を用いた場合を示す回路図
である。40は一画素を示す。Thereafter, as in the operation of FIG.
0 (10-1, 10-2, 10-3) counting operation is started, the output voltage of the DA converter 9 (9-1, 9-2, 9-3) is reduced, and the vertical signal line 12 The potential change is detected by the comparator 11, the operation of the counter 10 is stopped, and the change in the digital value from the start to the stop of the count is used as a digital output to complete the AD conversion. FIG. 9 shows DA
FIG. 9 is a circuit diagram showing a case where AE information is used as DA output range switching information in the converter 9 (9-1, 9-2, 9-3). Reference numeral 40 denotes one pixel.
【0027】図5に図2及び図3に示したDA変換器の
一構成例の回路図を示す。FIG. 5 is a circuit diagram showing an example of the configuration of the DA converter shown in FIGS. 2 and 3.
【0028】この構成例はR−2Rラダー方式でnビッ
トADのとき2n個の抵抗とn個のスイッチで構成され
る。基準電圧をスイッチコントロールによりラダーの抵
抗値を変化させ、その抵抗値とアンプの抵抗値Rf との
比がDA出力電圧となる。DA変換器の方式はR−2R
ラダー方式に限定されず、他に容量アレイ方式であって
も良い。This configuration example is composed of 2n resistors and n switches in the case of n-bit AD in the R-2R ladder system. The resistance value of the ladder is changed by switch control of the reference voltage, and the ratio of the resistance value to the resistance value Rf of the amplifier becomes the DA output voltage. The method of DA converter is R-2R
The present invention is not limited to the ladder method, but may be a capacitance array method.
【0029】DA出力範囲を切換える方法として、図6
にスイッチで複数の基準電圧(E1,E2,E3)に切換え
る方法、図7にアンプの帰環抵抗Rf を切換えてラダー
の抵抗値と抵抗値Rf との比を切換える方法を示す。As a method of switching the DA output range, FIG.
FIG. 7 shows a method of switching to a plurality of reference voltages (E1, E2, E3) by a switch, and FIG. 7 shows a method of switching the return value Rf of the amplifier to switch the ratio between the resistance value of the ladder and the resistance value Rf .
【0030】図8はDA出力レンジを図6あるいは図7
の方法により切換えた時のDA出力を示す特性図であ
る。DA変換器の比較基準電圧にKNEE特性あるいは
γ特性を持たせても良い。そうすることによって撮像装
置を簡略化させることが出来る。カラー撮像装置の場
合、後述のホワイトバランスとγ,Knee機能を共用
させると良い。FIG. 8 shows the DA output range of FIG. 6 or FIG.
FIG. 9 is a characteristic diagram showing DA output when switching is performed by the method of FIG. The comparison reference voltage of the DA converter may have a KNEE characteristic or a γ characteristic. By doing so, the imaging device can be simplified. In the case of a color image pickup apparatus, it is preferable to share the white balance described later and the γ and Knee functions.
【0031】図14に本発明の他の実施例の特性図を示
す。被写体の映像情報によって、AD変換のセンサ出力
信号レベルの変換範囲あるいは変換の重み付けやデジタ
ル化出力ビット数を用途によって変えることができる。FIG. 14 is a characteristic diagram of another embodiment of the present invention. Depending on the image information of the subject, the conversion range of the sensor output signal level of AD conversion, the weight of conversion, and the number of digitized output bits can be changed depending on the application.
【0032】図14において、(A)の場合は、センサ
出力信号DA出力電圧範囲V1とV2間で直線的にAD
変換する。In FIG. 14, in the case of (A), the AD signal is linearly adjusted between the sensor output signal DA output voltage range V1 and V2.
Convert.
【0033】(B)においては、同様にDA出力電圧範
囲V3とV4間でAD変換するが、DA出力電圧範囲が
小さくなっており、これは被写体の反射光量範囲が狭い
場合、例えば原稿情報、バーコード情報検出などに適し
ている。In (B), AD conversion is similarly performed between the DA output voltage ranges V3 and V4, but the DA output voltage range is small. This is because when the reflected light amount range of the subject is narrow, for example, document information, Suitable for bar code information detection.
【0034】また(C)はDA出力電圧を非直線的に変
換させた場合である。例えばDA出力電圧がV5近辺で
は電圧範囲を小さくし、V6近辺では大きくすることに
より、センサ出力信号にγ変換処理を行ったAD変換が
できる。センサ信号を直接的にデジタル変換しているの
で量子化誤差やノイズの増加がなく、高品質画質を得る
ことができる。(C) is a case where the DA output voltage is converted non-linearly. For example, by reducing the voltage range when the DA output voltage is near V5 and increasing the voltage range near V6, it is possible to perform AD conversion in which the sensor output signal is subjected to γ conversion processing. Since the sensor signal is directly converted into a digital signal, a high quality image can be obtained without an increase in quantization error or noise.
【0035】(D)は、(A)のDA出力電圧のビット
数を少なくした場合であり、原稿情報あるいはAD変換
が低ビット数でよい用途に対応できる。(D) is a case where the number of bits of the DA output voltage in (A) is reduced, and can be applied to a use in which document information or AD conversion requires a low number of bits.
【0036】図10に本発明の固体撮像装置の他の実施
例を示す回路図を示す。上述した図2〜図4を用いて説
明した実施例は画素信号の出力レベルの可変範囲をDA
出力レンジ切換情報に基づいて切り替えた実施例を示し
たが、本実施例は比較基準電圧の可変範囲をDA出力レ
ンジ切換情報に基づいて切り替えた実施例を示すもので
ある。FIG. 10 is a circuit diagram showing another embodiment of the solid-state imaging device of the present invention. In the embodiment described with reference to FIGS. 2 to 4, the variable range of the output level of the pixel signal is set to DA.
Although the embodiment in which the switching is performed based on the output range switching information has been described, the present embodiment illustrates an embodiment in which the variable range of the comparison reference voltage is switched based on the DA output range switching information.
【0037】図11に示すように、画素40からの画素
信号はコンパレータ42で列ごとにDA変換器43から
のDA出力電圧と比較され、AD変換器44でADデー
タに変換される。DA変換器43にはランプ状基準電圧
の範囲を切換えるDA出力レンジ切換情報(AE情報)
が入力される。41は負荷であり画素40のトランジス
タとの間でソースフォロア回路を構成する。As shown in FIG. 11, the pixel signal from the pixel 40 is compared with the DA output voltage from the DA converter 43 on a column basis by the comparator 42, and is converted into AD data by the AD converter 44. DA output range switching information (AE information) for switching the range of the ramp reference voltage is provided in the DA converter 43.
Is entered. A load 41 constitutes a source follower circuit with the transistor of the pixel 40.
【0038】図11はカラー化の実施例を示す回路図で
ある。本実施例は上述した図2〜図4を用いて説明した
実施例に適用した場合を示すものである。画素信号の出
力レベルの可変範囲はホワイトバランス(WB)情報に
基づいて切り替えられる。FIG. 11 is a circuit diagram showing an embodiment of colorization. This embodiment shows a case where the present embodiment is applied to the embodiment described with reference to FIGS. The variable range of the output level of the pixel signal is switched based on white balance (WB) information.
【0039】画素40にはR,G,Bの色フィルタがモ
ザイク状に配置されている。画素行(…(n+1)行,
n行)毎にDA変換器9(9−1,9−2,9−3)
に、WB情報切換信号を各色に対応して入力し、各色に
対応してDA出力レンジを切換えることで、各色信号の
AD変換範囲を切換える。このWB情報は図1のカメラ
信号処理系120のWB検出信号による。n行ではB信
号とG信号のAD変換範囲が、(n+1)行ではG信号
とR信号のAD変換範囲が順次切換えられる。In the pixel 40, R, G, B color filters are arranged in a mosaic pattern. Pixel rows (... (n + 1) rows,
DA converter 9 (9-1, 9-2, 9-3) for every n rows)
Then, a WB information switching signal is input for each color, and the DA output range is switched for each color, thereby switching the AD conversion range of each color signal. This WB information is based on the WB detection signal of the camera signal processing system 120 in FIG. In the n-th row, the AD conversion range of the B signal and the G signal is sequentially switched, and in the (n + 1) -th row, the AD conversion range of the G signal and the R signal is sequentially switched.
【0040】図12に色順次出力に本発明を応用した実
施例を示す。FIG. 12 shows an embodiment in which the present invention is applied to color sequential output.
【0041】図11と同様に、画素40にはR,G,B
の色フィルタがモザイク状に配置されている。n行で
は、まず列切換え制御パルスCoddによりB信号列の画
素信号をAD変換し、ADデータとして出力する。次に
列切換え制御パルスCevenによりG信号列の画素信号を
AD変換し、ADデータとして出力する。この際、DA
変換器9(9−1,9−2,9−3)に、WB情報切換
信号を各色に対応して入力し、各色に対応してDA出力
レンジを切換えることで、各色信号のAD変換範囲を切
換える。As in FIG. 11, R, G, B
Are arranged in a mosaic pattern. In the n-th row, first, the pixel signal of the B signal column is AD-converted by the column switching control pulse Codd, and is output as AD data. Next, the pixel signals of the G signal sequence are AD-converted by the column switching control pulse Ceven and output as AD data. At this time, DA
The WB information switching signal is input to the converter 9 (9-1, 9-2, 9-3) corresponding to each color, and the DA output range is switched corresponding to each color, so that the AD conversion range of each color signal is obtained. Switch.
【0042】この様に任意の列毎にAD変換することに
よりアナログデジタル回路を少なくすることが可能とな
った。このように回路規模を少なく出来ることは回路特
性の向上あるいはチップ面積を小さくできる。As described above, it is possible to reduce the number of analog digital circuits by performing the AD conversion for each arbitrary column. Reducing the circuit scale in this way can improve the circuit characteristics or reduce the chip area.
【0043】なお、画素部は複数の光電変換部に対して
1つの共通アンプを設けるようにしてもよい。図13は
共通アンプ画素の例を示す図である。図13に示すよう
に、a11,a12,a21,a22は各画素の光電変換部とな
るフォトダイオード、MSFは共通アンプとなる増幅用ト
ランジスタ、MTX1〜MTX4はフォトダイオードに蓄積さ
れた信号電荷を共通アンプの入力部に転送する転送用ト
ランジスタ、MRESは前記共通アンプの入力部をリセッ
トするリセット用トランジスタ、MSELは共通アンプ画
素を選択する選択用トランジスタである。トランジスタ
MSF,MSELはソースフォロア回路を構成する。かかる
共通アンプ画素は4つのフォトダイオードからの信号が
共通アンプを介して出力され、4画素で一つの単位セル
を構成する。1つの画素はフォトダイオード、転送用ト
ランジスタを含み、共通アンプ,リセット用トランジス
タ、選択用トランジスタからなる共通回路の一部を含ん
でいる。フォトダイオードa11,a22にGフィルター、
フォトダイオードa21にBフィルター、フォトダイオー
ドa12にRフィルターを配置する。The pixel section may be provided with one common amplifier for a plurality of photoelectric conversion sections. FIG. 13 is a diagram illustrating an example of a common amplifier pixel. As shown in FIG. 13, a11, a12, a21, and a22 are photodiodes serving as photoelectric conversion units of each pixel, MSF is an amplifying transistor serving as a common amplifier, and MTX1 to MTX4 share signal charges accumulated in the photodiodes. A transfer transistor for transferring to the input section of the amplifier, MRES is a reset transistor for resetting the input section of the common amplifier, and MSEL is a selection transistor for selecting a common amplifier pixel. The transistors MSF and MSEL form a source follower circuit. In such a common amplifier pixel, signals from four photodiodes are output via a common amplifier, and the four pixels constitute one unit cell. One pixel includes a photodiode and a transfer transistor, and includes a part of a common circuit including a common amplifier, a reset transistor, and a selection transistor. G filters for photodiodes a11 and a22,
A B filter is disposed on the photodiode a21, and an R filter is disposed on the photodiode a12.
【0044】[0044]
【発明の効果】以上説明したように、本発明によれば、
画像信号レベルに応じてAD入力電圧範囲を設定できる
ことにより、AD変換手段の性能をフルに引き出すこと
が可能となった。As described above, according to the present invention,
Since the AD input voltage range can be set according to the image signal level, the performance of the AD converter can be fully utilized.
【0045】また、アナログデジタル変換回路規模を小
さくできるので歩留り向上、低コスト化が可能である。
画素とAD変換手段をフィードバック構成にすることで
AD精度が良く、特にアナログゲイン回路を不要とする
設計も可能となった。Further, since the scale of the analog-to-digital conversion circuit can be reduced, the yield can be improved and the cost can be reduced.
By providing the pixels and the A / D conversion means in a feedback configuration, the A / D accuracy is improved, and in particular, a design that does not require an analog gain circuit has become possible.
【0046】またホワイトバランスとγ,KNEE機能
を共用することで信号処理装置を簡略化できる。The signal processing device can be simplified by sharing the white balance and the γ and KNEE functions.
【図1】本発明の撮像装置の一実施例の全体構成図であ
る。FIG. 1 is an overall configuration diagram of an embodiment of an imaging apparatus according to the present invention.
【図2】図1の撮像装置の画素部、ノイズ除去・アナロ
グデジタル変換回路部、垂直走査回路部の概略回路図で
ある。FIG. 2 is a schematic circuit diagram of a pixel unit, a noise removal / analog-to-digital conversion circuit unit, and a vertical scanning circuit unit of the imaging apparatus of FIG.
【図3】画素部の一画素とノイズ除去・アナログデジタ
ル変換回路部を示す等価回路ブロック図である。FIG. 3 is an equivalent circuit block diagram illustrating one pixel of a pixel unit and a noise removal / analog-to-digital conversion circuit unit.
【図4】図3の回路の動作を説明するためのするための
タイミングチャートである。FIG. 4 is a timing chart for explaining the operation of the circuit of FIG. 3;
【図5】図2及び図3に示したDA変換器の一構成例の
回路図である。FIG. 5 is a circuit diagram of a configuration example of the DA converter shown in FIGS. 2 and 3;
【図6】スイッチで複数の基準電圧(E1,E2,E3)に
切換える方法を示す図である。FIG. 6 is a diagram showing a method of switching to a plurality of reference voltages (E1, E2, E3) by a switch.
【図7】アンプの帰環抵抗Rf を切換えてラダーの抵抗
値と抵抗値Rf との比を切換える方法を示す図である。7 is a diagram showing a method of switching the Kikan resistance R f of the amplifier switches the ratio of the resistance value of the ladder and the resistance value R f.
【図8】DA出力レンジを図6あるいは図7の方法によ
り切換えた時のDA出力を示す特性図である。FIG. 8 is a characteristic diagram showing DA output when the DA output range is switched by the method of FIG. 6 or FIG.
【図9】DA変換器にDA出力レンジ切換え情報として
AE情報を用いた場合を示す回路図である。FIG. 9 is a circuit diagram showing a case where AE information is used as DA output range switching information in a DA converter.
【図10】本発明の固体撮像装置の他の実施例を示す回
路図である。FIG. 10 is a circuit diagram showing another embodiment of the solid-state imaging device of the present invention.
【図11】カラー化の実施例を示す回路図である。FIG. 11 is a circuit diagram showing an embodiment of colorization.
【図12】色順次出力に本発明を応用した実施例を示す
回路図である。FIG. 12 is a circuit diagram showing an embodiment in which the present invention is applied to color sequential output.
【図13】共通アンプ画素の例を示す回路図である。FIG. 13 is a circuit diagram illustrating an example of a common amplifier pixel.
【図14】本発明の他の実施例の特性図である。FIG. 14 is a characteristic diagram of another embodiment of the present invention.
100 光学系 110 固体撮像素子 111 画素部 112 垂直走査回路部 113 アナログデジタル信号処理回路部 114 水平走査回路部 115 タイミングジェネレータ(TG)部 120 カメラ信号処理系 121 カメラ信号処理回路部 122 AE(露光)情報検出回路部 123 ホワイトバランス情報検出回路部 130 カメラCPU 140 記録・再生系 150 表示系 REFERENCE SIGNS LIST 100 optical system 110 solid-state imaging device 111 pixel unit 112 vertical scanning circuit unit 113 analog digital signal processing circuit unit 114 horizontal scanning circuit unit 115 timing generator (TG) unit 120 camera signal processing system 121 camera signal processing circuit unit 122 AE (exposure) Information detection circuit section 123 White balance information detection circuit section 130 Camera CPU 140 Recording / reproduction system 150 Display system
Claims (9)
レベルと比較基準レベルとの比較結果に基づいてデジタ
ル信号を出力するアナログデジタル変換手段と、を備え
た撮像装置であって、 前記アナログデジタル変換手段は、比較を行う前記画素
からの画素信号のレベルと前記比較基準レベルとを相対
的に可変し、前記可変を行う可変範囲を変化させること
を特徴とする撮像装置。1. An image pickup apparatus comprising: a plurality of pixels; and an analog-to-digital converter that outputs a digital signal based on a comparison result between a pixel signal level from the pixel and a comparison reference level, wherein the analog An image pickup apparatus, wherein the digital conversion means relatively varies a level of a pixel signal from the pixel to be compared and the comparison reference level, and changes a variable range in which the variation is performed.
記アナログデジタル変換手段は、前記比較基準レベルを
可変し、前記比較基準レベルの可変範囲を変化させ、前
記比較基準レベルはデジタルアナログ変換手段の出力に
よって制御されることを特徴とする撮像装置。2. The image pickup apparatus according to claim 1, wherein the analog-to-digital conversion means changes the comparison reference level and changes a variable range of the comparison reference level, and the comparison reference level is a digital-to-analog conversion means. An image pickup apparatus characterized by being controlled by an output of the image pickup apparatus.
記画素は光電変換手段と、該光電変換手段からの信号を
増幅して画素信号として出力するとともに、その画素信
号の出力レベルを変動させる制御端子を有する増幅手段
と、を有し、 前記画素信号レベルの可変は、該制御端子に加えられる
制御電圧を変えることでなされてなる撮像装置。3. The image pickup apparatus according to claim 1, wherein the pixel amplifies a signal from the photoelectric conversion unit and outputs the amplified signal as a pixel signal, and varies an output level of the pixel signal. And an amplifying unit having a control terminal, wherein the variable of the pixel signal level is performed by changing a control voltage applied to the control terminal.
記制御電圧はデジタルアナログ変換手段によって出力さ
れることを特徴とする撮像装置。4. The imaging device according to claim 3, wherein the control voltage is output by digital-to-analog conversion means.
記可変範囲の変化はAE情報に基づいて行われることを
特徴とする撮像装置。5. The imaging device according to claim 1, wherein the change of the variable range is performed based on AE information.
記可変範囲の変化は、光源情報に基づいて、前記画素信
号の色信号ごとに行われることを特徴とする撮像装置。6. The imaging apparatus according to claim 1, wherein the change of the variable range is performed for each color signal of the pixel signal based on light source information.
をアナログデジタル信号処理して出力する撮像装置にお
いて、 複数の列毎に共通のアナログデジタル信号処理手段を設
けることを特徴とする撮像装置。7. An imaging apparatus for performing analog-to-digital signal processing on signals output from a plurality of pixels for each column and outputting the same, wherein a common analog-digital signal processing unit is provided for each of a plurality of columns. .
記アナログデジタル信号処理手段は画素のノイズ除去回
路、ゲイン制御回路又はアナログデジタル変換回路を含
むことを特徴とする撮像装置。8. The imaging apparatus according to claim 7, wherein said analog-to-digital signal processing means includes a pixel noise elimination circuit, a gain control circuit, or an analog-to-digital conversion circuit.
信号毎に共通のアナログデジタル信号処理手段を利用す
ることを特徴とする撮像装置。9. The imaging apparatus according to claim 7, wherein a common analog digital signal processing unit is used for each color signal.
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