JP3308146B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device for picking up an input two-dimensional light image.

[0002]

2. Description of the Related Art An imaging apparatus using a solid-state imaging device represented by a charge-coupled device (CCD) is used in various fields including home video. However, since the charge transfer efficiency of the CCD is low, for example, when a photodiode charge having a relatively large light receiving area is handled, a problem arises in that the charge cannot be completely transferred. Therefore, in a specific field, a MOS image sensor that does not cause a problem of charge transfer efficiency is used in a solid-state imaging device.

[0003] In a MOS type image sensor, for capturing a two-dimensional light image, one discrete amplifier is provided for a two-dimensionally arranged photodiode array to amplify a light detection signal at each photodiode. The method of taking out afterwards has been conventionally adopted. In recent years, MO
Mount the readout circuit on the same chip as the photodetector and change the circuit configuration method, aiming to improve the S / N of the photodetection signal and reduce the size of the device while taking advantage of the advantages of the S-type image sensor. Has been proposed.

A typical example of such a proposal is disclosed in Japanese Patent Laid-Open No.
588 is a solid-state imaging device. FIG. 6 is a circuit configuration diagram of this device. As shown in FIG. 6, this device includes (a) a vertical light receiving section 920 in which a photoelectric conversion element 911 and a switch element 912 are vertically arranged as a set of light receiving elements 910 and are connected by a common output line. Are integrated in the light receiving section 930 in which only N2 pieces are arranged in the horizontal direction, and (b) an integrating circuit 9 having a charge amplifier 941 arranged for each vertical light receiving section 920 and integrating the output of the vertical light receiving section 920, respectively.
40, and (c) a sample-and-hold circuit 950 that samples / holds a signal output for each integration circuit 940
(D) a switch 960 for performing output / non-output to / from the sample-and-hold circuit 950, (e) a vertical shift register 971 for specifying a vertical position of a light-receiving element from which a light detection result is read, and (f). Horizontal shift register 9 for indicating the horizontal position of the light receiving element from which the light detection result is read
72.

After a light detection signal corresponding to the amount of light detected by each light receiving element is output via the video signal wiring 980, impedance conversion is performed by the buffer circuit 990.

[0006]

The conventional solid-state imaging device is constructed as described above, and the output signal of the sample-and-hold circuit 950 is directly output to the video signal wiring 980 via the switch 960. There is a problem that a partial pressure is generated due to the capacitance of the wiring 980 and the SN ratio is significantly deteriorated.

To solve this problem, if the capability of the amplifier used in the buffer circuit 990 is increased, a new problem arises in that the heat generation locally increases in the amplifier portion, and the dark current distribution becomes non-uniform. Will happen.

In addition, although each integration circuit always has its own offset variation, the above-described prior art does not suppress the variation, so that a fixed pattern noise is generated at the time of image formation. In order to correct this fixed pattern noise by an external circuit, high-speed operation is inevitable while increasing the scale of hardware.

In order to solve the above problem, it is conceivable to arrange an analog / digital converter (A / D converter) for each vertical line. Since such A / D converters are arranged in an array, it is necessary to satisfy requirements such as small hardware scale, low power consumption, and high-speed operation. As a typical example of an A / D converter satisfying such demands, Japanese Patent Application Laid-Open No. 63-24 / 1988
No. 6085 discloses an A / D converter.

This A / D converter directly inputs a charge amount Q which is a time integration value of a current generated by light reception by a light receiving element, and has a power ratio of a power of 2 (1: 2: 4:...). : 2
^N-1 ) N capacitors (capacitance = C, 2C, 4C,
.. ^2N-1 C), a switch array for controlling whether or not each capacitor forms a combined capacitance, and ON / OF of each switch of the switch array
And a comparator for controlling F. In this A / D converter, Q = CX · Vref Here, Vref: a value of CX that satisfies the reference voltage is found from a combination of capacitors in the capacitor array.

[0011] That _{is, CX = L 1 · C +} ... + L N · 2 N-1 C _{wherein, L 1, ..., L N} : 0 or 1 satisfying the _{(L 1, ..., L N} ) analog to a digital code Obtained as a digital conversion value.

However, the adoption of the above A / D converter has the following problems.

(1) The problem of accuracy Generally, the pixel area of a two-dimensional image sensor is small, and the integration time of the current is short for the purpose of collecting moving images. Therefore, since the charge amount Q is small, it is necessary to minimize the capacitance of each capacitor in the capacitor array. On the other hand, in consideration of manufacturing variations among a plurality of capacitor arrays, there is a limit in reducing the capacitance of a capacitor, and a low reference voltage is used. However, when the reference voltage is lowered, the switch is turned on when changing the combined capacitor configuration in the capacitor array.
The S / N for noise generated every time the / OFF operation is performed is deteriorated.

(2) Problems with Parasitic Capacitance In the technique disclosed in Japanese Patent Application Laid-Open No. 63-246085, the capacitance value of each capacitor is required to be accurate because the main purpose is to divide the charge into capacitance. However, it is inevitable that parasitic capacitance accompanying the wiring and junction capacitance at the switch accompany it. Assuming that such an extra capacitance component is ΔC, Q = (CX + ΔC) · Vref. ΔC is expected to become a value equivalent to the basic capacity of the capacitor array when integrated into an IC, and it is difficult to realize a highly accurate A / D converter after integrated into an IC.

[0015] The present invention has been made in view of the above, and has as its object to provide a solid-state imaging device capable of imaging with a high SN ratio.

[0016]

A solid-state imaging device according to claim 1 is a solid-state imaging device for capturing an input two-dimensional optical image, comprising: (a) a photoelectric conversion element for converting an input optical signal into a current signal; A first terminal is connected to the signal output terminal of the photoelectric conversion element, and a switch element that causes the charge generated in the photoelectric conversion element to flow out from the second terminal in response to the vertical scanning signal, as a set of light receiving elements. A vertical light receiving portion, which is arranged by a first number along the direction of 1 and has signal output terminals electrically connected to the second terminal of each of the switch elements, is arranged along the second direction. (B) a charge amplifier for inputting, amplifying and outputting a current signal from the vertical light receiving unit, and a charge amplifier connected between the input and output terminals of the charge amplifier in response to a capacitance indication signal. Variable capacitance part whose capacitance value changes discretely The current signal is individually input from each of the vertical light receiving units, and when the reset instruction signal for instructing whether or not to perform the integration operation is instructed to perform the integration operation, the current signal is output from the vertical light receiving unit. A second number of integrating circuits for accumulating charges obtained by time-integrating the accumulated current signal in the variable capacitance section, and outputting an integration signal having a value corresponding to the accumulated charge amount and the capacitance value of the variable capacitance section; (C) a second number of comparison circuits for comparing the value of the integration signal output from each of the integration circuits with a reference value and outputting the result of the comparison as a comparison result signal; and (d) A comparison result signal output from the comparison circuit is input, a capacitance indication signal indicating a capacitance value to be set for the variable capacitance section is output based on the comparison result signal, and an integration signal is output based on the comparison result signal. Value and reference value are at a given resolution If it is determined that they match, a second number of capacitance control units that output a first digital signal corresponding to the capacitance value of the variable capacitance unit based on the capacitance instruction signal; A second number of horizontal readout units each receiving the first digital signal output from the capacitance control unit and outputting a second digital signal corresponding to each of the first digital signals in accordance with a horizontal scan signal When,
It is characterized by having.

Here, it is simple from the viewpoint of the circuit configuration that the value of the first digital signal is equal to the value of the second digital signal.

The horizontal readout unit further includes a data conversion unit that receives the first digital signal output from the capacitance control unit, converts the first digital signal into data, and outputs a second digital signal. It may be characterized. Here, data conversion can be applied to offset removal. Further, the data conversion unit inputs the first digital signal to the address input terminal, performs data conversion based on the data written in the storage unit, and outputs the second digital signal from the data output terminal. An element may be provided.

According to a sixth aspect of the present invention, there is provided a solid-state imaging device for capturing an input two-dimensional optical image, comprising: (a) a photoelectric conversion element for converting an input optical signal into a current signal; A first terminal is connected to the output terminal, and a switch element that outputs a current signal generated by the photoelectric conversion element from the second terminal in response to the vertical scanning signal is provided as a set of light receiving elements along the first direction. Vertical light-receiving sections having signal output terminals electrically connected to the second terminals of the respective switch elements and arranged in a second number along the second direction. (B) an array of light receiving sections
A charge amplifier that inputs, amplifies, and outputs a current signal from the vertical light receiving unit; and a variable capacitance unit that is connected between the input and output terminals of the charge amplifier and has a capacitance value that discretely changes according to a capacitance instruction signal. The current signal output from the vertical light receiving section when the current signal is individually input from each of the vertical light receiving sections and the reset instruction signal instructing whether or not to perform the integration operation instructs to perform the integration operation. A second number of integrator circuits for accumulating the electric charge obtained by time-integration of the variable capacitance section in the variable capacitance section and outputting an integration signal having a value corresponding to the accumulated charge amount and the capacitance value of the variable capacitance section; Each time the capacitance value of the variable capacitance section of each integration circuit changes, the value of the integration signal output from each integration circuit is compared with the reference value, and the comparison result signal that is the result of the comparison is compared with the reference value. 1st output as serial digital data And (d) the comparison result signals output from the respective comparison circuits, and are variable based on the value of the comparison result signal until the value of the integrated signal matches the reference value with a predetermined resolution. (E) sequentially inputting the first serial digital data output from each of the comparison circuits, the order being the reverse of the input order; , A second number of first-in-last-out (FILO) registers that are output as second serial digital data, and (f) the respective FILs.
A second number of processing units for sequentially inputting the second serial digital data from the O register, parallelizing the second serial digital data and outputting the first parallel digital data; And a second number of horizontal readout units that respectively input the output first parallel digital data and output digital signals corresponding to the respective first parallel digital data in accordance with the horizontal scanning signal. And

Here, the processing unit further receives the second serial digital data output from the FILO register corresponding to the adjacent vertical light receiving unit, performs an operation on adjacent pixels, and executes the second parallel digital data. May be output to the horizontal readout unit.

In the solid-state image pickup device according to the first or sixth aspect, the variable capacitance section may include: (1) a third number of an integer equal to or greater than 2 in which an input terminal of the charge amplifier is connected to one of the terminals. A capacitor, and (2) the other terminal and one terminal of each capacitor are connected, and the other terminal is connected to the output terminal of the charge amplifier, and opens and closes according to the value of the capacitance instruction signal.
(3) The other terminal and one terminal of each of the capacitive elements are connected, and the other terminal is connected to the reference potential level terminal, and opened and closed according to the value of the capacitance instruction signal. And a third number of second switch elements.

Here, assuming that the third number is N, the resolution is 1/2 ^{N-1 of the} reference value, and the capacitance values of the N capacitance elements of the variable capacitance section are C _{1 to} C _N. Then, these capacitance values may satisfy the relationship of C ₁ = 2C ₂ =... = 2 ^N-1 C _N (1).

In the solid-state imaging device according to the first aspect, first, the reset instruction signal is set to a significant level, and the vertical scanning signal is set to a state in which none of the light receiving elements is selected for output. In this state, the reset instruction signal R is set to insignificant to start the integration operation in each integration circuit.

The capacitance control unit generates a capacitance instruction signal from the value of the comparison result signal so that the value of the output signal of the integration circuit becomes substantially equal to the reference value, and notifies the variable capacitance unit of the integration circuit of the capacitance instruction signal. The variable capacity unit that has received the capacity instruction changes the capacity according to the instruction. The value of the integration signal changes due to the change in the capacitance of the variable capacitance section, and the changed integration signal is input to the comparison circuit again. In this way, a feedback loop of the integration circuit-comparison circuit-capacity control unit-integration circuit is formed, and finally the value of the integration signal matches the reference value within the range of the resolution.

Next, a vertical scanning signal for turning ON only the switch element of the first light receiving element in the vertical scanning of each vertical light receiving section is output. When the switch element is turned “ON”, the electric charge accumulated in the photoelectric conversion element by the light reception up to that time is output as a current signal from the light receiving unit. Then, the electric charge flows into the variable capacitance section set to the initial capacitance value, the integration signal obtained by integration by the integration circuit is input to the comparison circuit, and the value of the integration signal is compared with the reference value. The result is input to the capacity control unit as a binary 1-bit digital signal. On the other hand, the comparison result 1-bit digital signal is input to the FILO register as first serial digital data and stored. Here, since the variable capacitance section is connected to the input terminal and the output terminal of the charge amplifier, the capacitance value can be set to a value sufficient for accuracy as a capacitance value, so that noise resistance can be improved.

The capacity control section outputs a first digital signal having a value corresponding to the capacity indication signal when the value of the integration signal matches the reference value within the range of the resolution. The first digital signals output from the capacitance control unit are input to a horizontal readout unit, and second digital signals corresponding to the respective first digital signals are sequentially and selectively selected by setting a horizontal scanning signal. Then, the signals are sequentially read as detection signals corresponding to the first light receiving element in the vertical scanning of each vertical light receiving unit.

The vertical scanning signal is set so that none of the light receiving elements is selected in consideration of the time when it is estimated that the photoelectric conversion element of the first light receiving element in the vertical scanning has completely discharged the accumulated charge. .

When the sequential reading of the detection signal corresponding to the first light receiving element of the vertical light receiving section in the vertical scanning is completed, the reset instruction signal is made significant.

Next, after the reset instruction signal is again made insignificant and the capacitance value of the variable capacitance section is set to the initial value, only the switch element of the second light receiving element in the vertical scanning of each vertical light receiving section is in the "ON" state. Is output. When the switch element is turned “ON”, the electric charge accumulated in the photoelectric conversion element by the light reception up to that time is output as a current signal from the light receiving unit.

Hereinafter, the first of the vertical light receiving portions in the vertical scanning will be described.
As in the case of the second light receiving element, detection signals corresponding to the second light receiving element of the vertical light receiving section in the vertical scanning are sequentially read.

Subsequently, while sequentially designating the light receiving elements of each vertical light receiving section, the detection according to the light receiving element of each vertical light receiving section is performed in the same manner as in the case of the first light receiving element in the vertical scanning of each vertical light receiving section. By sequentially reading out the signals, imaging data of the optical image input to the light receiving unit is collected.

Assuming that the first digital signal is directly output by the horizontal readout unit, the second digital signal and the first digital signal have the same data value. When this method is adopted, the circuit of the horizontal readout unit can be composed of only switch elements, which is simple.

If the horizontal readout unit further includes a data conversion unit that inputs the first digital signal output from the capacitance control unit, converts the data, and outputs a second digital signal, Can be appropriately processed to obtain a second digital signal having an output data value. For example, by performing the offset conversion for the data conversion, it is possible to obtain accurate data with the offset removed. As such a data conversion unit, a read-only memory that inputs a first digital signal to an address input terminal, performs data conversion based on data written to a storage unit, and outputs a second digital signal from a data output terminal Preferably, an element (ROM) is used. As a result, the second value from which the offset value is removed
Digital signal can be obtained.

The integration circuit includes a charge amplifier for receiving, amplifying and outputting an output signal from the vertical light receiving unit, and includes a variable capacitance unit and an input terminal for an output signal from the vertical light receiving unit of the charge amplifier. A third number of capacitive elements to which one of the terminals is connected, the other terminal of each of the capacitive elements is connected to one of the terminals, and the other terminal is connected to the output terminal of the charge amplifier. A third number that opens and closes according to the value of the first switch element, the other terminal and one terminal of each capacitive element are connected, the other terminal is connected to a reference potential level terminal, and a capacitance instruction signal And a third number of second switch elements that open and close according to the value of.

In this case, the capacitance control section outputs a signal for controlling the opening and closing of the first switch element and the second switch element. Then, the capacitance value of the variable capacitance section is controlled by controlling the opening and closing of the first switch element and the second switch element.

When the third number is N, in order to set the resolution to ¹ / ^N of the reference value, the capacitance values of the N capacitance elements of the variable capacitance section should be C ₁ to C _{1. Assuming} that _N , these capacitance values preferably satisfy the following relationship: C ₁ = 2C ₂ =... = 2 ^N-1 C _N (1) According to this configuration, when the capacitance control unit controls the opening and closing of the first and second switch elements from the capacitance element having a large capacitance value, and sequentially compares the value of the integration signal with the reference value by the comparison circuit, Third
With a capacity instruction of the number of times, accuracy measurement with a resolution of 1/2 ^N can be performed.

In the solid-state imaging device according to the sixth aspect, first, the reset instruction signal is set to be significant, and the vertical scanning signal is set to a state in which no light-receiving element is selected for output. In this state, the reset instruction signal R is set to insignificant to start the integration operation in each integration circuit.

Next, a vertical scanning signal for turning ON only the switch element of the first light receiving element in the vertical scanning of each vertical light receiving section is output. When the switch element is turned “ON”, the electric charge accumulated in the photoelectric conversion element by the light reception up to that time is output as a current signal from the light receiving unit. Then, the electric charge flows into the variable capacitance section set to the initial capacitance value, the integration signal obtained by integration by the integration circuit is input to the comparison circuit, and the value of the integration signal is compared with the reference value. The result signal is input to the capacity control unit. Here, since the variable capacitance section is connected to the input terminal and the output terminal of the charge amplifier, the capacitance value can be set to a value sufficient for accuracy as a capacitance value, so that noise resistance can be improved.

The capacitance control unit generates a capacitance instruction signal from the value of the comparison result signal so that the value of the output signal of the integration circuit becomes substantially equal to the reference value, and notifies the variable capacitance unit of the integration circuit of the capacitance control signal. The variable capacity unit that has received the capacity instruction changes the capacity according to the instruction. The value of the integration signal changes due to the change in the capacitance of the variable capacitance section, and the changed integration signal is input to the comparison circuit again. Then, each time the capacitance value of the variable capacitance section changes, the first serial digital data is sequentially transmitted from the comparison circuit to the FILO.
Input to a register and stored.

In this way, a feedback loop of the integrating circuit, the comparing circuit, the capacitance control section, and the integrating circuit is formed, and the value of the integrated signal finally matches the reference value within the range of the resolution.

In the case where the variable capacitance section is composed of capacitances having the capacitance values represented by the equation (1), the capacitance control section converts the capacitance having the maximum capacitance value (C ₁ ) into a combined capacitance. Are preferably determined in order from the contribution / non-contribution of In such a case, the MSB (Most Signi?
LSB (Least Significant Bi)
Until t) is output as the first serial digital data.

When the value of the integration signal matches the reference value within the range of the resolution, the processing unit reads the second serial digital data in the reverse order of the bit order of the first serial digital data from the FILO register, Output as the first parallel digital data. The first parallel digital data output from the processing unit is input to a horizontal readout unit, and a second digital signal corresponding to each of the first parallel digital data is sequentially and selectively set by setting a horizontal scanning signal. The selected signal is sequentially read out as a detection signal corresponding to the first light receiving element in the vertical scanning of each vertical light receiving unit.

The vertical scanning signal is set so that none of the light receiving elements is selected in consideration of the time when it is estimated that the photoelectric conversion element of the first light receiving element in the vertical scanning has completely discharged the accumulated charge. .

When the sequential reading of the detection signal corresponding to the first light receiving element of the vertical light receiving section in the vertical scanning is completed, the reset instruction signal is made significant.

Next, after the reset instruction signal is again made insignificant and the capacitance value of the variable capacitance section is set to the initial value, only the switch element of the second light receiving element in the vertical scanning of each vertical light receiving section is in the "ON" state. Is output. When the switch element is turned “ON”, the electric charge accumulated in the photoelectric conversion element by the light reception up to that time is output as a current signal from the light receiving unit.

Thereafter, the first of the vertical light receiving sections in the vertical scanning
As in the case of the second light receiving element, detection signals corresponding to the second light receiving element of the vertical light receiving section in the vertical scanning are sequentially read.

Subsequently, while sequentially designating the light receiving elements of each vertical light receiving section, detection according to the light receiving element of each vertical light receiving section is performed in the same manner as in the case of the first light receiving element in the vertical scanning of each vertical light receiving section. By sequentially reading out the signals, imaging data of the optical image input to the light receiving unit is collected.

Here, the processing unit further inputs the second serial digital data output from the FILO register corresponding to the adjacent vertical light receiving unit, and performs an operation on adjacent pixels, for example, an outline extraction operation of a moving image or the like. To output the second parallel digital data to the horizontal readout unit.

[0049]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a solid-state imaging device according to the present invention will be described with reference to the accompanying drawings. In the description of the drawings, the same elements will be denoted by the same reference symbols, without redundant description.

(First Embodiment) FIG. 1 is a circuit diagram of a solid-state imaging device according to a first embodiment of the present invention. As shown in FIG. 1, this device includes (a) a photoelectric conversion element 130 for converting an input optical signal into a current signal, and a signal output terminal of the photoelectric conversion element 130, and a vertical scanning signal V _i (i = 1 ~ N
And a switch element 140 for flowing out a current signal generated by the photoelectric conversion element 130 according to 1).
The vertical light receiving units 110 arranged N1 along the first direction (hereinafter, referred to as a vertical direction) and electrically connected to the signal output terminals of the respective switch elements 140 correspond to the second direction (hereinafter, referred to as the vertical direction). , Horizontal direction), and (b) vertical light receiving units 110 _j (j = 1
To N2), the signal processing unit 200 includes a horizontal signal processing unit 210 _j that individually outputs a signal according to a horizontal scanning signal (H _j ) after signal processing.
And (c) a timing control unit 30 for notifying the light receiving unit 100 and the signal processing unit 200 of an operation timing instruction signal.
0.

The horizontal signal processing section 210 _j receives the output signal from the vertical light receiving section 110 _j and outputs a reset instruction signal R
Vertical current signal output from the light receiving unit 110 _j is connected between the input and output terminals, the integral (the case of a reset instruction signal R = non-significant) in the variable capacitance portion 222, or a non-integral (reset instruction signal R in response to = Significant), a comparison circuit 230 that compares the value of the integration signal V _S output from the integration circuit 220 with a reference value V _REF and outputs a comparison result, and a comparison circuit. receives the comparison result signal V _C output from 230, comparison outputs a capacitance instruction signal C to notify the result variable capacitance portion 222 from the value of the signal V _C, the comparison result from the signal V _C of the integral signal V _S value When it is determined that the reference value _VREF and the reference value _VREF match at a predetermined resolution, a capacity control mechanism 240 that outputs a digital signal D1 corresponding to the capacity instruction signal C, and a digital signal output from the capacity control mechanism 240. Faith Enter the D1, after generating a digital signal D2 indicating a data value obtained by removing the predetermined offset value from the data value indicated by the digital signal D1, in response to the horizontal scanning signal H _j, horizontal read for outputting the digital signal D2 Unit 250.

The integrating circuit 220 includes a vertical light receiving section 110 _j
And a charge amplifier 221 for receiving an output signal from the amplifier and amplifying the charge of the input current signal, one terminal connected to the input terminal of the charge amplifier 221, and the other terminal connected to the output terminal of the charge amplifier 221. A variable capacitance section 222;
One terminal is connected to the input terminal of the charge amplifier 221,
A second terminal connected to the output terminal of the charge amplifier 221;
When the reset instruction signal R = significant, the state becomes “ON”, and when the reset instruction signal R = insignificant, “OFF”.
And a switching element 223 to be in a state.

FIG. 2 is a circuit configuration diagram of the integration circuit 220, and particularly shows a detailed circuit configuration of the variable capacitance section 222. FIG. 2 shows an example of an integrating circuit having an analog-to-digital conversion function having a resolution of 1/2 ³ = １ ／, and this circuit configuration will be described below.

As shown in FIG. 2, the variable capacitance section 222
A capacitor C1~C4 the input terminal and the respective one of the terminals of the output signals from the vertical light receiving section 110 _j is connected to charge amplifier 221, one terminal is connected to the other terminal of each of the capacitive elements C1~C4 And the other terminal is the charge amplifier 2
It is connected to the 21 output terminal of, C ₁₁ of the capacitor instruction signal C -C
Switch elements SW11 to SW1 that open and close according to the value of ₁₄
4, is connected to the other terminal and the one terminal of each of the capacitive elements C1 -C4, the other terminal is connected to the GND level, to open and close depending on the value of C ₂₁ -C ₂₄ of the capacitance instruction signal C switches Elements SW21 to SW24 are provided. The capacity value C ₁ -C ₄ capacitive element C1~C4 is a relation _{C 1 = 2C 2 = 4C 3} = 8C 4 ... (2) C 1 + C 2 + C 3 + C 4 = C 0 ... (3) Fulfill.

The horizontal read section 250 inputs the digital signal D1 output from the capacity control mechanism 240 to an address input terminal, performs data conversion based on the data written in the storage section, and outputs the digital signal D1 from the data output terminal.
Read-only storage element (ROM) 251 for outputting 2
When the digital signal D2 output from the ROM251 entered in one terminal, and a switch element 252 that switches and a "ON" state and "OFF" state in accordance with the specification of the horizontal scanning signal H _j.

[0056] The timing control unit 300, a basic timing unit 310 for generating a basic timing signal in accordance with a vertical scanning instruction notified from the basic timing unit 310, the vertical shift register 3 for generating a vertical scanning signal V _i
20, in accordance with the horizontal scanning instruction notified from the basic timing unit 310, a horizontal shift register 330 for generating a horizontal scanning signal H _j, according to the basic timing notified from the basic timing unit 310, a control for generating a reset instruction signal R A signal section 340.

The device of the present embodiment is as follows:
The optical image data input to the light receiving unit 100 is collected. FIG.
FIG. 3 is an operation explanatory diagram of the device of the present embodiment.

In the solid-state imaging device according to the present embodiment, first, the reset instruction signal R is significantly set, all the switches SW11 to SW14 are turned on, and all the switches SW21 to SW24 are set to "OF".
The capacitance between the input terminal and the output terminal of the charge amplifier 221 as F "state and sets the C _0, the vertical scanning signal V _i to any of the light receiving element 120 i, _j do not select state (i.e., all Switch element 140 is "OFF"
State). In this state, the reset instruction signal R is set to be insignificant, and the integration operation in each integration circuit 220 is started.

Next, the switch elements 1 of the first light receiving element 120 _{1, j} in the vertical scanning of the vertical light receiving section 110 _j
40 only outputs a vertical scanning signal V ₁ to "ON". When the switch element 140 is turned “ON”, the electric charge accumulated in the photoelectric conversion element 130 by the light reception up to that time is output from the light receiving unit 100 as a current signal. Then, the variable capacitance section 222 set to the initial capacitance value C ₀
(See FIG. 3A).

Subsequently, the capacity control mechanism 240 switches SW1
After opening SW2 to SW13, SW22 to SW24 are closed (see FIG. 3B). As a result, the integrated signal V _S outputs a voltage value of V _S = Q / C ₁ . This voltage value is supplied to the comparison circuit 23
0 and is compared with a reference voltage value V _REF .

If V _S > V _REF , upon receiving this comparison result, the capacity control mechanism 240 further closes SW 12 after opening SW 22 (see FIG. 3C). As a result,
The integrated signal V _S outputs a voltage value of V _S = Q / (C ₁ + C ₂ ). This voltage value is supplied to the comparison circuit 23
0 and is compared with a reference voltage value V _REF .

If V _S <V _REF , the capacity control mechanism 240 receives the result of this comparison, and then closes SW 12 and SW 21 after opening SW 11 and SW 22 (see FIG. 4B). As a result, the integrated signal V _S outputs a voltage value of V _S = Q / C ₂ . This voltage value is supplied to the comparison circuit 23
0 and is compared with a reference voltage value V _REF .

Thereafter, in the same manner, the comparison and the capacity setting (S) are performed by the feedback loop of the integrating circuit 220, the comparing circuit 230, the capacity control mechanism 240, and the integrating circuit 220.
"ON / OF" of W11-SW14, SW21-SW24
F ”control) is sequentially repeated to perform the capacitance control up to the capacitance element C4. When the capacitance control is completed for all of the capacitance elements C1 to C4, the capacitance control mechanism 240
Outputs a digital signal D1 corresponding to the final capacitance setting to the horizontal readout unit 250.

In the horizontal read unit 250, the digital signal D1 is input to the address input terminal of the ROM 251, and data conversion is performed based on the data written in the storage unit.
The digital signal D2 is output from the data output terminal. RO
The digital signal D2 output from M251 is input to the switch element 252. Subsequently, the output of the ROM251 respective sequential by setting the horizontal scanning signal H _j, and alternatively selected, first in the vertical scanning of the vertical light receiving section 110 _j
The detection signals corresponding to the light receiving elements 1201 _{, j} are sequentially read.

As a result, digital signal D 2 is output from switch element 252, so that video signal wiring 400
Is not affected by the voltage division by the capacitance of the analog signal. In addition, an external analog-to-digital converter, which is conventionally required, becomes unnecessary.

The vertical scanning signal V ₁ is set so that the light receiving element is not selected in consideration of the time when it is estimated that the charge accumulated in the photoelectric conversion element of the first light receiving element in the vertical scanning has been completely discharged. .

[0067] For sequential reading of the detection signal corresponding to the first light receiving element 120 1, _j vertical light receiving section 110 _j in the vertical scanning is completed, a significant reset instruction signal R.

Next, the reset instruction signal R is again changed to insignificant,
After the capacitance value of the variable capacitance section 222 has an initial value C _0, the vertical scanning only the switch element 140 of the second light receiving element 120 2, _j in the vertical scanning of the vertical light receiving section 110 _j to "ON" state and it outputs a signal V _2. When the switch element is turned “ON”, the electric charge accumulated in the photoelectric conversion element 130 by the light reception up to that time is output as a current signal from the light receiving unit.

Thereafter, the vertical light receiving section 110 in the vertical scanning
in the same manner as in the first light receiving element 120 1, _j of the _j, sequentially reads a detection signal corresponding to the second light receiving element 120 2, _j of the vertical light receiving section 110 _j in the vertical scanning.

Subsequently, while sequentially designating the light receiving elements 120 _{i, j} of each vertical light receiving section 110 _j ,
_{In the same} manner as in the case of the _first light receiving element 1201 _{, j} in the vertical scanning of _j , the light receiving element 1 of each vertical light receiving section 110j
By sequentially reading out the detection signals corresponding to 20 _{i, j} ,
The imaging data of the light image input to the light receiving unit is collected.

(Second Embodiment) The device of this embodiment is different from the device of the first embodiment in that the integration circuit 220 has a different circuit configuration, and the electric charge stored in the photoelectric conversion element 130 is extremely small. In this case, the solid-state imaging device ensures an SN ratio.

FIG. 4 is a circuit configuration diagram of the integration circuit 290 of the present embodiment. As shown in FIG.
A charge amplifier 221 that receives an output signal from the vertical light receiving unit 110 _j and amplifies the charge of the input current signal;
A variable capacitance section 229 having one terminal connected to the input terminal of the charge amplifier 221 and the other terminal connected to the output terminal of the charge amplifier 221, and one terminal connected to the input terminal of the charge amplifier 221; A second terminal is connected to the output terminal of the reset instruction signal R. When the reset instruction signal R = significant, the output terminal is turned on and the reset instruction signal R =
The switch element 2 which is in the “OFF” state in the case of insignificance
23.

The variable capacitance section 229 has, in addition to the variable capacitance section 222, one terminal connected to the input terminal side of the charge amplifier 221 of each of the capacitance elements C1 to C3, and the other terminal connected to the vertical terminal of the charge amplifier 221. switching element SW31~S connected to the input terminal of the output signals from the light receiving portion 110 _j
A switch element SW41 in which W33 is connected to one terminal of each of the input terminals of the charge amplifier 221 of the capacitive elements C1 to C3, and the other terminal is connected to the GND level.
To SW43. And the capacity control mechanism 2
40, a signal C for ON / OFF control of the switch elements SW31 to SW33 and the switch elements SW41 to SW43.
_{31 ~C 33,} C _{41 ~C 43} is further supplied.

The device of this embodiment is as follows:
The optical image data input to the light receiving unit 100 is collected.

In the solid-state imaging device according to the present embodiment, first, the reset instruction signal R is significantly changed to SW11 to SW14, SW
41 to 43 are all set to the “ON” state, and SW21 to SW2
4, C ₄ a capacitance value between the input terminal of the charge amplifier 221 as all "OFF" state SW31~33 output terminal
And sets the vertical scanning signal V _i to any of the light receiving element 120 i, _{state j} do not select (i.e., all the switch elements 140 are "OFF" state) is set to. In this state, the reset instruction signal R is set to be insignificant, and the integration operation in each integration circuit 220 is started.

[0076] Next, switching element 1 of the first light receiving element 120 _{1, j} in the vertical scanning of the vertical light receiving section 110 _j
40 only outputs a vertical scanning signal V ₁ to "ON". When the switch element 140 is turned “ON”, the electric charge accumulated in the photoelectric conversion element 130 by the light reception up to that time is output from the light receiving unit 100 as a current signal. Then, the electric charge Q flows into the variable capacitance section 229 in which the initial capacitance value C _{4 is} set.

At this time, the integrated signal V _S outputs a voltage value of V _S = Q / C ₄ .

Next, after SW41 to SW43 are turned off, SW31 to SW33 are turned on. Even if such a change occurs, the voltage relationship between both ends of the capacitors C1 to C3 does not change, and the value of V _S does not change.
Total charge generated in the C4 becomes _{Q '= Q · (C 0} / C 4). That is, compared to the first embodiment, (C ₀ / C
₄ ) Double charges will be accumulated.

Thereafter, similarly to the first embodiment, the optical image data input to the light receiving section 100 is collected. Therefore, S / N can be secured even when the charge stored in the photoelectric conversion element 130 is extremely small.

(Third Embodiment) FIG. 5 is a circuit diagram of a solid-state imaging device according to a third embodiment of the present invention. As shown in FIG. 5, this device includes (a) a photoelectric conversion element 130 for converting an input optical signal into a current signal, and a signal output terminal of the photoelectric conversion element 130, and a vertical scanning signal V _i (i = 1 ~ N
And a switch element 140 for flowing out a current signal generated by the photoelectric conversion element 130 according to 1).
The vertical light receiving units 110 arranged N1 along the first direction (hereinafter, referred to as a vertical direction) and electrically connected to the signal output terminals of the respective switch elements 140 correspond to the second direction (hereinafter, referred to as the vertical direction). , Horizontal direction), and (b) vertical light receiving units 110 _j (j = 1
To N2) individually, and after signal processing, a signal processing unit 500 including a horizontal signal processing unit 510 _j that selectively outputs a signal according to a horizontal scanning signal (H _j ).
And (c) a timing control unit 30 that notifies the light receiving unit 100 and the signal processing unit 500 of an operation timing instruction signal.
0.

The horizontal signal processing section 510 _j receives the output signal from the vertical light receiving section 110 _j and outputs a reset instruction signal R
Vertical current signal output from the light receiving unit 110 _j is connected between the input and output terminals, the integral (the case of a reset instruction signal R = non-significant) in the variable capacitance portion 222, or a non-integral (reset instruction signal R in response to = Significant) and the signal V output from the integration circuit 220
Clamp circuit 521 for removing noise superimposed on _S ′
And the integrated signal V _S output from the clamp circuit 521.
The values are compared with respective reference values V _REF, the comparative circuit 230 for outputting the result, and inputs the comparison result signal V _C is 1-bit two-level signal outputted from the comparison circuit 230, the comparison result signal V A capacity control mechanism 240 that outputs a capacity instruction signal C that notifies the variable capacity unit 222 from the value of _C ;
The comparison result signal V _C output from the comparison circuit 230 sequentially inputs the serial digital data, the FILO register 522 outputs serial digital data of the reverse order of the input order, is output from the FILO register 522 of its own system Serial digital data and adjacent FILO
A processing unit 523 for outputting the first parallel digital signals parallelized after operation to input the serial digital data sequentially output from the register 522, the processing unit 523 inputs the parallel digital signal, the horizontal scanning signal H _j A horizontal readout switch 252 for outputting a digital signal.

The device of the present embodiment is as follows:
The optical image data input to the light receiving unit 100 is collected.

The device of this embodiment is as follows:
The optical image data input to the light receiving unit 100 is collected.

In the solid-state imaging device according to the present embodiment, similarly to the first embodiment, first, the reset instruction signal R is significantly changed to S.
W11 to SW14 are all set to the “ON” state, and SW21 to SW14 are
SW 24 is set to the “OFF” state, and charge amplifier 221 is set.
The capacitance between the input terminal and the output terminal is set to C ₀ , and the vertical scanning signal V _i is
_The state is set such that neither _i nor _j is selected (ie, all switch elements 140 are in the “OFF” state). In this state,
The reset instruction signal R is set to be insignificant and each of the integration circuits 22
The integration operation at 0 is started.

[0085] Then, as in the first embodiment, the first light receiving element in the vertical scanning of the vertical light receiving section 110 _j 12
A vertical scanning signal V ₁ that turns ON only the switch elements 140 of _{01 and j} is output. When the switch element 140 is “O
N ", the photoelectric conversion element 1
The electric charge accumulated in the light receiving unit 30 becomes a current signal.
Output from Then, the electric charge Q flows into the variable capacitance section 222 set to the initial capacitance value C ₀ .

Subsequently, similarly to the first embodiment, the capacity control mechanism 240 opens the switches SW12 to SW13,
Close W22 to SW24. As a result, the integration signal V
_S outputs a voltage value of V _S = Q / C ₁ . This voltage value is supplied to the comparison circuit 23
0 and is compared with a reference voltage value V _REF .

If V _S > V _REF , the capacity control mechanism 240 receives this comparison result, and further closes SW 12 after opening SW 22. As a result, the integrated signal V _S outputs a voltage value of V _S = Q / (C ₁ + C ₂ ). This voltage value is supplied to the comparison circuit 23
0 and is compared with a reference voltage value V _REF .

If V _S <V _REF , the capacity control mechanism 240 receives this comparison result, further opens SW 11 and SW 22, and then closes SW 12 and SW 21. As a result, the integrated signal V _S outputs a voltage value of V _S = Q / C ₂ . This voltage value is supplied to the comparison circuit 23
0 and is compared with a reference voltage value V _REF . And
Each time the capacitance value of the variable capacitance section 222 changes, the value from MSB to L
To the SB, serial digital data is sequentially input from the comparison circuit 230 to the FILO register 522 and stored.

Thereafter, in the same manner, the comparison and the capacity setting (S) are performed by the feedback loop of the integrating circuit 220, the comparing circuit 230, the capacity control mechanism 240, and the integrating circuit 220.
"ON / OF" of W11-SW14, SW21-SW24
By repeating the “F” control sequentially, the capacitance control up to the capacitance element C4 is performed. When the capacitance control is completed for all of the capacitance elements C1 to C4 in this manner, the comparison circuit 230 terminates the output capacitance up to the LSB of the serial digital data, and the FILO register 522 receives the input of data for one pixel of the own system. finish.

The processing unit 523 inputs serial digital data from the FILO register 522 of the own system in the bit order from LSB to MSB, and inputs serial digital data from the FILO register 522 of the adjacent system to the bit order from LSB to MSB. To enter. After the calculation of the contour extraction, the calculation result is output to the horizontal readout switch 252 as a parallel digital data signal.

[0091] In the horizontal reading unit 250, the processing unit 523 inputs the parallel digital data signal output from the vertical light receiving section 110 based on the horizontal scanning signal H _j
The detection signal corresponding to the _first light receiving element 1201 _{, j} in the vertical scanning of _j is sequentially output.

As a result, a digital signal is output from the horizontal read switch 252, so that the video signal wiring 4
The effect of the voltage division by the capacity of 00 is not affected as in the case of the analog signal. In addition, an external analog-to-digital converter, which is conventionally required, becomes unnecessary.

The vertical scanning signal V ₁ is set so that the light receiving element is not selected in view of the time when it is estimated that the photoelectric conversion element of the first light receiving element in the vertical scanning has completely discharged the accumulated charge. .

[0094] For sequential reading of the detection signal corresponding to the first light receiving element 120 1, _j vertical light receiving section 110 _j in the vertical scanning is completed, a significant reset instruction signal R.

Next, the reset instruction signal R is again changed to insignificant,
After the capacitance value of the variable capacitance section 222 has an initial value C _0, the vertical scanning only the switch element 140 of the second light receiving element 120 2, _j in the vertical scanning of the vertical light receiving section 110 _j to "ON" state and it outputs a signal V _2. When the switch element is turned “ON”, the electric charge accumulated in the photoelectric conversion element 130 by the light reception up to that time is output as a current signal from the light receiving unit.

Thereafter, the vertical light receiving section 110 in the vertical scanning
in the same manner as in the first light receiving element 120 1, _j of the _j, sequentially reads a detection signal corresponding to the second light receiving element 120 2, _j of the vertical light receiving section 110 _j in the vertical scanning.

Subsequently, while sequentially designating the light receiving elements 120 _{i, j} of each vertical light receiving section 110 _j ,
_{In the same} manner as in the case of the _first light receiving element 1201 _{, j} in the vertical scanning of _j , the light receiving element 1 of each vertical light receiving section 110j
By sequentially reading out the detection signals corresponding to 20 _{i, j} ,
The imaging data of the light image input to the light receiving unit is collected.

Note that the present embodiment can also be modified in the same manner as the second embodiment with respect to the first embodiment.

The present invention is not limited to the above embodiment, but can be modified. For example, in the first embodiment, it is possible to adopt a simple circuit configuration by setting the horizontal readout unit to only the switch element 252. However, in this case, since the offset value cannot be compensated for each horizontal processing unit, the measurement accuracy is expected to be lower than in the above embodiment.

[0100]

As described in detail above, according to the solid-state imaging device of the present invention, a photodetection signal is output from the horizontal reading section after digitization with a simple circuit configuration including a charge amplifier. Therefore, the partial voltage due to the capacitance of the video signal wiring does not substantially affect the accuracy as in the case of the analog signal, so that the imaging data of the optical image input to the light receiving unit can be collected with high accuracy.

Further, since digitization is performed before horizontal reading, an external analog-to-digital converter is not required, and the apparatus can be simply configured.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a solid-state imaging device according to a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of an integration circuit of the solid-state imaging device according to the first embodiment of the present invention.

FIG. 3 is an operation explanatory diagram of the solid-state imaging device according to the first embodiment of the present invention;

FIG. 4 is a circuit configuration diagram of an integration circuit of a solid-state imaging device according to a second embodiment of the present invention.

FIG. 5 is a circuit configuration diagram of a solid-state imaging device according to a third embodiment of the present invention.

FIG. 6 is a circuit configuration diagram of a conventional solid-state imaging device.

[Explanation of symbols]

100 light receiving section, 110 vertical light receiving section, 120 light receiving element, 130 photoelectric conversion element, 140 switching element, 2
00: signal processing unit, 210: horizontal signal processing unit, 220,
290: integration circuit, 221: charge amplifier, 222, 22
9: capacitance element, 223: switch element, 230: comparison circuit, 240: capacitance control mechanism, 250: horizontal readout unit,
251 ROM, 252 switch element, 300 timing control section, 310 basic timing section, 320 vertical shift register, 330 horizontal shift register, 34
0: control signal section, 400: video signal wiring, 521: clamp circuit, 522: FILO register, 523: processing unit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/335 H01L 27/146

Claims (9)

(57) [Claims] 1. A solid-state imaging device for capturing an input two-dimensional optical image, wherein a photoelectric conversion element that converts an input optical signal into a current signal, and a first terminal is connected to a signal output terminal of the photoelectric conversion element. And
A switch element that outputs a current signal generated by the photoelectric conversion element from a second terminal in response to a vertical scanning signal, and a first number of the switch elements are arranged along a first direction as a set of light receiving elements. A vertical light receiving section having a signal output terminal electrically connected to a second terminal of each of the switch elements, a light receiving section arranged by a second number along a second direction; A charge amplifier that inputs, amplifies, and outputs a current signal from a light receiving unit; and a variable capacitance unit that is connected between the input and output terminals of the charge amplifier and that has a capacitance value that discretely changes according to a capacitance instruction signal. When the current signal is individually input from each of the vertical light receiving units, and the reset instruction signal for instructing whether to perform the integration operation is instructed to perform the integration operation, the current signal is output from the vertical light receiving unit. Time integration of the current signal A second number of integrating circuits for accumulating the electric charges stored in the variable capacitance section, and outputting an integrated signal having a value corresponding to the amount of the accumulated electric charge and the capacitance value of the variable capacitance section; and A second number of comparison circuits for comparing the magnitude of the output integrated signal with a reference value and outputting the magnitude comparison result as a comparison result signal; and the comparison result output from each of the comparison circuits. A signal is input, and the capacitance indicating signal indicating the capacitance value to be set for the variable capacitance section is output based on the comparison result signal, and the value of the integration signal is set based on the comparison result signal. When it is determined that the reference value matches with a predetermined resolution, a second digital signal corresponding to the capacitance value of the variable capacitance unit is output based on the capacitance instruction signal. A capacity control unit for the number, A second number for inputting the first digital signal output from each of the capacitance control units and outputting a second digital signal corresponding to each of the first digital signals in accordance with a horizontal scanning signal; And a horizontal readout unit. 2. The method according to claim 1, wherein a value of said first digital signal and said second digital signal are
2. The solid-state imaging device according to claim 1, wherein the value of the digital signal is the same. 3. The horizontal read unit receives the first digital signal output from the capacitance control unit, converts the first digital signal into data, and outputs the second digital signal. The solid-state imaging device according to claim 1, further comprising a conversion unit. 4. The solid-state imaging device according to claim 3, wherein said data conversion is offset removal. 5. The data conversion unit inputs the first digital signal to an address input terminal, performs data conversion based on data written in a storage unit, and outputs the second digital signal from a data output terminal. The solid-state imaging device according to claim 3, further comprising a read-only storage element that outputs a signal. 6. A solid-state imaging device for capturing an input two-dimensional optical image, wherein a photoelectric conversion element for converting an input optical signal into a current signal, and a first terminal is connected to a signal output terminal of the photoelectric conversion element. And
A switch element that outputs a current signal generated by the photoelectric conversion element from a second terminal in response to a vertical scanning signal, and a first number of the switch elements are arranged along a first direction as a set of light receiving elements. A vertical light receiving section having a signal output terminal electrically connected to a second terminal of each of the switch elements, a light receiving section arranged by a second number along a second direction; A charge amplifier that inputs, amplifies, and outputs a current signal from a light receiving unit; and a variable capacitance unit that is connected between the input and output terminals of the charge amplifier and that has a capacitance value that discretely changes according to a capacitance instruction signal. When the current signal is individually input from each of the vertical light receiving units, and the reset instruction signal for instructing whether to perform the integration operation is instructed to perform the integration operation, the current signal is output from the vertical light receiving unit. Time integration of the current signal A second number of integration circuits for accumulating the electric charges stored in the variable capacitance section, and outputting an integration signal having a value corresponding to the accumulated charge amount and the capacitance value of the variable capacitance section; For each change in the capacitance value of the variable capacitance section, the value of the integration signal output from each of the integration circuits is compared in magnitude with a reference value, and a comparison result signal that is the magnitude comparison result is converted to a first serial signal. A second number of comparison circuits for outputting as digital data, the comparison result signals output from the respective comparison circuits being input, and the above-mentioned comparison circuit until the value of the integration signal matches the reference value with a predetermined resolution. A second output unit that outputs the capacitance instruction signal that notifies the variable capacitance unit based on the value of the comparison result signal;
And the second serial digital data that is sequentially input with the first serial digital data output from each of the comparison circuits and is output as the second serial digital data in the reverse order of the input order. A first in-last out register, and a second in which the second serial digital data is sequentially input from the respective first in-last out registers, the second serial digital data is parallelized, and the first parallel digital data is output. And the first parallel digital data output from each of the processing units is input, and a digital signal corresponding to each of the first parallel digital data is output according to a horizontal scanning signal. And a second number of horizontal readout units. 7. The processing unit further inputs the second serial digital data output from the first in-last-out register corresponding to the adjacent vertical light receiving unit, and performs an operation on adjacent pixels. The solid-state imaging device according to claim 6, wherein the second parallel digital data is output to the horizontal readout unit. 8. The variable capacitance section includes: a third number of capacitance elements, each of which is an integer of 2 or more, connected to an input terminal of the charge amplifier and one of the terminals, and the other of the respective capacitance elements A third number of first switch elements, one of which is connected to one of the terminals, the other of which is connected to the output terminal of the charge amplifier, and which opens and closes in accordance with the value of the capacitance instruction signal; A third number of second switch elements, wherein the other terminal of the element is connected to one terminal, the other terminal is connected to the reference potential level terminal, and the switch is opened and closed according to the value of the capacitance instruction signal. 7. The solid-state imaging device according to claim 1, wherein: 9. Assuming that the third number is N, the resolution is 2 ^{N− 1} / 1 of the reference value, and the capacitance value of each of the N capacitance elements of the variable capacitance section is C _1. When -C _N, these capacitance values each _{other, C 1 = 2C 2 = ···} = 2 N-1 C N solid-state imaging device according to claim 8, wherein a satisfies the relationship.