JP2001320606A - Signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal processing circuit that converts a received analog signal into a digital signal and can automatically adjust the sensitivity. SOLUTION: The signal processing circuit uses a controlled variable required to make an input signal voltage V in matching with a reference voltage Vref for a digital conversion value of the input signal voltage. The signal processing circuit stores a maximum value of the luminance of an input image to a solid- state image pickup element 1 denoted by the digital signal, converts it into an analog signal and feeds it back to an input of a comparator 60 as the Vref. Even when the luminance of the input image is remarkably increased and gets higher, the controlled variable is not saturated and when the luminance is not increased, and the analog signal with a small luminance can be analog/digital- converted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a signal processing circuit, and more particularly, to a signal processing circuit for converting a video signal output from a solid-state imaging device into a digital signal.

[0002]

2. Description of the Related Art Conventionally, there has been known a signal processing circuit for processing an output signal from a sensor such as a solid-state imaging device. The present inventors have developed such a signal processing circuit. For example, the signal processing circuit described in Japanese Patent Application Laid-Open No. 2000-32342 performs A / D conversion while performing offset double noise by performing correlated double sampling (CDS) on an output signal from a sensor. Demonstrates excellent characteristics.

That is, in this signal processing circuit,
An analog signal from the input sensor is converted into a voltage signal based on the variable capacitance, the converted signal voltage and the reference voltage are input to a comparator, and the signal voltage and the reference are output based on the output of the comparator. The variable capacitance is controlled so that the voltage matches the voltage, and the control amount is output as a digital amount.

[0004]

However, in the conventional signal processing circuit, the output in the image cannot be automatically adjusted. The present invention relates to an improvement of such a signal processing circuit, and it is an object of the present invention to provide a signal processing circuit capable of converting an input analog signal into a digital signal and performing automatic output adjustment. .

[0005]

In order to solve the above problems, a signal processing circuit according to the present invention converts an analog signal input from a solid-state imaging device into a signal voltage based on a variable parameter, and converts the signal voltage into a reference voltage. And a voltage to a comparator, based on the output of the comparator, a variable parameter is controlled so that the signal voltage and the reference voltage coincide, and a signal processing circuit that outputs the control amount as a digital signal. The maximum value or the average value of the luminance of the input image to the solid-state imaging device indicated by the digital signal is stored within a predetermined period, the stored maximum value or the average value is converted into an analog signal, and the comparator is used as the reference voltage as the reference voltage. It is characterized by returning to the input. The conversion may be any of converting a charge signal into a voltage signal, converting a current signal into a voltage signal, and converting an input voltage signal into a voltage signal different from the input signal.

According to this circuit, the analog signal input from the solid-state imaging device is converted into a voltage signal, and control is performed so as to change a variable parameter until the signal voltage input to the comparator matches the reference voltage. As a result, the control amount is output as a digital signal. However, if the set value of the reference voltage increases, the control amount until the above-mentioned matching is performed increases, so that the luminance indicated by the digital signal indicated as the control amount Increases.

If the reference voltage is fixed, the brightness of the input image increases significantly, and if the voltage signal input to the comparator increases, the control amount becomes saturated and constant. I will. If the reference voltage is set to be large from the beginning, such saturation can be suppressed, but when the luminance is low, the signal voltage cannot be matched with the reference voltage. As described above, the reference voltage determines the range of luminance in which A / D conversion can be performed.

In this circuit, the maximum value of the luminance of the image input to the solid-state imaging device indicated by the digital signal is stored, converted into an analog signal, and fed back to the input of the comparator as a reference voltage. Therefore, the control amount does not saturate even when the luminance of the input image is significantly increased and the signal voltage input to the comparator is large. A / D conversion can be performed. If the average value is stored instead of the maximum value, the signal from the pixel which gives the maximum value of the luminance in the image is slightly saturated, but the analog signal having a smaller luminance than the case where the maximum value is used is also used. A / D conversion can be performed accurately.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a signal processing circuit according to an embodiment will be described. In addition, the same reference numerals are used for the same elements or elements having the same functions, and overlapping descriptions are omitted.

The signal processing circuit 2 reads out a signal from the solid-state imaging device 1 such as a CCD or a MOS image sensor and performs A / D conversion on the read-out analog signal. In this example, a MOS is used as the solid-state imaging device 1.
A type image sensor is used.

FIG. 1 is a system configuration diagram of the MOS image sensor 1 and the signal processing circuit 2. The MOS type image sensor 1 includes a plurality of photoelectric conversion elements PD arranged two-dimensionally, and each photoelectric conversion element PD is provided with a switching element FET. The photoelectric conversion element PD in this example is a photodiode, and the switch element FET is a shift register 1SF.
Are sequentially connected for each of the vertical columns.
In other words, each vertical column 12 _1, ... 12 _L of the photodiode P
D is connected to each output terminal OUT by connecting the switch element FET.

More specifically, a plurality of the vertical photodiode rows are arranged adjacent to each other, and the shift register 1S
In response to the signal from F, adjacent vertical photodiode rows are sequentially selected, and the photodiodes PD of the selected photodiode row are connected to the output terminal OUT. This allows
The input image having a two-dimensional spread to the image sensor 1 can be converted into an electric signal and output from the output terminal OUT.

The shift register 1SF is driven by a pulse output from the timing generation circuit 4. The timing generation circuit 4 converts a reference frequency clock signal output from the oscillator 3 such as a crystal oscillator or a multivibrator from the shift register 1SF. , And pulse signals necessary for driving the apparatus.

Photodiode PD, switch element FE
T, the shift register 1SF is provided in the same semiconductor substrate, the signal output electrode pad OUT connected to each photodiode PD is provided at the end of the substrate, and the wiring W
Is connected to the signal processing circuit 2 via the.

The signal processing circuit 2 includes a charge amplifier 30,
A plurality of (five in this example) circuit rows MAIN including the conversion section 50, the comparator 60, and the control section CONT connected in series are provided. The signal processing circuit 2 is formed on a semiconductor substrate, and a signal input electrode pad IN that functions as an input terminal of each circuit row is provided at an end of the semiconductor substrate.

Each photodiode PD and each charge amplifier 30 are connected via a signal output electrode pad OUT, a bonding wire W, and a signal input electrode pad IN. The shorter the length of the bonding wire W,
Since the influence of the parasitic capacitance of the charge amplifier 30 can be suppressed, the sensor and the signal processing circuit are preferably formed on the same semiconductor substrate, but in this example, they are formed on different semiconductor substrates, respectively. It shall be.

The output from each photodiode PD passes through a wiring W, and then passes through a charge amplifier 30, a converter 50, a comparator 6
0 is sequentially input to the control unit CONT. The charge signal output from the photodiode PD is output to an output terminal O
Charge amplifier 3 via UT, wiring W, and input terminal IN
After being input to 0 and being subjected to charge-voltage conversion by the charge amplifier 30, it is input to the conversion unit 50.

The converter 50 converts the input analog signal into a voltage signal V. In this conversion, for example, a charge signal is converted into a voltage signal, but from a different point of view, a current signal is converted into a voltage signal, or an input voltage signal is converted into a different voltage signal. You may. The conversion unit 50 includes a variable parameter (parameter variable unit) 53
(See FIG. 2).

The conversion unit 50 is a voltage conversion circuit with a variable capacitance using the capacitance as the variable parameter.
When the capacitance is controlled by the NT, the level of the signal voltage V fluctuates according to the input charge amount or voltage, and AD
In the conversion period, the control amount by the control unit CONT is output as a charge amount as a digital signal.

This variable parameter constitutes a conversion coefficient,
The input analog signal is converted into a signal voltage V based on a variable parameter. For example, when an input analog signal is represented by a charge amount, the variable parameter is a parallel capacitance (capacitor), and if the capacitance is increased, the signal voltage V across the capacitor under a constant charge amount. Becomes smaller. That is, in this case, the increase amount of the variable parameter indicates the decrease amount of the signal voltage V.
In other words, when the variable parameter is feedback-controlled so that the signal voltage V becomes a constant value, the control amount is proportional to the amplitude of the input analog signal, that is, the charge amount.

To perform such feedback control, the converted signal voltage V and the reference voltage Vref are input to the comparator 60, and the signal voltage V and the reference voltage Vref match based on the output of the comparator 60. In this way, the variable parameter is controlled by the control unit CONT. Therefore, the control unit CONT
Is output as a digital signal proportional to the amplitude of the input analog signal (the luminance of the signal output from each pixel PD of the image sensor 1). As a result, A / D conversion is performed. Become. In other words, in this circuit, the control amount required to make the input signal voltage V equal to the reference voltage Vref is a digitally converted value of the input signal voltage V.

The digital signal of each horizontal circuit row output from each control unit CONT is input to a maximum value or average value storage unit MEM, and the storage unit MEM stores the digital signal in an image for a predetermined period (for one frame). The maximum value or average value of the in-image luminance indicated by the digital signal is stored. The stored digital signal is converted into an analog signal by the D / A converter DA, and is fed back to the non-inverting input terminal of each comparator 60 as the reference voltage Vref.

That is, a digital signal for one frame is input to the storage unit MEM as current data, the maximum value or the average value is stored in the storage unit MEM, and the value corresponding to the stored value is D / D. The analog signal is converted and output as an analog signal.
D, and when the digital signal for the next one frame is read into the storage unit MEM, the reference voltage Vref
Used as When the digital signal for the next one frame is read into the storage unit MEM, the maximum value or the average value at this time is newly stored in the storage unit MEM, and this is used as the above-described current data, and thereafter, the same operation is performed. The process is repeated.

As described above, the signal processing circuit 2 converts the analog signal input from the solid-state imaging device 1 into a signal voltage V based on the variable parameter 53 (see FIG. 2). And the reference voltage Vref are input to a comparator 60, and based on the output of the comparator 60, the variable parameter is controlled so that the signal voltage V and the reference voltage Vref match, and this control amount is converted into a digital signal. In the output signal processing circuit, the maximum value or average value of the luminance of the image input to the solid-state imaging device 1 indicated by the digital signal within a predetermined period (one frame) is stored in the storage unit MEM, and the stored maximum value or average is stored. The value is converted into an analog signal by the D / A converter DA, and is fed back to the input of the comparator 60 as the reference voltage Vref.

An analog signal input from the solid-state imaging device 1 is converted into a signal voltage V, and control is performed so as to change a variable parameter until the signal voltage V input to the comparator 60 matches the reference voltage Vref. Then, the control amount is output as a digital signal. If the set value of the reference voltage Vref increases, the control amount until the above-mentioned matching is performed increases. Therefore, the luminance indicated by the digital signal indicated as the control amount becomes To increase.

Various variables can be considered as the variable parameter. The parameter is a capacitance, and the signal voltage V converts an analog signal input to the converter 50 according to the capacitance as a variable parameter. Generated by Further, the variable parameter can be constituted by a resistor.

If the reference voltage Vref is fixed, the brightness of the input image increases significantly, and if the signal voltage input to the comparator 60 increases, the control amount is saturated and becomes constant. turn into. If the reference voltage Vref is set to be large from the beginning, such saturation can be suppressed. However, when the luminance is low, the signal voltage cannot be matched with the reference voltage Vref. In this manner, the reference voltage Vref determines the range of luminance when performing A / D conversion.

In this circuit, the maximum value of the luminance of the input image indicated by the digital signal to the solid-state imaging device 1 is stored, converted into an analog signal, and fed back to the input of the comparator 60 as the reference voltage Vref. ing. Therefore, even when the luminance of the input image is significantly increased and the signal voltage input to the comparator 60 is increased, the control amount is not saturated, and
If the luminance does not increase, an analog signal having a small luminance can be A / D converted. If the storage unit MEM stores the average value instead of the maximum value, the signal from the pixel that gives the maximum value of the luminance in the image is slightly saturated, but the luminance is lower than when the maximum value is used. Can be accurately A / D converted. That is, the output is automatically adjusted.

The conversion section 50 also functions as a CDS circuit that outputs the input signal while performing correlated double sampling. The digital signal output from the control unit CONT may be a parallel output or a serial output that sequentially switches output lines using a shift register.

Here, the configuration of one of the five circuit rows MAIN will be described in more detail. In addition,
The configuration of other circuit rows is the same as this circuit row. Also,
In the above embodiment, an example in which a circuit row is provided for each of a plurality of photodiode rows has been described. However, the output of each photodiode horizontal row may be sequentially input to one circuit row MAIN.

FIG. 2 shows a sensor 1 and one circuit array MAI.
FIG. 2 is a circuit configuration diagram of N.

The charge amplifier 30 forms an integrating circuit, receives a current signal output from an output terminal OUT, integrates the current signal, and outputs a voltage signal to an output terminal. The charge amplifier 30 includes an operational amplifier 31, a capacitance element 32, and a reset switch element 33. The operational amplifier 31 has a non-inverting input terminal (+) connected to a fixed potential, and inputs a current signal to the inverting input terminal (-). The capacitive element 32 is provided in parallel between the inverting input terminal and the output terminal of the operational amplifier 31, and receives an input current signal,
That is, the charge is stored. The switch element 33 is provided between the inverting input terminal and the output terminal of the operational amplifier 31. When the switch element 33 is open, the switch element 33 causes the capacitive element 32 to accumulate charges.
When closed, the charge accumulation in the capacitor 32 is reset.

The output of the charge amplifier 30 is input to the converter 50. The conversion unit 50 includes a capacitance element 51, an operational amplifier 52, a variable capacitance unit 53, and a reset switch element 5.
4 is provided. The capacitance element 51 is connected to the charge amplifier 30
And the inverting input terminal of the amplifier 52. The non-inverting input terminal of the operational amplifier 52 is connected to a fixed potential, and a voltage signal from the capacitive element 51 is input to the inverting input terminal. The variable capacitance section 53 has a variable capacitance and is controllable. The variable capacitance section 53 is provided between the inverting input terminal and the output terminal of the operational amplifier 52, and stores electric charge in accordance with the input voltage signal. The switch element 54 is provided between the inverting input terminal and the output terminal of the operational amplifier 52. When the switch element 54 is open, the variable capacitor 53 accumulates electric charge. When the switch element 54 is closed, the electric charge accumulation in the variable capacitor 53 is reset. I do. The conversion unit 50 converts the input signal voltage into a variable capacitance unit 53
And outputs an integrated signal as a result of the integration as a signal voltage V.

The comparator 60 inputs the integrated signal voltage output from the converter 50 to an inverting input terminal, and the non-inverting input terminal is set to the reference potential Vref. Vref is compared in magnitude, and a comparison result signal is output as a result of the magnitude comparison.

The capacitance control unit CONT receives the comparison result signal output from the comparator 60, and controls the capacitance of the variable capacitance unit 53 based on the comparison result signal.
Is output, and when it is determined that the value of the integrated signal voltage V and the reference potential Vref match at a predetermined resolution based on the comparison result signal, the digital signal corresponding to the capacitance of the variable capacitance section 53 is output as described above. Is output as the control amount of. Note that a reading unit for removing the offset value of the conversion unit 50 may be provided downstream of the capacitance control unit CONT.

Conversion section 50, comparator 60, capacity control section CO
The signal processing unit 100 is configured with NT as one set. The signal processing unit 100 has a CDS function for removing an offset error and an A / A for converting an analog signal into a digital signal.
It has a D conversion function. The conversion unit 50 that performs these functions will be described in more detail.

FIG. 3 is a circuit diagram of the converter 50.
Since this is the same as that described in the above-described prior art, the amplifier 30 will be described below with reference to FIG.
And the function of the conversion unit 50 will be briefly described.

Here, a circuit configuration having an A / D conversion function having a resolution of 1/2 ⁴ = 1/16 is shown, and this circuit configuration will be described below. The variable capacitance section 53 includes a capacitive element C
1 to C4, switch elements SW11 to SW14 and switch elements SW21 to SW24. Capacitance elements C1, C
2, C3, and C4, and switch elements SW11,
Each of the switches SW12, SW13, and SW14 is connected in series with each other, and provided in parallel between the inverting input terminal and the output terminal of the amplifier 52. Switch element SW21,
Each of SW22, SW23 and SW24 is composed of capacitive elements C1, C1, C3 and C4 and switch elements SW11 and SW4.
12, SW13, and SW14 are provided between each connection point and the ground potential.

Each of switch elements SW11 to SW14 is connected to a capacitance instruction signal C output from capacitance control unit CONT.
Open and close according to the values of C11 to C14. The switch elements SW21 to SW24 open and close according to the values of C21 to C24 of the capacitance instruction signal C output from the capacitance control unit CONT. Capacitance values C1 to C4 of capacitive elements C1 to C4
Satisfies the following relationship: C1 = 2.times.C2 = 4.times.C3 = 8.times.C4 C1 + C2 + C3 + C4 = C0 In a state where no signal is input from the photodiode PD, the charge amplifier 30 is reset by closing the switch element 33 of the charge amplifier 30.
By closing the switch element 54 of the converter 50, the converter 50 is reset. Further, by closing each of the switch elements SW11 to SW14 of the conversion unit 50 and opening each of the switch elements SW21 to SW24,
The capacitance value of the variable capacitance section 53 is set to C0. Then, in this state, by opening the switch element 33 of the charge amplifier 30, the integration operation in the charge amplifier 30 is enabled. At this point, an offset voltage serving as switching noise is generated in the charge amplifier 30 by the action of the parasitic capacitance of the switch element 33.

The switching element 54 is opened with a slight delay ΔTd from the time when the switching element 33 is opened. As a result, the output terminal of the integrating circuit 50 relatively changes the voltage level corresponding to the amount of photocharge generated thereafter, in a form in which the offset level of the charge amplifier 30 is removed. That is, a so-called CDS action occurs.

[0041] When connecting only photodiode vertical column 12 _first switching element FET, the charge accumulated in the photodiode PD is, the charge amplifier 3 becomes a current signal
0, is integrated by the charge amplifier 30, and is input to the converter 50. The voltage signal input to the capacitance element 51 of the conversion unit 50 fluctuates by the output voltage change corresponding to the amount of photocharge in the charge amplifier 30, and the charge corresponding to the voltage fluctuation and the capacitance C0 of the variable capacitance unit 53. Q is the variable capacitance section 5
Flow into 3

Subsequently, the capacitance control unit CONT opens the switch elements SW12 to SW14 of the variable capacitance unit 53 and then closes the switch elements SW22 to SW24. As a result, the capacitance value of the variable capacitance unit 53 becomes C1, and the conversion unit 50
Is V = Q / C1. The integrated signal voltage is input to the comparator 60, and the value is compared with the reference potential Vref.

If V> Vref, the capacity control unit CONT further receives the result of the comparison, and
After opening the third switch element SW22, the switch element SW12 is closed. As a result, the capacitance value of the variable capacitance unit 53 becomes C1 + C2, and the value V of the integration signal output from the conversion unit 50 becomes V = Q / (C1 + C2). This integrated signal voltage is input to the comparator 60, and the value thereof is
ref is compared with the size.

If V <Vref, the capacitance control unit CONT further receives the result of the comparison, opens the switch elements SW11 and SW22 of the variable capacitance unit 53, and then closes the switch elements SW12 and SW21. As a result, the capacitance value of the variable capacitance unit 53 becomes C2, and the conversion unit 5
The value V of the integration signal output from 0 is V = Q / C2. The integrated signal voltage is input to the comparator 60, and the value is compared with the reference potential Vref.

Thereafter, similarly, the conversion unit 50 and the comparator 6
By the feedback loop composed of 0 and the capacitance control unit CONT, the capacitance value of the variable capacitance unit 53 is determined until the capacitance control unit CONT determines that the value V of the integration signal matches the reference potential Vref with a predetermined resolution. The magnitude comparison between the voltage value of the setting and integration signal and the reference potential Vref is repeated. When the capacitance control unit CONT completes the capacitance control for all of the capacitance elements C1 to C4 of the variable capacitance unit 53 in this way, it outputs a digital signal corresponding to the final capacitance value of the variable capacitance unit 53 to the reading unit. In the readout unit, the digital signal output from the capacitance control unit CONT is input as data according to the address of the photodiode row,
The digital data stored at the address of the storage element is output as a light detection signal of the solid-state imaging device according to the present embodiment.

At a time when it is estimated that the photodiode PD in the first row has completely discharged the accumulated charge, the switch element FET connected thereto is opened, and thereafter, connection and disconnection of the vertical photodiode row are repeated in the same manner. Read signals.

The configuration of the variable capacitance section 53 of the conversion section 50 is not limited to the circuit configuration shown in FIG. 3, but may be another conventionally known circuit configuration.

The photoelectric conversion element may be of a type, such as a CCD, in which electric charges are accumulated in a potential well formed on the surface of the semiconductor substrate in response to the incidence of light. Furthermore, a photomultiplier tube can be used as the photoelectric conversion element.

[0049]

As described above, according to the signal processing circuit of the present invention,
The input analog signal can be converted into a digital signal, and the sensitivity can be automatically adjusted.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of a MOS image sensor 1 and a signal processing circuit 2.

FIG. 2 is a circuit configuration diagram of a sensor 1 and one circuit row MAIN.

FIG. 3 is a circuit configuration diagram of a conversion unit 50.

[Explanation of symbols]

Reference numeral 60: comparator, CONT: control unit, Vref: reference voltage.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kazuki Fujita 1126-1, Nomachi, Hamamatsu-shi, Shizuoka Prefecture Inside Hamamatsu Photonics Co., Ltd. (72) Inventor Hiroo Yamamoto 1-126-1, Nomachi, Ichinomachi, Hamamatsu-shi, Shizuoka Prefecture Photonics Hamamatsu Incorporated (72) Inventor Seiichiro Mizuno 1 1126 Nomachi, Hamamatsu-shi, Shizuoka Prefecture F-term within Hamamatsu Photonics Co., Ltd. CY46 GX03 GY01 GY31 HX20 HX21 HX23 HX29

Claims (1)

[Claims] 1. An analog signal input from a solid-state imaging device is converted into a voltage signal based on a variable parameter, the signal voltage and a reference voltage are input to a comparator, and based on an output of the comparator, A signal processing circuit that controls the variable parameter so that the signal voltage matches the reference voltage and outputs the control amount as a digital signal, wherein an input image to the solid-state imaging device indicated by the digital signal within a predetermined period A signal processing circuit for storing a maximum value or an average value of the luminance of the signals, converting the stored maximum value or the average value into an analog signal, and feeding the analog signal back to the input of the comparator as the reference voltage.