JPH10257389A - Amplifier-type solid-state image-pickup unit and operating method therefor - Google Patents

Amplifier-type solid-state image-pickup unit and operating method therefor

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Publication number
JPH10257389A
JPH10257389A JP9056307A JP5630797A JPH10257389A JP H10257389 A JPH10257389 A JP H10257389A JP 9056307 A JP9056307 A JP 9056307A JP 5630797 A JP5630797 A JP 5630797A JP H10257389 A JPH10257389 A JP H10257389A
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JP
Japan
Prior art keywords
means
vertical
vertical signal
noise
horizontal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
JP9056307A
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Japanese (ja)
Inventor
Masayuki Matsunaga
誠之 松長
Original Assignee
Toshiba Corp
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, 株式会社東芝 filed Critical Toshiba Corp
Priority to JP9056307A priority Critical patent/JPH10257389A/en
Priority claimed from US09/038,039 external-priority patent/US6037577A/en
Publication of JPH10257389A publication Critical patent/JPH10257389A/en
Abandoned legal-status Critical Current

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Abstract

(57) [Problem] To provide a charge adding circuit in front of a noise suppression circuit so that sensitivity is not inferior to a CCD imaging device. The unit cells arranged two-dimensionally include horizontal address lines 7 1 , 7 2 ,... And charge transfer control lines 8 1 , 8.
2, ... and the reset line 9 1, 9 2, connected ... to the vertical shift register 6 through the. At one end of the vertical signal lines 10 1 , 10 2 ,... Connected to the unit cells, load transistors 13 1 , 13 2 ,. The other ends of the vertical signal lines 10 1 , 10 2 ,.
1, 30 2, ..., and the noise suppression circuit 14 1, 14 2, the horizontal selection through ... transistor 15 1, 15 2, ... it is connected. The horizontal selection transistors 15 1 , 15 2 ,.
Are selected by a selection pulse supplied from the horizontal shift register 16 and are connected to the horizontal signal line 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an imaging device for converting incident light into an electric signal, and more particularly to an amplification type solid-state imaging device and an operation method thereof.

[0002]

2. Description of the Related Art FIG. 10 is an example of a circuit diagram of a solid-state imaging device called a general amplification type MOS sensor. FIG.
, A photodiode 1 11 for performing photoelectric conversion,
1 12, ..., 1 21, 1 22, ... and the photodiode 1 11, 1 12, ..., 1 21, 1 22, amplifying transistor 2 11, 2 12 for amplifying a ... signal, ..., 2 21, 2 22, ... and the vertical selecting reading line signal Sensawa transistor 3 11,
3 12, ..., 3 21, 3 22, ... and the reset transistor 4 11, 4 12 to reset the signal charge, ..., 4 21, 4 22, ...
When, the photodiode 1 11, 1 12, ..., 1 21,
1 22, ... amplifying transistor 2 11, 2 12 the charge of, ..., 2
21, 2 22, ... the signal charge transfer transistor 5 11, 5 12 to be transferred to the gate region of, ..., 5 21, 5 22, the unit cell composed of ..., are arranged two-dimensionally. FIG. 10 shows an example in which 2 × 2 unit cells are arranged, but actually more unit cells are arranged.

[0005] From the vertical shift register 6, horizontal address lines 7 1 , 7 2 ,...
1, 8 2, ..., reset line 9 1, 9 2, ... is the wiring is connected to each unit cell, respectively described above. In other words, the horizontal address line 7 1, 7 2, ... vertical Sensawa transistor 3 11, 3 12, ..., 3 21, 3 22, is connected to the ... gate is used to determine the reading line signals. The charge transfer control lines 8 1 , 8 2 ,... Are signal charge transfer transistors 5 11 ,
5 12, ..., 5 21, 5 22, and is connected to the ... gate of.
The reset line 9 1, 9 2, ..., the reset transistor 4 11, 4 12, ..., 4 21, 4 22, are connected to the ... gate of.

The amplifying transistors 2 11 , 2 12 ,.
The sources of 21 , 22 ,... Are vertical signal lines 10 1 , 10 2 ,.
Is connected to These vertical signal lines 10 1 , 10 2 ,
Are connected to the common gate line 11 and the common source line 12 at one end of the load transistors 13 1 , 13 2 ,.
Is provided. The vertical signal lines 10 1 , 1
0 2, the ... the other end of the noise suppression circuit 14 1, 14 2, ...
, Are connected to the horizontal selection transistors 15 1 , 15 2 ,. The horizontal selection transistors 15 1 and 15
2, ... are those selected by the selection pulse supplied from the horizontal shift register 16 are connected to the horizontal signal line 17.

The noise suppression circuits 14 1 , 14 2 ,...
This is a circuit for determining the difference between when there is a signal on the vertical signal lines 10 1 , 10 2 ,. FIG. 11 is a circuit diagram showing an example of the configuration of the noise suppression circuit.

In FIG. 1, a vertical signal line 10 is connected to a gate of a slice transistor 19. The source of the slice transistor 19 includes a slice capacitor 20 and a slice capacitor reset transistor 2.
1, and a drain is connected to a slice charge storage capacitor 21 and a slice charge storage capacitor reset transistor 22 as shown. In addition, 2 in the figure
Reference numerals 4, 25, 26, 27, and 28 denote a slice capacitor reset transistor common source line, a slice capacitor reset transistor common gate, a slice capacitor control line, a DC line, and a slice charge storage capacitor reset transistor common gate, respectively.

FIG. 12 is a timing chart for explaining the operation of this conventional device. The BL pulse is used to read the signal of the photodiode 1 during a period I during which the noise suppression circuit 14 suppresses noise and a period during which the signal is read out to the horizontal signal line 17.
II is shown.

First, the period I will be described. Address pulse S to the horizontal address line 7 1 is a high level
1 when 1 is applied, are turned on only select transistor of this line, amplifier transistor 2 11, 2 12 and the load transistor 13 1, 13 2 in the source follower circuit of this row is configured, the amplifier transistor 2 11, 2 12 A voltage substantially equal to the gate voltage appears on the vertical signal lines 10 1 and 10 2 .

[0009] Then, the reset pulse S2 1 is generated in the reset line 81, to the gate of the amplifying transistor 2 11 by the reset transistor 4 1 is turned on, the voltage of the absence of signal is generated. At this time, the vertical signal line 1
At 0 1 and 10 2 , only a noise voltage when there is no signal is generated. That is, only noise is applied to the gate of the slice transistor 19.

The slice capacitor reset pulse S is applied to the slice capacitor reset transistor common gate 25.
3 1 is applied, the slice capacitor 20 is preset.

[0011] Next, the first slice BALS S4 1 is applied to the slice capacitor control line 26 connected to the slice capacitor 20, a part of the charge accumulated in the slice capacitor 20 through the gate-channel slices transistor 19 Transferred to drain. The charge corresponding to the noise voltage applied to the gate of the slice transistor 19 remains in the slice capacitor 20.

The charge transferred from the drain of the slice transistor 19 to the slice charge storage capacitor 22 also has a quantity related to the stale charge, which is connected to the slice charge storage capacitor reset transistor common gate 28 by the first gate. slice charge storage capacitor reset pulse S5 1 is applied, the slice charge storage capacitor is reset.

Furthermore, in order to maintain the state of application of the noise accurately, the second slice pulse S6 1, second slice charge storage capacitor reset Bals S7 1 is applied. Subsequently, the signal charge transfer pulses to the charge transfer control line 9 1 S8 1
There is applied, the signal charge transfer transistor 5 11 is turned on, the signal charge is transferred to the gate region of the amplifying transistor 2 11. A signal voltage appears on the vertical signal lines 10 1 and 10 2 , and the signal voltage is applied to the gate of the slice transistor 19.

[0014] Next, a third slice pulse S9 1 is applied, part of the charge accumulated in the slice capacitor 20 is transferred as the slice charge storage capacitor 22 to the gate channel slices transistor 19. Since a charge amount corresponding to the noise is stored in the slice capacitor 20 and a signal voltage on which the noise is superimposed is applied to the gate of the slice transistor 19, the noise component is stored in the slice charge storage capacitor 22. Only the charge corresponding to the subtracted signal is transferred. Only the signal charge without noise is stored in the slice charge storage capacitor 22.

Next, in period II, the horizontal shift register 1
6 sequentially generated horizontal selection pulses S10 1 , S10
2 is applied to the gates of the horizontal selection transistors 15 1 and 15 2 , and the signal charge of the slice charge storage capacitor 22 is read out to the horizontal signal line 17. Read signals S11 11 and S11
Numeral 11 12 corresponds to the signals of the photodiodes 11 1 and 1 12 , respectively. The signals in the subsequent rows can be similarly read.

[0016]

By the way, as described above, the MOS type image pickup device has a problem that the type having an amplification transistor in a unit pixel has a lower sensitivity than the image pickup device having a CCD. there were. The reason is that if the performance of the amplification transistor present in the unit pixel of the amplification type MOS imaging device and the performance of the transistor of the output amplifier existing in the final stage of the CCD imaging device are the same, the manufacturing process is almost the same. Because they will be the same.

The CCD image pickup device has almost no noise, and it can be considered that the noise is generated only from the output amplifier. On the other hand, in the amplification type MOS imaging device, even after amplification in a unit pixel, some noise passes through the transistor before being output to an output terminal, so that new noise is superimposed here. Therefore, the present invention
It is an object of the present invention to provide an amplifying solid-state imaging device whose sensitivity is not inferior to that of a CCD imaging device and an operation method thereof.

[0018]

That is, according to the present invention, noise is amplified by performing amplification a plurality of times in a unit pixel of an amplifying MOS imaging device, integrating the amplified charge a plurality of times, and entering a noise suppression circuit. The effect of noise superimposed after the suppression circuit can be reduced. Alternatively, the charge amplified in the unit pixel is transferred to a small capacitance without being amplified in the charge region,
The signal is amplified only in the voltage domain and input to the noise suppression circuit.
However, this requires that the noise suppression circuit be of a gate input type.

With this configuration, the amplification type M
The noise of the OS image sensor is almost determined by the noise of the amplification transistor of the unit pixel. Therefore, CC
The sensitivity becomes higher than that of the CCD by the same sensitivity as that of the D imaging device or by the amplification factor just before the amplifier circuit.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of an amplification type solid-state imaging device according to an embodiment of the present invention. In the embodiments described below, the same portions as those in the above-described conventional example are denoted by the same reference numerals, and detailed description will be omitted.

[0021] In FIG. 1, the photodiode 1 11, 1 12 for photoelectric conversion, ..., 1 21, 1 22, ... and the amplifier transistor 2 11, 2 12, ..., 2 21, 2 22, ... and vertical Sensawa transistor 3 11, 3 12, ..., 3 21, 3 22, ... and the reset transistor 4 11, 4 12, ..., 4 21, 4 22, ... and the signal charge transfer transistors 5 11, 5 12 ,…, 5 21 , 5 22 ,
Are arranged two-dimensionally. FIG. 1 shows an example in which 2 × 2 unit cells are arranged, but actually more unit cells are arranged.

From the vertical shift register 6, horizontal address lines 7 1 , 7 2 ,...
1, 8 2, ..., reset line 9 1, 9 2, ... is the wiring is connected to each unit cell, respectively described above.

Are connected to one end of each of the vertical signal lines 10 1 , 10 2 ,...
Are connected to the load transistors 13 1 , 13 2 ,. On the other hand, the vertical signal lines 10 1 , 10 2 ,
, Are connected to horizontal selection transistors 15 1 , 15 2 ,... Via charge addition circuits 30 1 , 30 2 , and noise suppression circuits 14 1 , 14 2 ,. The horizontal selection transistors 15 1 , 15 2 ,... Are selected by a selection pulse supplied from a horizontal shift register 16 and are connected to a horizontal signal line 17.

FIG. 2 shows the charge adding circuits 30 1 , 30
2 is a circuit diagram showing an example of the configuration of... 2, the charge adding circuit 30 includes an amplified charge transfer transistor 31 having a source and a drain connected to the vertical signal line 10;
It comprises a charge adding capacitor 32 and a charge adding capacitor reset transistor 33 connected to the drain of the amplified charge transfer transistor 31. 3
4 is a common gate of the amplified charge transfer transistor, 35 is DC
The line 36 is a common gate of the charge addition capacitor reset transistor.

In the solid-state imaging device having such a configuration,
An example of the operation will be described with reference to the timing chart of FIG. The same signals as those in the above-described conventional example are denoted by the same reference numerals, and description thereof will be omitted.

First, since the load transistor 13 is pulse-driven, a pulse voltage is input to the load transistor common gate 11. The vertical signal lines 10 1 , 10 2 ,... Are reset so that the load transistor 13 is turned on to have substantially the same voltage as the load transistor common source 12. Thereafter, when the load transistor 13 is turned off,
The electric charge is discharged through the gate channel of the amplification transistor 2 and the vertical selection transistor 3 in the addressed row, and the potential of the vertical signal lines 10 1 , 10 2 ,... Is almost the same as the potential of the gate channel of the amplification transistor 2. become.

The charge accumulated in the capacitance of the vertical signal line 10 can be transferred to the charge adding capacitor 32 when the amplified charge transfer transistor 31 is turned on. FIG. 3 shows an example in which such a transfer operation is performed three times.

[0028] First, in order to charge adding capacitor 32 is reset, the first charge adding capacitor reset pulse S16 1 is applied to the charge adding capacitor reset transistor common gate 36. When only noise is applied to the amplification transistor 2, the first vertical signal line reset pulse S1 at the time of noise is applied to the load transistor common gate 11.
2 11 , the first gate of the amplified charge transfer transistor common gate 34
Noise during amplification charge transfer pulses 14 11 is applied respectively, amplified Zatsumukashi charges are transferred to the charge adding capacitor 32.

Subsequently, the second and third noise signal line reset pulses 12 12 and 12 13 , and the second and third noise amplified charge transfer pulses 14 12 and 14 13 are applied, and a total of three noise noises are applied. The charges are accumulated in the charge summing capacitor 32. The noise output added by the charge addition circuit 30 at this time is taken into the noise suppression circuit 14. The operation of the noise suppression circuit 14 is the same as the timing chart shown in FIG.

Next, the signal charge transfer transistor 5 is turned on, and the signal of the photodiode 1 is transferred to the gate of the amplification transistor 2. Then, the second charge adding capacitor reset pulse S17 1 is applied to the charge adding capacitor reset transistor common gate 36.

Thereafter, the load transistor common gate 11
First, second, third signal during the vertical signal line reset BALS S13 11, S13 12, S13 13 is first amplification charge transfer transistor common gate 29, a second, a third signal upon amplification charge transfer pulses to S15 11 , 15 12 and 15 13 are applied,
A total of three signal charges are accumulated in the charge adding capacitor 32. The added noise output of the charge addition circuit 30 at this time is taken into the noise suppression circuit 14.

The operation of the noise suppression circuit 14 is the same as the timing chart shown in FIG. The subsequent operation is substantially the same as the timing chart shown in FIG.

A method of making the number of additions other than three can be easily considered. For example, when the number of additions increases, the charge addition capacitor 32 saturates. Therefore, the capacitance value is set to be larger than the capacitance value of the vertical signal line 10. In order for the charge added to the charge adding capacitor 32 to be input as a voltage to the noise suppression circuit 14, the noise suppression circuit 14 needs to be a gate input. This is not suitable, for example, as disclosed in Japanese Patent Application Laid-Open No. 64-2354, which requires a large amount of charge for charging a clamp capacitor.

FIG. 4 shows a gate input type noise suppression circuit 14.
FIG. 2 is a circuit diagram showing an example of a configuration of A. In FIG.
The gate input type noise suppression circuit 14A includes a gate input circuit composed of a noise suppression amplification transistor 39 and a noise suppression load transistor 40, a clamp capacitor 41, a clamp transistor 42, and a sample poled transistor 4.
3. It is provided at the preceding stage of the correlated double sampling type noise suppression circuit comprising the sampled poled capacitor 44.

In the noise suppression circuit 14A having the structure shown in FIG. 4, the charge addition capacitor 32 is connected to the vertical signal line 10 by the variation of the threshold voltage of the amplified charge transfer transistor 31.
May vary in each column. In order to suppress such variations, the charge adding circuit 30 can be modified and configured as described below.

For example, as shown in FIG. 5, the charge adding circuit 30A includes an amplified charge transfer transistor gate drive capacitor 46 between the gate of the amplified charge transfer transistor 31 and the amplified charge transfer transistor common gate 34, and an amplified charge transfer The configuration is such that a feedback transistor 47 is connected between the gate and the drain of the transistor 31. Reference numeral 48 denotes a common gate of the feedback transistor. As a result, it is possible to suppress the variation in the electric charge in each column.

FIG. 6 shows an example of a circuit for separately correcting the variation in the threshold value and adding the charges. As shown in FIG. 6, the charge addition circuit 30B includes an amplified charge transfer transistor 31, a charge addition capacitor 32, a charge addition capacitor reset transistor 33, and a feedback transistor 47. The second amplified charge transfer transistor 31 ′ and the second charge addition capacitor 3 are connected to the drain of the amplified charge transfer transistor 31.
2 'is connected. Reference numeral 34 'denotes a common gate of the amplified charge transfer transistor.

FIG. 7 is a circuit diagram showing still another example of the configuration of the charge adding circuit. As shown in FIG. 7, the charge adding circuit 30C includes the charge adding circuits 30A and 30A shown in FIG.
0B. That is, the configuration is such that the second amplified charge transfer transistor 31 'and the second charge addition capacitor 32' are connected to the drain of the amplified charge transfer transistor 31 of the charge addition circuit 30A.

In general, when an image sensor is used for a camera,
In order to make the sensitivity variable, an external amplifier circuit for amplifying the output signal has a variable amplification factor. In the above-described charge addition circuit, by changing the number of additions,
The gain can be changed without using an external amplifier circuit at the output of the image sensor. In order to capture both low and high brightness areas, the system has an automatic sensitivity adjustment function that automatically increases the amplification factor in low brightness areas. This is made possible by configuration.

In the above-described charge addition circuit, the voltage is amplified by adding the signal charges. However, the voltage can be amplified by a single transfer operation without performing the addition. In this case, it is necessary to set the capacitance value of the charge adding capacitor 32 to be smaller than that of the vertical signal line 10.

FIG. 8 is a circuit diagram showing a configuration of a charge adding circuit for amplifying a voltage in a single transfer operation of such signal charges. In FIG. 8, a charge addition circuit 30D is provided at a connection point between the amplified charge transfer transistor 31 and the charge addition capacitor reset transistor 33 to select a first to third charge addition capacitors 32a to 32c. The sources of the transistors 49a to 49c
They are connected in parallel. The charge addition capacitors 32a to 32c for storing amplified charges are provided at the drains of the charge addition capacitor selection transistors 49a to 49c.
However, the gates are connected to number selection lines 50a to 50c for selecting the transistors 49a to 49c.

As described above, the charge adding circuit 30D is provided with a plurality of charge adding capacitors for accumulating amplified charges, and three charge adding capacitors in FIG. Then, in order to make the amplification rate variable, the charge addition capacitor selection transistor 49a
By selecting the switches of .about.49c, the number of capacitors in which electric charges are accumulated in the electric charge adding capacitor is selected. That is,
The amplification factor of the voltage changes according to the number of the selected charge adding capacitors.

As a method of amplifying a voltage by a single transfer operation of a signal charge, a configuration using a variable capacitor whose capacitance value is changed by a bias of a diode or the like can be considered. FIG.
Is a circuit diagram showing a configuration example of such a charge addition circuit. A charge addition circuit 30E is provided at a connection point between the amplified charge transfer transistor 31 and the charge addition capacitor reset transistor 33 as shown in FIG. Are connected. Incidentally, 52 is a diode bias line.

In the charge adding path 30E shown in FIG. 9, the voltage is changed by controlling the diode bias line 52, thereby changing the capacitance of the diode 51 to change the amplification factor.

As described above, without adding the signal charges, 1
The voltage can be amplified by one transfer operation. Further, in addition to the above-described embodiment, the present invention includes the following invention.

(1) An image pickup area in which photosensitive cells each comprising a photoelectric conversion means, a signal charge accumulation means, a signal charge discharge means, a row selection means and an amplification means are two-dimensionally arranged on a semiconductor substrate, and a row is arranged in this area. Multiple vertical selection lines arranged in directions,
Vertical selection means for driving the vertical selection lines, a plurality of vertical signal lines arranged in the column direction for reading the output of the amplifying means, and a plurality of vertical signal line driving assists provided for the plurality of vertical signal lines. Means, noise suppression means provided at the end of the vertical signal line and taking in and subtracting noise and signal appearing with a time difference in the vertical signal line, horizontal selection lines arranged in the column direction, and the horizontal selection line and the noise In an amplifying solid-state imaging device including a horizontal readout unit that relays the output of the suppression unit and a horizontal selection unit that drives the horizontal readout unit, the amplifying-type solid-state imaging device includes the above described arrangement between the vertical signal line and the noise suppression unit. An amplification-type solid-state imaging device comprising charge addition means for adding signal charges on a vertical signal line.

(2) The charge adding means comprises a vertical signal line charge transfer means for transferring charges to the vertical signal line, and an added charge storage capacitor for storing charges transferred by the vertical signal line charge transfer means. The amplification type solid-state imaging device according to the above (1), wherein

(3) The amplification type solid-state imaging device according to the above (2), further comprising an additional charge discharging means for discharging the charge accumulated in the additional charge storage capacitor. (4) The vertical signal line charge transfer means includes a MOS transistor, and a feedback MOS transistor connected between a gate electrode of the MOS transistor and a drain to which the added charge storage capacitor is connected. The amplification type solid-state imaging device according to the above (3), which is characterized in that:

(5) The amplification type solid-state imaging device according to any one of (1) to (4), wherein the electric capacitance value of the added charge storage capacitance is larger than the electric capacitance value of the vertical signal line. (6) The noise suppressing means includes at least one MOS
The amplification type solid-state imaging device according to any one of (1) to (5), further including a transistor, wherein an output of the charge adding means is input to a gate of the MOS transistor.

(7) Photosensitive cells comprising photoelectric conversion means, signal charge accumulating means, signal charge discharging means, row selecting means and amplifying means are arranged on a semiconductor substrate in a row direction of an imaging region in which two-dimensional arrangement is made. A plurality of vertical selection lines are driven by vertical selection means, the output of the amplification means is read out by a plurality of vertical signal lines arranged in the column direction, and the vertical signal is read by noise suppression means provided at an end of the vertical signal line. The noise and signal appearing in the line with a time difference are taken in and subtracted, the horizontal selection line arranged in the column direction of the imaging area and the output of the noise suppression unit are relayed by the horizontal reading unit, and the horizontal reading unit is driven by the horizontal selection unit In the method of operating an amplification type solid-state imaging device, a first step of performing a plurality of amplification operations on one signal stored in the signal charge storage means, and the vertical step is performed by the first step. Multiple times for signal lines A second step of subtracting the signal and noise obtained by adding the generated amplified signal and amplified noise a plurality of times by the noise suppressing means.

(8) The method according to (7), wherein the second step changes the sensitivity by changing the number of additions. (9) The operation method of the amplification type solid-state imaging device according to (8), wherein the second step performs sensitivity adjustment by making the number of additions variable according to the amount of incident light.

(10) Photosensitive cells comprising photoelectric conversion means, signal charge accumulating means, signal charge discharging means, row selecting means and amplifying means are arranged on a semiconductor substrate in a row direction of an imaging region in which the photosensitive cells are two-dimensionally arranged. The plurality of vertical selection lines are driven by vertical selection means, the output of the amplifying means is read out by a plurality of vertical signal lines arranged in the column direction, and the signals are read out by noise suppression means provided at the ends of the plurality of vertical signal lines. A noise and a signal appearing in the vertical signal line with a time difference are taken in and subtracted, and a MOS transistor is provided between the vertical signal line and the noise suppressing means. A gate electrode of the MOS transistor is connected to a drain to which the integrated charge storage capacitor is connected. And a charge integration means comprising a feedback MOS transistor and an integrated charge storage capacitor, and a horizontal selection line arranged in the column direction of the imaging area and the output of the noise suppression means are relayed by a horizontal reading means. A first step of applying a reference voltage to the vertical signal line in the operation method of the amplification type solid-state imaging device in which the horizontal readout means is driven by the horizontal selection means;
When the reference voltage is applied to the vertical signal line, the feedback MO
A second step of driving the S transistor;
A third step of performing a plurality of amplifying operations on one signal accumulated in the signal charge accumulating means after driving the S transistor; and generating a plurality of times on the vertical signal line by the third step. And a fourth step of driving the feedback transistor to subtract the added signal and noise by the noise suppressing means when adding the amplified signal and amplified noise a plurality of times. An operation method of the amplification type solid-state imaging device, which is characterized by the following.

(11) An imaging area in which photosensitive cells each composed of a photoelectric conversion means, a signal charge storage means, a signal charge discharging means, a row selection means, and an amplification means are two-dimensionally arranged on a semiconductor substrate. A plurality of vertical selection lines arranged in a row direction; vertical selection means for driving the vertical selection lines; a plurality of vertical signal lines arranged in a column direction for reading out the output of the amplification means; A plurality of vertical signal line driving auxiliary means provided on the vertical signal line, noise suppressing means provided at an end of the vertical signal line, taking in noise and a signal appearing with a time difference in the vertical signal line and subtracting the noise, An amplifying solid-state imaging device comprising: a horizontal signal line arranged; a horizontal read line for relaying the output of the horizontal select line and the noise suppressing unit; and a horizontal select unit for driving the horizontal read unit. ,
An amplifying solid-state imaging device comprising: a voltage amplifying means for amplifying a signal voltage on the vertical signal line between the double direct signal line and the noise suppressing means.

(12) The voltage amplifying means comprises a vertical signal line charge transferring means for transferring charges to the vertical signal line, and a voltage amplified charge storage capacitor for storing the charges transferred by the vertical signal line charge transferring means. (1)
The solid-state imaging device according to 1).

(13) The amplification type solid-state imaging device according to (12), wherein the capacitance value of the voltage-amplified charge storage capacitor is smaller than the capacitance value of the vertical signal line. (14) The amplification-type solid-state imaging device according to (11), further including a voltage-amplified charge discharging unit configured to discharge the charge stored in the voltage-amplified charge storage capacitor.

(15) The vertical signal line charge transfer means includes a MOS transistor and a feedback MOS transistor connected between the gate electrode of the MOS transistor and the drain to which the voltage-amplified charge storage capacitor is connected. The amplification-type solid-state imaging device according to the above (11), wherein:

(16) The noise suppressing means is configured to include at least one MOS transistor, and an output of the voltage amplifying means is input to a gate of the MOS transistor. Or (1
An amplification type solid-state imaging device according to 5).

(17) The voltage-amplified charge storage capacity is
The amplifying solid-state imaging device according to (12), wherein the capacitance value is variable by an external signal input from outside.

(18) The voltage-amplified charge storage capacity is
The amplification type solid-state imaging device according to the above (17), wherein the amplification type solid-state imaging device is laterally formed by a variable capacitance transistor and a plurality of divided capacitors.

(19) Photosensitive cells comprising photoelectric conversion means, signal charge storage means, signal charge discharge means, row selection means, and amplification means are arranged on a semiconductor substrate in the row direction of an imaging area in which two-dimensional arrangement is made. A plurality of vertical selection lines are driven by vertical selection means, the output of the amplification means is read out by a plurality of vertical signal lines arranged in the column direction, and a plurality of vertical signal line driving assists provided for the plurality of vertical signal lines are provided. Means and noise suppression means provided at the end of the vertical signal line, take in and subtract noise and signals appearing on the vertical signal line with a time difference, and provide a MOS transistor between the vertical signal line and the noise suppression means. A charge integrating means comprising a feedback MOS transistor and a voltage amplification storage capacitor is connected between the gate electrode of the transistor and the drain connected to the voltage amplification storage capacitor, and the water is arranged in the column direction of the imaging region. In a method of operating an amplification type solid-state imaging device in which a horizontal selection line and an output of a noise suppression unit are relayed by a horizontal reading unit and the horizontal reading unit is driven by the horizontal selection unit, a reference voltage is applied to the vertical signal line. A first step;
When the reference voltage is applied to the vertical signal line, the feedback MO
A second step of driving the S transistor;
When the amplified signal and the amplified noise are transferred to the voltage amplification storage capacitor via the MOS transistor after driving the S transistor, the voltage amplified signal and noise are suppressed without driving the feedback MOS transistor. And a third step of performing an operation of subtracting by means.

(20) Photosensitive cells comprising photoelectric conversion means, signal charge storage means, signal charge discharge means, row selection means, and amplification means are arranged on a semiconductor substrate in a row direction of an imaging region in which two-dimensional arrangement is made. A plurality of vertical selection lines are driven by vertical selection means, the output of the amplification means is read out by a plurality of vertical signal lines arranged in the column direction, and a plurality of vertical signal line driving assists provided for the plurality of vertical signal lines are provided. Means and noise suppression means provided at the end of the vertical signal line, take in and subtract noise and signal appearing in the vertical signal line with a time difference, and transfer between the vertical signal line and the noise suppression means between the vertical signal line charge transfer means and the outside. A charge integration means comprising a variable voltage amplification and storage capacity capable of controlling a variable electric capacitance value, and a horizontal selection line arranged in the column direction of the imaging region and an output of the noise suppression means are relayed by a horizontal reading means; Horizontal reading In the method of operating the amplification type solid-state imaging device in which the driving means is driven by the horizontal selection means, a step of externally providing a variable capacitance signal, and a step of controlling the sensitivity by changing the electric capacitance value of the voltage amplification storage capacitor. An operation method of an amplification type solid-state imaging device, comprising:

(21) The operation method of the amplification type solid-state imaging device according to the above (20), wherein the sensitivity is adjusted by changing the electric capacitance value according to the amount of incident light.

[0063]

As described above, according to the present invention, CC
It is possible to provide an amplification type solid-state imaging device whose sensitivity is not inferior to that of a D imaging device and an operation method thereof.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating an example of a configuration of a charge adding circuit in FIG. 1;

FIG. 3 is a timing chart illustrating an operation of the solid-state imaging device in FIG. 1;

FIG. 4 is a circuit diagram showing an example of a configuration of a gate input type noise suppression circuit.

FIG. 5 is a circuit diagram showing another configuration example of the charge adding circuit of FIG. 1;

FIG. 6 is a diagram illustrating an example of a charge adding circuit that separately performs correction of threshold variation and addition of charges.

FIG. 7 is a circuit diagram showing still another configuration example of the charge addition circuit of FIG. 1;

FIG. 8 is a circuit diagram illustrating a configuration of a charge addition circuit that amplifies a voltage by a single transfer operation of a signal charge.

FIG. 9 is a circuit diagram showing another configuration of a charge adding circuit that amplifies a voltage in one transfer operation of a signal charge.

FIG. 10 is an example of a circuit diagram of a solid-state imaging device called a general amplification type MOS sensor.

11 is a circuit diagram illustrating an example of a configuration of the noise suppression circuit of FIG.

FIG. 12 is a timing chart illustrating the operation of the solid-state imaging device in FIG. 11;

[Explanation of symbols]

1 11, 1 12, ..., 1 21, 1 22, ... photodiode, 2 11, 2 12, ..., 2 21, 2 22, ... amplification transistor 3, 11, 3 12, ..., 3 21, 3 22, ... vertical selection transistors, 4 11, 4 12, ..., 4 21, 4 22, ... reset transistor, 5 11, 5 12, ..., 5 21, 5 22, ... the signal charge transfer transistor, 6 vertical shift register, 7 7 1, 7 2, ... horizontal address lines, 8 1, 8 2, ... charge transfer control line, 9 1, 9 2, ... reset line, 10, 10 1, 10 2, ... vertical signal line, 11 common gate line, 12 common source wiring, 13 1 , 13 2 , ... load transistor, 14, 14 A, 14 1 , 14 2 , ... noise suppression circuit, 15 1 , 15 2 , ... horizontal selection transistor, 16 horizontal shift register, 17 horizontal signal line , 30, 30A, 30B, 30 C, 30D, 30E, 30
1 , 30 2 , ... charge addition circuit, 31 amplified charge transfer transistor, 32 charge addition capacitor, 33 charge addition transistor reset transistor, 34 amplified charge transfer transistor common gate, 35 DC line, 36 charge addition capacitor reset transistor common gate, 39 Noise suppression amplification transistor, 40 noise suppression load transistor, 41 clamp capacitor, 42 clamp transistor, 43 sample hold transistor, 44 sample hold capacitor, 46 amplification charge transfer transistor gate drive capacitor, 47 feedback transistor, 48 feedback transistor common gate.

Claims (6)

[Claims]
1. An imaging area in which photosensitive cells each comprising a photoelectric conversion means, a signal charge storage means, a signal charge discharge means, a row selection means, and an amplification means are two-dimensionally arranged on a semiconductor substrate, and a row direction is set in this area. A plurality of vertical selection lines, a plurality of vertical signal lines arranged in a column direction for reading the output of the vertical selection means for driving the vertical selection lines and the output of the amplification means, and the plurality of vertical signal lines. A plurality of vertical signal line driving auxiliary means provided in the vertical signal line, a noise suppressing means provided at an end of the vertical signal line and taking in noise and a signal appearing with a time difference in the vertical signal line, and a horizontal arrangement arranged in the column direction. In an amplification type solid-state imaging device comprising a selection line, horizontal reading means for relaying the output of the horizontal selection line and the noise suppressing means, and horizontal selection means for driving the horizontal reading means, the vertical signal Line and the noise suppression means Amplifying solid-state imaging device characterized by comprising a charge adding means for adding the signal charges of the vertical signal line between.
2. A plurality of photosensitive cells each comprising a photoelectric conversion means, a signal charge storage means, a signal charge discharge means, a row selection means, and an amplification means arranged on a semiconductor substrate in a row direction of an image pickup area arranged two-dimensionally. Drive the vertical selection line of the vertical selection means,
The output of the amplifying means is read out by a plurality of vertical signal lines arranged in the column direction, and noise and signals appearing on the vertical signal lines with a time difference are taken and subtracted by noise suppressing means provided at the end of the vertical signal line, In a method for operating an amplification type solid-state imaging device, a horizontal selection line arranged in the column direction of the imaging region and an output of the noise suppression unit are relayed by a horizontal reading unit, and the horizontal reading unit is driven by the horizontal selection unit. A first step of performing a plurality of amplifying operations on one signal accumulated in the signal charge accumulating means; an amplified signal and an amplified noise generated a plurality of times on the vertical signal line by the first step; And a second step of subtracting a signal and noise obtained by adding the above two or more times by the noise suppressing means.
3. A plurality of photosensitive cells each comprising a photoelectric conversion means, a signal charge storage means, a signal charge discharge means, a row selection means, and an amplification means arranged on a semiconductor substrate in a row direction of an imaging region in which the photosensitive cells are two-dimensionally arranged. Drive the vertical selection line of the vertical selection means,
The output of the amplifying means is read out by a plurality of vertical signal lines arranged in the column direction, and noise and signals appearing on the vertical signal lines with a time difference are taken in by the noise suppressing means provided at the ends of the plurality of vertical signal lines. In addition, a MOS transistor is provided between the vertical signal line and the noise suppressing means, and a charge integration device including a feedback MOS transistor and an integrated charge storage capacitor is provided between a gate electrode of the MOS transistor and a drain to which the integrated charge storage capacitor is connected. Means, an output of the noise suppression means and a horizontal selection line arranged in the column direction of the imaging area are relayed by a horizontal reading means, and the operation of the amplification type solid-state imaging device which drives the horizontal reading means by the horizontal selection means. In the method, a first step of applying a reference voltage to the vertical signal line;
A second step of driving the S-transistor; and a third step of driving the feedback MOS transistor and performing a plurality of amplification operations on one signal stored in the signal charge storage means. When the amplified signal and the amplified noise generated a plurality of times in the vertical signal line in the third step are added a plurality of times, the signal and the noise added by driving the feedback transistor are subtracted by the noise suppressing means. A method of operating the amplification type solid-state imaging device, comprising: a fourth step of performing an operation.
4. An imaging area in which photosensitive cells each comprising a photoelectric conversion means, a signal charge storage means, a signal charge discharge means, a row selection means, and an amplification means are two-dimensionally arranged on a semiconductor substrate, and rows are arranged in the imaging area. A plurality of vertical selection lines arranged in the vertical direction, vertical selection means for driving the vertical selection lines, a plurality of vertical signal lines arranged in a column direction for reading the output of the amplifying means, and the plurality of vertical selection lines. A plurality of vertical signal line driving auxiliary means provided on the signal line; noise suppressing means provided at an end of the vertical signal line for taking in and subtracting noise and signal appearing with a time difference in the vertical signal line; A horizontal signal line, a horizontal read line that relays the output of the horizontal select line and the noise suppression unit, and a horizontal select unit that drives the horizontal read unit. The double signal line and the noise Amplifying solid-state imaging device characterized by comprising a voltage amplification means for amplifying the signal voltage of the vertical signal line between the pressure means.
5. A plurality of photosensitive cells each comprising a photoelectric conversion means, a signal charge storage means, a signal charge discharge means, a row selection means, and an amplification means arranged on a semiconductor substrate in a row direction of an imaging region in which the photosensitive cells are two-dimensionally arranged. Drive the vertical selection line of the vertical selection means,
The output of the amplifying means is read out by a plurality of vertical signal lines arranged in the column direction, and a plurality of vertical signal line driving auxiliary means provided on the plurality of vertical signal lines and a noise suppressing means provided at an end of the vertical signal line. The noise and signal appearing on the vertical signal line with a time difference are taken in and subtracted by the means, a MOS transistor is provided between the vertical signal line and the noise suppression means, and the gate electrode of the MOS transistor and the voltage amplification storage capacitor are connected. A charge integration means comprising a feedback MOS transistor and a voltage amplification storage capacitor is connected between the drain and the drain, and the horizontal selection line arranged in the column direction of the imaging region and the output of the noise suppression means are relayed by the horizontal reading means. In an operation method of an amplification type solid-state imaging device in which a horizontal readout unit is driven by a horizontal selection unit, a first step of applying a reference voltage to the vertical signal line; and a reference voltage to the vertical signal line. The feedback MO when you give
A second step of driving the S transistor; and, when the amplified signal and the amplified noise are transferred to the voltage amplification storage capacitor via the MOS transistor after driving the MOS transistor for the period, the feedback MOS transistor is driven. And performing a subtraction operation of the voltage-amplified signal and noise by the noise suppression unit.
6. A plurality of photosensitive cells each comprising a photoelectric conversion unit, a signal charge storage unit, a signal charge discharge unit, a row selection unit, and an amplification unit arranged on a semiconductor substrate in a row direction of an imaging area in which the photosensitive cells are two-dimensionally arranged. Drive the vertical selection line of the vertical selection means,
The output of the amplifying means is read out by a plurality of vertical signal lines arranged in the column direction, and a plurality of vertical signal line driving auxiliary means provided on the plurality of vertical signal lines and a noise suppressing means provided at an end of the vertical signal line. Means for extracting and subtracting noise and signal appearing in the vertical signal line with a time difference, subtracting the vertical signal line between the vertical signal line and the noise suppressing means, and a variable voltage amplifying storage capacitor capable of controlling a variable electric capacitance value from outside. An amplification type solid-state device, wherein a horizontal integration line arranged in the column direction of the imaging area and an output of the noise suppression device are relayed by a horizontal reading device, and the horizontal reading device is driven by the horizontal selection device. The method of operating an imaging apparatus includes a first step of providing a capacitance variable signal from the outside, and a second step of controlling the sensitivity by changing the capacitance value of the voltage amplification storage capacitor. Toss Operation method of the amplification type solid-state imaging device.
JP9056307A 1997-03-11 1997-03-11 Amplifier-type solid-state image-pickup unit and operating method therefor Abandoned JPH10257389A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9056307A JPH10257389A (en) 1997-03-11 1997-03-11 Amplifier-type solid-state image-pickup unit and operating method therefor

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Application Number Priority Date Filing Date Title
JP9056307A JPH10257389A (en) 1997-03-11 1997-03-11 Amplifier-type solid-state image-pickup unit and operating method therefor
US09/038,039 US6037577A (en) 1997-03-11 1998-03-11 Amplifying solid-state image pickup device and operating method of the same

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JPH10257389A true JPH10257389A (en) 1998-09-25

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