JPH02135981A - Image receiver controller - Google Patents

Abstract

PURPOSE:To obtain a high definition reception picture quality with simple configuration by executing the calculation of a clamp level, the detection and quantization of noise quantity, automatic gain control, etc., in a central processing unit in a concentrated way. CONSTITUTION:The DC level of an input signal is reproduced, the A/D conversion gain of the input signal is controlled, the quantity of a noise mixed in either a transmitting process or a recording process is detected, and controls noise reduction without the sense of incongruity in the sense of sight by writing an A/D converted signal through a digital filter having a variable characteristic to a RAM 35, reading out the A/D converted signal by a CPU 38, and calculating the A/D converted signal. Further, both the control system of an input level and a clamp level control system are processed in the CPU 38 in the concentrated way. Thus, the mutual interference between the system of the automatic gain control of the input level and the clamp level control system can be reduced, and a stable receiving system having satisfactory response characteristics can be realized with simple hardware configuration.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a receiver control device that multiplexes and transmits a clamp level reference signal and an amplitude reference signal on a video signal.

2. Description of the Related Art Conventionally, a clamp level reference signal multiplexed with a video signal is used not only to reproduce the DC level of the original video signal but also to detect the amount of noise. An example of a DC level regeneration method is disclosed in Japanese Unexamined Patent Publication No. 124373/1983. Further, a method of detecting the amount of noise using a clamp level reference signal multiplexed with a video signal and controlling a reproducing device is disclosed in, for example, Japanese Patent Laid-Open No. 172879/1983. FIG. 7 shows the configuration of a conventional receiver control device that uses these methods to perform DC level reproduction, noise amount detection, and automatic gain control processing.

In FIG. 7, 1 is an input signal, 2 is an analog clamper, 3 is an A/D converter, and 4 is a digital signal output.

The input signal 1 is clamped to a predetermined value by an analog clamper 2, and then converted to, for example, an 8-bit digital signal by an A/D converter 3.

The digital level comparator 5 calculates the difference between the value obtained by digitally converting the clamp level reference signal portion of the input signal and a predetermined digital value, for example, a numerical value of 128. Integrating circuit 6 integrates the output of digital level comparator 5,
It is converted into an analog clamp level signal by the D/A converter 7 and connected to the analog clamper 2 to form a feedback loop, and the average value of the digital signal obtained by A/D converting a predetermined portion of the input signal is 128. This is how it is controlled. Digital level comparator 5 and integrator 6
The operating speed of is the same as the conversion speed of the A/D converter.

8 to 17 are parts for detecting the amount of noise.

The A/D converted value of the clamp level reference signal should be a substantially constant value if no noise is mixed in, but normally the value changes for each sample value due to the influence of noise on the transmission path. The variance of this sample value from the average value represents the energy of the noise. Noise is a random process, so to actually determine the noise level, we process many sample values and then perform low-pass filtering along the time axis, that is, temporal filtering to suppress temporal fluctuations. It is necessary to treat things as noise levels. The A/D converted signal 4 uses a flip-flop 8 and a subtracter 9 to take the difference of one clock period, which is the same as the operating clock (terminal 19) of the A/D converter, and then outputs the difference in the flip-flop 10. ,
Sampling is performed using the clock (b) from the terminal 20.

Next, a difference of one cycle of the clock (a) from the terminal 22 is obtained using the flip-flop 11 and the subtracter 12. During the period of the clamp level reference signal, the clock (0
) represents the position of the signal used for noise detection. 13 to obtain an absolute value, and a low-pass filter in the time axis direction, that is, a temporal filter 14, to obtain a signal corresponding to the noise level. The temporal filter 14 is configured as shown in FIG. 8, and is intended to reduce temporal fluctuations in input.

In FIG. 8, 21 is a subtracter, 22 is a coefficient multiplier with a gain of 1, 23 is an adder, 24 is a delay circuit, and 25 is a coefficient multiplier with a gain of 2. The coefficient unit 22, adder 23 and delay circuit 24 constitute a digital integration circuit 26. That is, the input of the integrating circuit 26 multiplied by 1 is added to the past value, and when a constant input value is given, the output changes with a slope proportional to the input value. This integrating circuit is provided with a subtracter 21, and a loop is formed in which the output is doubled by a coefficient multiplier 25 and then supplied to the subtracter 21. By doing this, when an appropriate positive input is given, the output of the integrating circuit 26 will gradually increase, but as the output of the delay circuit 24 increases, the value fed back will also increase. Eventually, the output of the subtracter 21, which subtracts the output of the coefficient multiplier 25 from the input (~), becomes smaller, and the change in the output of the integrating circuit 26 becomes slow, and finally, 26
The output becomes a constant value proportional to the input value and becomes stable.

Therefore, the circuit having the configuration shown in FIG. 8 operates as a so-called temporal filter that suppresses fluctuations in the time direction. The threshold circuit 15 is the detected noise level (c)
(FIG. 7) is quantized into, for example, four steps, and the degree of noise reduction is switched to four steps.

16 to 18 are systems for automatic gain control, in which the analog input signal from terminal 1 is digitized by the A/D converter 3, and the deviation of the amplitude reference signal contained therein from a predetermined value is digitized. Detected by gain detector 16. The integrator 17 removes the effects of noise and increases the closed loop DC gain to avoid offset errors. The output of the integrator 17 is converted into an analog signal by the D/A converter 18, and is supplied to the A/D converter 3 as an A/D reference voltage (N).
A feedback loop is formed by controlling the D conversion gain so that the signal obtained by A/D converting the input amplitude reference signal has a predetermined digital value.

However, in this type of receiver control device, most of the circuits for clamp level calculation, noise level detection, and automatic gain control are constructed from separate circuits. The problem is that the required hardware is large. In addition, many parts such as the digital level comparator 16, integrator 6, 17.26, etc. need to operate with the same relatively high frequency clock as the A/D converter operating clock (a), which reduces power consumption. It was also disadvantageous. Also, the detected noise level (
Since the noise level (c) is simply quantized into about four stages and used for noise reduction control, if the value of the noise level (c) happens to be near one of the multiple thresholds of the threshold circuit 15, the residual Even slight fluctuations in the noise level result in frequent stepwise changes in the noise reduction level.

In other words, the noise reduction level (D) may change even though the noise level contained in the input signal input from terminal 1 has hardly changed.
This means that, for example, the S/N ratio of the screen changes while receiving a still image or the like, which has the disadvantage that the received image quality from a visual viewpoint is significantly degraded. In addition, the operation of the clamp level processing circuit and the operation of the automatic gain control circuit are not processed in relation to each other, and therefore, in some cases, the clamp operation and automatic gain control operation may interfere with each other, resulting in unstable operation. was there.

Next, a case where the clamp operation and the automatic gain control operation interfere with each other will be explained. As a means for performing gain control, there is a method of controlling the conversion rate between an input analog signal and an output digital value by changing the reference voltage of an A/D converter. Most A/D converters are usually equipped with such a reference voltage input terminal, and gain control using this method is simple in terms of circuit configuration and may not require a special gain control amplifier. Yes, it can be said to be an effective method.

Generally, there are two reference voltages inside an A/D converter: a reference voltage that determines the input analog level that gives the maximum output digital value, and a reference voltage that determines the input analog level that gives the minimum output digital value. , the difference between these two voltages is inversely proportional to the A/D conversion gain.

However, some A/D converters output only one of these reference voltages to the outside, and in order to ensure A/D conversion performance, it is almost impossible to change one of these reference voltages. An A/D converter is also present. In such a case, the conversion gain is controlled by controlling one of the reference voltages.

Figures 9a and 9b are diagrams showing an example of the operation of an A/D converter when conversion gain control is performed using only one reference voltage, and the reference voltage of the A/D converter, the input analog voltage, and the digital Shows the relationship between output values. In Figure 9a, the number of bits of the A/D converter is 8 bits, the input analog level that gives the maximum value of the output digital value is determined by yI/77, the voltage is VRT (-1, Ov), and the output digital value is Let V*e (-3, OV) be the reference voltage that determines the input analog level that gives the minimum value. Further, the reference value of the clamp level is assumed to be -2, OV level for the input analog signal of terminal 1, and 128 for the corresponding digital signal. Assume that in a system operating stably in such a state, there is a stepwise increase in input amplitude while the DC reproduction level of the input signal from terminal 1 remains unchanged. There is no change in the DC reproduction level of the input signal from terminal 1, so the reference value of the clamp level should continue to be at the level of -2, OV. Now, as the amplitude of the input signal becomes larger, the reference voltage (N) to the A/D converter 3 changes from -3.OV due to the operation of the automatic gain control system composed of 16 to 18, and for example, -4, OV is assumed. This allows V RT and V
The difference in RB increases, and as a result, the conversion gain of the A/D converter 3 decreases to compensate for the increase in the amplitude of the input signal.

Problem to be Solved by the Invention However, when the clamp level reference value -2, OV is set to A
The value of the /D-converted digital signal becomes a value larger than 128, for example 170, and an error signal similar to that when the DC reproduction level fluctuates greatly from 128 is detected, making the clamp level control operation unstable. Or, it may have taken a long time for the clamp level to return to normal.

Since there is no fluctuation in the DC reproduction level of the input signal, fluctuations in the clamp level should not be detected. However, using an A/D converter that performs gain control by controlling only one reference voltage, In this case, even if only a gain variation occurs, it is assumed that there is also a DC level variation at the same time, and that disturbance is applied to the system that controls the clamp level. That is, it has the disadvantage that changes in the amplitude of the input signal also affect the reproduction of the DC level.

The present invention solves the above problems and realizes a receiver control device that provides high quality received images with a simple configuration.

Means for Solving the Problems The present invention writes a signal obtained by A/D converting an input signal into a memory through a digital filter with variable characteristics, reads it out by a central processing unit (hereinafter abbreviated as CPU), and performs calculations.
It is characterized in that the calculation of the clamp level, detection and quantization of the amount of noise, automatic gain control, etc. are performed centrally by the central processing unit.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 16.

In FIG. 1, it is assumed that the input signal (g) includes, for example, a clamp level reference signal of 256 samples in one field. Input signal (G) is analog clamper 3
0 to a predetermined level, and the A/D converter 31 sets the sample frequency to a predetermined sampling frequency, for example, 16 MHz.
The data is converted into digital data (Figure 2 (h)). A digital filter 32 is used to perform calculations on a portion of the digital data that corresponds to the clamp level reference signal. This calculation may be performed, for example, by alternately performing the sum and difference of two adjacent signals, and in this case, the output of the digital filter 32 will be as shown in FIG. What kind of calculation is performed by the digital filter 32 is controlled by a timing generation circuit 33 that operates in synchronization with the video signal.

The output of the digital filter 32 is supplied to the data input terminal 351 of the RAM 35 via the data selector 34. The timing generation circuit 33 described above controls the initial counting value of the counter 36, and the output of the counter 36 is connected to the address input terminal 352 of the RAM 35 via the address selector 37. In this way, the clamp level reference signal in the input signal is A/D converted, the sum or difference between adjacent signals is calculated, and then stored at a predetermined address in the RAM 35. After writing data to the RAM 35 is completed, the CPU 38 processes the data in the RAM 35 to perform calculations for clamp level, noise level detection, and automatic gain control. 381 is the CPU data bus, and 382 is the CPU address bus.

The arithmetic processing operations of the receiver control device according to the embodiment of the present invention configured as described above will be explained.

The CPU 38 calculates the clamp level for each field. Assuming that the clamp reference level is the central value of the 8-bit digital signal, ie, 128, the A/D-converted signal, if considered as an offset binary value, directly represents the error from the clamp reference level.

That is, the digital signal obtained by A/D converting the clamp level reference signal can be used as it is as a signal representing the error in the clamp level. The data used for calculating the clamp level is obtained by calculating the sum of signals of two adjacent samples using a digital filter 32. The calculation of the clamp level by the CPU 38 uses 128 pieces of data written in the RAM 35 as the sum of two adjacent signals.

Since the 128 pieces of data are already an average of adjacent signals, the number of additions can be reduced to 1/2 compared to when 256 pieces of clamp level reference signal data are directly averaged. The burden is reduced.

Although the addition operation itself is extremely easy for the CPU 38, it requires a large number of operations, and as a result, the CPU 38
This is a burden on the public. Therefore, halving the number of data additions from 256 to 128 means that the CPU 38
This will greatly contribute to reducing the burden on people. The 128 pieces of data that have been averaged are then subjected to integration processing. This integration prevents offset errors from occurring by making the DC gain infinite.

The 128 pieces of data described above may be directly integrated without being averaged, but in that case,
Every time data is added, it is necessary to check whether the calculation has caused an overflow, and if the calculation is performed by software, it is disadvantageous in terms of the time required for the calculation. In the case of the method that performs averaging processing and integration, only 128 additions are required for averaging processing, 1 addition and 1 overflow check are required for integration processing, and the addition operation is reduced to 1. Although this increases the number of overflow checks, it has the advantage that 127 overflow checks can be omitted. The integrated signal is sent to the D/A converter 3.
9 is converted into an analog signal and connected to the analog clamper 3o to form a feedback loop, and operates so that the average of the signals obtained by A/D converting the clamp level reference signal included in the signal input from terminal 1 is 128. .

The automatic gain control process by the CPU 38 is performed by using, for example, a frame pulse signal transmitted for each frame as an amplitude reference signal. Assuming that the frame pulse signal has two levels, the deviation of the difference between the two levels from a predetermined value represents an error with respect to the normal gain. Digital filter 3 is used for automatic gain control calculation.
2, the sum of the signals of two adjacent samples is used. The automatic gain control calculation by the CPU 38 uses about 20 pieces of data written in the RAM 35 as the sum of two adjacent signals. Since the 20 pieces of data are already an average of adjacent signals, the number of additions can be reduced to 1/2 compared to when 40 frame pulse signals, which are also the amplitude standards, are directly averaged. The processing burden is reduced. Although the addition operation itself is an extremely easy operation for the CPU 38, it requires a large number of operations, and as a result, it becomes a burden on the CPU 38. Therefore, halving the number of data additions greatly contributes to reducing the burden on the CPU 38. The averaged data is then subjected to integration processing. This integration prevents offset errors from occurring by making the DC gain infinite. The above 20 pieces of data can be directly integrated without averaging, but in that case, it is necessary to check whether the calculation has overflowed each time data is added. If the calculation is performed by software, it is disadvantageous in terms of the time required for the calculation.

In the case of the method of performing averaging and integrating, only 20 additions are required for the averaging process, and 1 addition and 1 overflow check are required for the integration process, which reduces the number of addition operations to 1. This increases the number of overflow checks, but this has the advantage that 19 overflow checks can be omitted. The integrated signal is converted into an analog signal by the D/A converter 40, which is connected to the A/D converter 31 as a reference voltage (nu), and the conversion gain of the A/D converter 31 is controlled to form a feedback loop. is formed, and operates so that the difference between the two signal levels of the frame pulse becomes a predetermined value.

FIG. 3 shows the procedure of noise level calculation processing according to the present invention. The data used to detect the noise level is the difference data between two adjacent signals obtained by the digital filter 32 in FIG. 1. This difference data (w) is subjected to absolute value processing 42 and then to limiter processing 43.

Furthermore, fluctuations in the time axis direction are suppressed by temporal filter processing 44, further, hysteresis processing 45 is performed, and quantization processing 46 is performed to quantize the hysteresis into several stages to obtain a noise reduction control signal. The calculation of the noise level by the CPU 38 is based on 1 written in the RAM 35.
28 pieces of differential data are used. This makes it possible to omit software processing for calculating differences between a large number of sample values. These operations that can be omitted are simple and extremely easy for the CPU 38, but the amount of data to be processed is large, and as a result, the CPU 38
This is a burden of 8. By providing the digital filter 32 and having the digital filter 32 process simple calculations that require a large number of calculations, the CPU 3B can ensure the ability to perform more sophisticated calculations. The difference between the obtained sample values is first subjected to absolute value processing at 42.

The average value of these values basically corresponds to the noise level, but 43 limiter processing is then performed to prevent overflow from occurring in subsequent processing. This absolute value processing 42 and limiter processing 43 can be performed simultaneously by a method such as table reference. This limiter processing 43 increases the probability of clipping when the noise level increases to a certain extent. However, since noise is random, there are naturally cases where it is not clipped. In other words, even if the noise level becomes considerably large, the average level of the limiter output does not saturate immediately, so that a sudden increase in the noise level is compressed, and noise level detection over a wide dynamic range can be performed. can.

This is an extremely useful property when performing operations with a limited number of bits. FIG. 4 shows the input/output characteristics of the absolute value processing 42, limiter processing, and temporal filter processing in FIG. 3, that is, the noise amount detection characteristics.

Note that even if the average noise level falls below a certain level, noise with large amplitude occasionally occurs, so
If the noise level is smaller than in the case of a point, the value of the noise level detection result will not be so small. However, by setting point A below a practical noise level, a wide practical noise M detection range can be secured.

The signal corresponding to the detected amount of noise is subjected to temporal filter processing to suppress fluctuations in the time axis direction.

This processing can be performed by software processing equivalent to the circuit shown in FIG. If you control the noise reduction by quantizing the temporal filter output (W) in four stages as it is, if the value of the temporal filter output (W) happens to be around the quantization threshold, even if the value of the temporal filter output (W) happens to be around the quantization threshold, ), that is, the noise level is a nearly constant value, the noise reduction control level may vary frequently, and the received image quality in terms of visual psychology deteriorates significantly. In order to prevent this, noise level quantization processing 45 is performed with a hysteresis characteristic as shown in FIG. 5, and the noise level is divided into four stages and outputted from the output port 41 as a noise reduction control signal. According to experiments, the width of this hysteresis is practically 1 to 2 dB. In actual stable reception conditions, the average noise level changes over a few seconds by less than 1 to 2 dB, and by providing such hysteresis characteristics, it is possible to avoid frequent changes in the degree of noise reduction. Become.

Note that the digital filter 32 includes, for example, an adder 321, a delay circuit 322, and an exclusive circuit as shown in FIG.
It can be easily constructed using a sibu-OR circuit 323 or the like. In FIG. 6, (force) is a characteristic control signal that controls the characteristics of the digital filter 32.
selects whether to perform a sum calculation or a difference calculation between adjacent signals.

Furthermore, in the case of this embodiment, the only part of the calculation section that requires high-speed processing is the digital filter 32, and as described above, the digital filter 32 has a relatively simple configuration as shown in FIG. This is advantageous in terms of power consumption.

Furthermore, when the detected amount of noise is quantized and used as a noise reduction control signal, it is possible to detect that the screen is in a scene change state, and to control the noise reduction control signal in synchronization with this, the noise reduction can be performed without any noticeable discomfort. can be controlled.

Furthermore, in the configuration according to the present invention, since the operating status of the clamp level processing and the operating status of the automatic gain control processing are grasped at the same time by the CPU 3B, even when a change in the amplitude of the input signal occurs, the It becomes possible to perform only gain control independently without affecting the clamp level control system. For example, the reference voltage (nu) that controls the conversion gain of the A/D converter 31
To prevent the gain control operation from affecting the clamp level operation by reading and calculating the error from the clamp reference level according to the digital value output to the output D/A converter 40. becomes possible. That is, when the conversion gain of the A/D converter 31 is smaller than the standard, the signal obtained by A/D converting the clamp level reference signal is read as a smaller value, and when the conversion gain of the A/D converter 31 is larger than the standard, the signal obtained by A/D converting the clamp level reference signal is read as a smaller value. A/D clamp level reference signal
The converted signal is read as a larger value and the clamp level is calculated. This rereading operation is performed by CPU3.
8, this can be easily done using a table reference command or the like.

Note that in the embodiment of the present invention, the digital filter 32
Although it has been explained that the calculation according to the above is effective in reducing the calculation burden on the CPU 38, if the CPU 38 has sufficient ability, the operation of the digital filter 32 may be made to be an all-band pass filter, or the digital filter 32 may be removed. You can also do it.

Effects of the Invention As described above, the receiver control device of the present invention transmits A/D converted signals to RA via a digital filter with variable characteristics.
By writing in M and reading and calculating it in the CPU, the DC level of the input signal is reproduced, the A/D conversion gain of the input signal is controlled, and the amount of noise mixed in during the transmission or recording process is detected. It is possible to control noise reduction without causing visual discomfort. Also,
Since both the input level control system and the clamp level control system are intensively processed by the CPU, mutual interference between the input level automatic gain control system and the clamp level control system can be reduced, resulting in stable and stable operation. A receiving system with good response characteristics can be realized with a simple hardware configuration.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a receiver control device according to an embodiment of the present invention;
Fig. 2 is an explanatory diagram showing an example of calculation in the characteristic variable digital filter of the same device, Fig. 3 is a block diagram of noise level detection processing with a limiter in an embodiment of the present invention, and Fig. 4 is a noise amount according to the present invention. FIG. 5 is a characteristic diagram showing detection characteristics. FIG. 5 is a characteristic diagram of quantization processing with hysteresis characteristics in an embodiment of the present invention. FIG. 6 is a configuration diagram of a variable characteristic digital filter in an embodiment of the present invention. FIG. 7 8 is a configuration diagram of a conventional receiver control device that performs clamp level processing, noise level detection, and automatic gain control. FIG. 8 is a configuration diagram of a conventional temporal filter. FIG. 9 is a diagram of gain control in an A/D converter. It is an explanatory diagram of operation. 30...Analog clamper, 31...A/converter, 32
・・Digital filter, 321・・Adder, 322・
・Delay circuit, 323... Exclusive O circuit, 33
...Timing generation circuit, 34...Data selector, 3
5...RAM136...Counter, 37...Address selector, 38...CPU, 381...CPU data bus, 382...CPU address bus, 39.40...D/
A converter, 41...output port, 42...absolute value processing. Name of agent Patent attorney Shigetaka Awano First name (Figure 6 Figure 6 (Q-) Figure (b)

Claims (8)

[Claims] (1) An analog clamper that clamps an input signal to a predetermined DC level, an A/D converter that A/D converts the output of the analog clamper at a predetermined sampling period, a timing generation circuit, and the timing generation circuit. a controlled counter circuit, a central processing unit (CPU), a data selector that switches between an output signal of the A/D converter and a data bus of the CPU and supplies the signal to the RAM;
an address selector that switches between the output of the counter circuit and the address bus of the CPU and supplies the data to the RAM; A receiver control device, characterized in that it outputs a noise reduction control signal according to the noise level mixed in during the process, and outputs a clamp level signal from the D/A converter. (2) In claim 1, the signal stored in the RAM is a signal obtained by A/D converting the clamp level reference signal included in the input signal and the gain reference signal included in the input signal, and A receiver control device that outputs a clamp level signal from an A converter, a signal for gain control from a second D/A converter, and a noise reduction control signal from an output port. (3) an analog clamper that clamps an input signal to a predetermined DC level; an A/D converter that A/D converts the output of the analog clamper at a predetermined sampling period;
a digital filter that calculates predetermined frequency characteristics on the output signal of the /D converter; a timing generation circuit that controls the frequency characteristics of the digital filter at a period that is an integral multiple of the sampling period; and a timing generation circuit that is controlled by the timing generation circuit. a central processing unit (CPU); a data selector that switches between the output of the digital filter and the data bus of the CPU and supplies it to the RAM; and an address selector that switches and supplies data to the RAM, and performs arithmetic operations on the data stored in the RAM by the CPU to perform noise reduction control according to the noise level mixed in during the process of transmission or recording from the output port of the CPU. A receiver control device characterized in that the D/A converter outputs a clamp level signal. (4) In claim 3, the signal stored in the RAM is obtained by applying a digital filter with predetermined characteristics to a signal obtained by A/D converting a clamp level reference signal included in the input signal and a gain reference signal included in the input signal. The first D/A converter outputs a clamprel signal, and the second
A receiver control device that outputs a signal for gain control from the D/A converter and outputs a noise reduction control signal from the output port. (5) In claim 1 or 3, the clamp level signal is calculated using signals obtained by A/D converting each of the clamp level reference signal included in the input signal and the amplitude reference signal included in the input signal. A receiver control device characterized by: (6) In claim 5, the clamp level signal is obtained by obtaining a difference signal from a predetermined level of a signal obtained by A/D converting the clamp level reference signal included in the input signal, integrating the difference signal, and converting the clamp level signal into the input signal. A receiver control device that performs calculations using a signal used for gain control of the A/D converter obtained by processing a signal obtained by A/D converting the included amplitude reference signal. (7) In claim 1 or 3, the noise reduction control signal takes the absolute value of the difference between predetermined sample values of the clamp level reference signal, and obtains the absolute value of the difference between predetermined sample values of the clamp level reference signal through limiter means and quantization means having hysteresis characteristics. A receiver control device characterized in that: (8) The receiver control device according to claim 3, further comprising means for updating the noise reduction control signal in synchronization with a scene change of the input image.