JP2001343945A - Planar display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make an external control circuit compact and to reduce the cost of the circuit in a planar display device in which a driving circuit or the like are arranged on an array substrate. SOLUTION: In this display device, a charge pump circuit 10 is arranged on an array substrate 101 and an output capacitance 15 to be connected between the output side of the circuit 10 and the ground (GND), and the input capacitance 16 of a clock input part are arranged at the outside of the substrate 101.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a flat display device, and more particularly to a flat display device having a driving circuit and the like disposed on a substrate on which pixels are formed.

[0002]

2. Description of the Related Art A flat display device represented by a liquid crystal display device has been used in a wide range of fields by making use of characteristics such as thinness, light weight, and low power consumption. Above all, a liquid crystal display device in which a TFT (thin film transistor) is arranged as a switching element for each pixel is widely used as a display device for an information equipment terminal or a thin television. In particular, in recent years, in order to increase the effective screen area on an array substrate of the same area and reduce the manufacturing cost, an active matrix type in which drive circuits and power supply circuits are arranged on an array substrate on which pixels are formed Liquid crystal display devices are being developed.

[0003]

By the way, various clock signals, power supply voltages, and the like are supplied from an external control circuit provided outside to a drive circuit and a power supply circuit disposed on the array substrate. The external control circuit includes IC components such as a control IC, a D / A converter, a level shifter, and a charge pump circuit (voltage source circuit).

In the charge pump circuit, a large-capacity capacitor is arranged in the clock input section and the output section in order to suppress the fluctuation of the output voltage. However, in the current manufacturing process, it is difficult to form a large-capacity capacitor on the array substrate, and it has been difficult to arrange the charge pump circuit on the array substrate. Therefore, there is a problem that it is difficult to reduce the size of the external control circuit, and the cost is increased due to the necessity of high-performance IC components.

On the other hand, a glass substrate such as an array substrate has a T
In the operation of forming the FT, the manufacturing process is difficult, and the characteristics of the transistor are often unstable. For these reasons, even when the charge pump circuit is formed on the array substrate, the transistor characteristics of the TFTs constituting the circuit become unstable, the threshold value varies, and the output voltage fluctuates. was there.

Further, the TFT on the array substrate is made of polycrystalline Si.
In the case where the TFT is formed, the performance of the TFT is inferior to that in the case where the TFT is formed of single crystal Si. For this reason, there is a problem that the area required for the arrangement is increased, and the frame is accordingly increased.

A first object of the present invention is to provide a flat display device which realizes a compact and low cost external control circuit.

A second object of the present invention is to provide a flat display device capable of stabilizing an output voltage from a charge pump circuit without being affected by a TFT manufacturing process.

A third object of the present invention is to provide a flat display device in which circuits such as a charge pump circuit can be arranged on an array substrate without enlarging a frame.

[0010]

According to a first aspect of the present invention, there are provided a plurality of scanning lines and a plurality of signal lines which intersect each other, a switching element disposed at each intersection of these two lines, and A first substrate including a connected pixel electrode; a second substrate including a counter electrode facing the pixel electrode; and a light modulation layer held between the first substrate and the second substrate. A display panel, a signal line driving circuit for supplying a data signal to the signal line, a scanning line driving circuit for supplying a scanning signal to the scanning line, a predetermined signal to the signal line driving circuit and the scanning line driving circuit, In a flat panel display device having an external control circuit for supplying a potential, a voltage source circuit included in the external control circuit is arranged on the first substrate, and a voltage is applied between an output section of the voltage source circuit and ground. Capacity,
In addition, the capacitance of the clock input unit is arranged outside the first substrate.

In a preferred embodiment, in a configuration in which an auxiliary capacitor is electrically connected in parallel with the pixel electrode, the auxiliary capacitor is included in a capacitor disposed between an output section of the voltage source circuit and ground. Features.

According to a second aspect of the present invention, in the voltage source circuit of the first aspect, the first thin film transistor having a different polarity and the second thin film transistor are connected to each other.
Thin film transistors are connected in series, a first input portion for inputting a clock signal via a first capacitor is connected to the gate electrodes of the first thin film transistor and the second thin film transistor, and via a second capacitor A second input unit for inputting an inverted clock signal of the clock signal is configured to be connected to an intermediate connection point between the first thin film transistor and the second thin film transistor;
A capacitance is arranged outside the first substrate together with a capacitance between an output of the second thin film transistor and ground.

According to a third aspect of the present invention, the voltage source circuit of the first aspect is configured such that a first thin film transistor and a second thin film transistor having different polarities are connected in series, and the two thin film transistors are further paired in series. It is characterized by being connected.

In a preferred embodiment, a first thin film transistor and a second thin film transistor having different polarities are connected in parallel, and the two thin film transistors are further paired and connected in series.

According to a fourth aspect of the present invention, the voltage source circuit according to any one of the first to third aspects is arranged in an area on the first substrate opposite to an area where the scanning line driving circuit is arranged.

In a preferred embodiment, a bypass capacitor is arranged in a region on the first substrate opposite to a region where the scanning line driving circuit is arranged.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a case will be described in which a flat display device according to the present invention is applied to an active matrix type liquid crystal display device in which a drive circuit is integrated on an array substrate.

[Embodiment 1] First, as Embodiment 1,
A liquid crystal display device that realizes a compact external control circuit and low cost will be described.

FIG. 1 is a circuit configuration diagram of the liquid crystal display device according to the first embodiment, and particularly shows the configuration of an array substrate and an external control circuit. On the array substrate 101 shown in FIG. 1, a pixel portion 103 in which a plurality of pixels are formed, a scan line driver circuit 104, and a signal line driver circuit 105 are arranged.

The pixel portion 101 has a plurality of signal lines S1,
(Hereinafter, generically S) and a plurality of scanning lines G1, G2,... (Hereinafter generically G) intersecting with each other are arranged so as to intersect with each other. The portion is provided with a TFT 11 as a switch element.
The signal lines S and the scanning lines G are electrically insulated by an insulating film (not shown).

The source electrode of the TFT 11 is connected to the signal line S, and the drain electrode is connected to the pixel electrode 12.
Although not shown in FIG. 1, a counter electrode paired with the pixel electrode 12 is formed on a counter substrate (not shown). The array substrate 101 and the counter substrate are arranged at predetermined intervals so that their respective electrode surfaces face each other, and the periphery thereof is sealed with a sealing material. Then, the inside of both substrates is filled with a liquid crystal material to be a light modulation layer.

In the array substrate 101, an auxiliary capacitor 13 is connected in parallel with the pixel electrode 12 in order to maintain a potential relationship with a counter electrode (not shown). The auxiliary capacitance 13 is composed of the pixel electrode 12 and auxiliary capacitance lines C1, C2,.
(Hereinafter, collectively C) forms a capacitance Cs. The auxiliary capacitance line C is electrically connected to the auxiliary capacitances 13 of all the pixels, and is supplied with a constant voltage from the external control circuit 102.

Further, a constant common voltage (Vcom) is applied to the counter electrode (not shown) from the external control circuit 102. The data signal written through the signal line S is held for one frame scanning period by the liquid crystal capacitance Clc and the capacitance Cs.

The scanning line driving circuit 104 includes a timing circuit (shift register) and a buffer circuit (not shown), and scan lines G 1 and S 1 based on a vertical clock signal CKV and a vertical start signal STV supplied from the external control circuit 102. G2... Sequentially output scanning signals.

The signal line driving circuit 105 includes a timing circuit (shift register) (not shown), a video bus, an analog switch circuit, and the like. The analog switch circuit is composed of TFTs, and respective drain electrodes are connected to signal lines S1, S2, S3,. The timing circuit controls the analog switch circuit based on the horizontal clock signal CKH and the horizontal start signal STH supplied together with the data signal from the external control circuit 102, and outputs the data signal at a predetermined timing to the signal lines S1, S2, S3.・ Sampling is performed. In addition,
The driving method of the signal line driving circuit may be a D / A conversion method in addition to the analog sample and hold method.

The external control circuit 102 comprises a control IC (not shown), a D / A converter, a level shifter, and the like. The external control circuit 102 appropriately converts and processes a reference clock signal and a digital data signal supplied from the outside. An analog data signal, a horizontal / vertical clock signal, a start signal, a power supply voltage (VDD1, VDD)
2) Output common voltage and the like. This external drive circuit 1
02 and the array substrate 101, an unillustrated FPC
(Flexible wiring board).

On the array substrate 101, a charge pump circuit 10 is arranged. This charge pump circuit 1
0 indicates that the output-side capacitance 15 provided between the output portion of the circuit and the ground (GND) and the input-side capacitance 16 provided at the clock input portion are both arranged on the array substrate 101. It is arranged outside the array substrate 101. In FIG. 1, the output side capacitor 15 is drawn outside the array substrate in order to facilitate understanding of the relationship between the output portion of the circuit and the ground.
The output-side capacitance 15 is formed in the external control circuit 102 via the external control circuit 102. However, these capacitors only need to be arranged outside the array substrate 101, and as in this embodiment, the external control circuit 10
There is no need to place them within 2.

The output capacitor 15 is connected to the auxiliary capacitor 13 of each pixel via an auxiliary capacitor line C. As described above, by connecting the auxiliary capacitors 13 attached to all the pixels and the output capacitors 15 disposed outside the array substrate 101, the output voltage can be further stabilized. In the case where the screen has a higher density or a larger size, if the sum of the capacitances Cs of the auxiliary capacitances 13 is sufficiently large, the capacitance of the output-side capacitance 15 arranged outside the array substrate 101 can be reduced. Alternatively, the output-side capacitor 15 itself can be omitted.

Here, the circuit configuration and operation of the charge pump circuit 10 will be briefly described. FIG. 2A is a circuit configuration diagram of the charge pump circuit 10, and FIG. 2B is an equivalent circuit diagram thereof. In FIG. 2, the same parts as those in FIG. 1 are denoted by the same reference numerals.

The charge pump circuit 10 has two Nch
TFTs 17 and 18, input-side capacitance 15 and output-side capacitance 16
It consists of. Among them, the drain electrode side of the NchTFT 17 is connected to the source electrode and the gate electrode of the NchTFT 18.

FIG. 3 is a timing chart showing the operation of the charge pump circuit 10. Referring to FIG.
An operation example of the charge pump circuit 10 will be described.

First, the amplitude VDD is input from the clock input unit 14.
1 clock signal (CKU). For example, FIG.
A square wave having an amplitude of 10 V and a frequency of 1.5 MHz as shown in FIG. In addition, for example, DC10V is input to the power supply input unit 21 as the power supply voltage VDD1.

At the intermediate node pg, the following voltages are maintained according to the input waveform. That is, during a period in which no clock signal is input from the clock input unit 14, V
A voltage obtained by subtracting the threshold value Vth of the Nch TFT 17 from DD1 is maintained. For example, if the threshold value Vth of the Nch TFT 17 is 2 V, the intermediate node pg becomes 8 V
(VDD2-Vth). Also, during a period when the clock signal is being input from the clock input unit 14,
An amplitude waveform boosted by the boost ratio α is obtained. For example, when the step-up ratio α is 1, an amplitude waveform of 8 to 18 V (VDD2−Vth + αVDD1) is obtained as the pulse waveform as shown in FIG. Then, the voltage of the output unit 22 is gradually increased as the clock signal is input to the clock input unit 14, and finally VDD2-2Vth + αV
The output voltage of DD1 is obtained. For example, in FIG. 3C, when the threshold value Vth of the Nch TFT 18 is 2 V, 16 V is obtained as the output voltage.

The liquid crystal display device 10 configured as described above
According to 0, since the charge pump circuit 10 can be arranged on the array substrate 101, the external control circuit 102
Of the external control circuit 102
In addition, since high-performance IC components are not required, the cost can be reduced. In particular, the charge pump circuit 10 arranged in the external control circuit 102 is
In the case of the transfer to the upper side, since a large-capacity capacitor cannot be formed on the array substrate 101, it is difficult to suppress the fluctuation of the output voltage of the charge pump circuit 10 to be small. However, according to the configuration of the first embodiment, it is possible to stabilize the output voltage as in the case where the charge pump circuit 10 is arranged in the external control circuit 102.

Therefore, in the liquid crystal display device of the first embodiment, not only can the output voltage be stabilized as in the conventional case, but also the external control circuit can be made more compact and lower in cost.

[Embodiment 2] Next, as Embodiment 2, when a charge pump circuit is formed on an array substrate, T
A liquid crystal display device that can stabilize the output voltage without being affected by the FT manufacturing process will be described.

Since the basic configuration of the liquid crystal display device according to the second embodiment is the same as that of the first embodiment, the description is omitted, and only the configuration of the charge pump circuit characteristic of the second embodiment will be described.

FIG. 4 is a circuit diagram of a charge pump circuit according to the second embodiment. This charge pump circuit 2
0 is NchTFT25, NchTFT26, PchT
FT 27, input side capacitors 29 and 32, and output side 35.

The Nch TFT 26 and the Pch TFT 27 are connected in series, and the drain electrode side of the Nch TFT 25 is connected to the Nch TFT 26 and the P channel TFT through the intermediate node pg.
It is connected to each gate electrode of chTFT27. A clock signal (CKU) is supplied from the clock input unit 28 to the respective gate electrodes of the NchTFT 26 and the PchTFT 27 via the input-side capacitor 29. Further, from the clock input unit 31, an inverted clock signal (/ CKU) of the clock signal is input to an intermediate node ps, which is an intermediate connection point between the NchTFT 26 and the PchTFT 27, via an input-side capacitor 32.

It should be noted that also in the second embodiment, the capacitors arranged at the clock input section and the output section of the charge pump circuit 20 are arranged outside the array substrate. That is, the input capacitors 29 and 32 shown in FIG. 4 and the output capacitor 35 provided between the output unit 34 and the ground are both arranged outside the array substrate 101.

FIG. 5 is a timing chart showing the operation of the charge pump circuit 20. Referring to FIG.
An operation example of the charge pump circuit 20 will be described.

First, a clock signal (CKU) having the amplitude Vs is input from the clock input section 28, and an inverted clock signal (/ CKU) having the same amplitude Vs is input from the clock input section 31. For example, a square wave with an amplitude of 10 V and a frequency of 1.5 MHz and its inverted square wave as shown in FIGS. In addition, for example, DC 10 V is input to the input unit 33 as the power supply voltage VDD.

At the intermediate node pg, the following voltage is maintained according to the input clock signal (CKU). That is, during a period in which the clock signal (CKU) is not input, the threshold voltage Vth of the Nch TFT 25 is changed from VDD.
The voltage subtracted by the minute is maintained. For example, Nch
Assuming that the threshold Vth of the TFT 25 is 2 V, the intermediate node pg is 8 V (VDD− | Vt) as shown in FIG.
h |). Further, during the period when the clock signal (CKU) is input, an amplitude waveform boosted by the boost ratio α is obtained. For example, when the boost ratio α is 1, FIG.
As shown in (c), 8 to 18 V (VDD + Vs- | Vt
h |) is obtained. The intermediate node ps has N
When the chTFT 26 is on, that is, when the clock signal (C
VDD is maintained during the period when KU) becomes Vs. For example, when the intermediate node pg is 18V and VDD is 10V, 10V is maintained. On the other hand, when the Nch TFT 26 is off, that is, during a period when the clock signal (CKU) is at GND, as shown in FIG. 5D, at the rising edge, only by the amplitude (Vs) of the inverted clock signal (/ CKU). The potential is instantaneously raised, and then drops. For example, when the amplitude of the inverted clock signal (/ CKU) is 10 V, the rising edge instantaneously causes 20 V
(VDD + Vs), and thereafter the potential gradually decreases. The output unit 34 includes a PchTFT2
7 is on, that is, the inverted clock signal (/ CKU)
Current flows from the intermediate node ps during the period when the voltage becomes Vs, and the voltage (VDD + Vs) at the intermediate node ps at this time.
Is the output voltage. For example, when the intermediate node pg is 8 V and the ps is 20 V, 20 V is obtained as the output voltage.

In FIG. 4, when the threshold value Vth of the Nch TFT 26 becomes larger than, for example, a design value due to variation in transistor characteristics, VDD− | Vth | becomes smaller. Therefore, the output voltage required for the drive circuit cannot be supplied only by the output from the Nch TFT 26, and the circuit cannot operate normally. However, the charge pump circuit 20 of the second embodiment
In this case, the potential is instantaneously raised by the amplitude of the inverted clock signal (/ CKU) irrespective of the variation of the threshold value Vth of the Nch TFT 26, so that the voltage (VDD + Vs) at the intermediate node ps at this time is output. By taking out the voltage, a stable output voltage can always be obtained.

Therefore, in the liquid crystal display device of the second embodiment, the output voltage from the charge pump circuit can be stabilized without being affected by the TFT manufacturing process.

Also, in the second embodiment, the charge pump circuit is arranged on the array substrate, and the large-capacity capacitors connected to the input / output unit are arranged outside the array substrate. By arranging a capacitor having a sufficient size as in the case of 1, the output voltage can be stabilized, and the external control circuit can be made more compact and lower cost.

Third Embodiment Next, as a third embodiment, when a charge pump circuit is formed on an array substrate as in the second embodiment, the output voltage is stabilized without being affected by the TFT manufacturing process. A description will be given of a liquid crystal display device that can be made to operate.

The basic configuration of the liquid crystal display device according to the third embodiment is the same as that of the first embodiment, and a description thereof will be omitted. Only the configuration of the charge pump circuit characteristic of the third embodiment will be described. I do.

FIG. 6 is a circuit diagram of a charge pump circuit according to the third embodiment. This charge pump circuit 3
0 indicates two diode circuits 36 and 38 and an output-side capacitance 4
2 and an input-side capacitor 44. The diode circuit 36 includes an NchTFT 136 and a PchTFT 137 connected in series. Also, the diode circuit 38 includes an Nch TFT similarly connected in series.
138 and a PchTFT 139. Further, these two diode circuits 36 and 38 are connected in series. In addition, the charge pump circuit 30 includes:
VDD is input as a power supply voltage from the outside, and a clock signal (CKU) is input from the clock input unit 43.

The charge pump circuit 30 of the third embodiment
Also, the output-side capacitance 42 provided between the output part 41 of the circuit and the ground (GND) and the input-side capacitance 44 provided in the clock input part 43 are both disposed outside the array substrate 101. I have.

The diode circuit 3 configured as described above
In 6 and 38, the threshold values of the two TFTs having different polarities constituting the circuit are approximately Vthn (NchTFT).
+ Vthp (PchTFT). Then, depending on the manufacturing process, the Nch TFT or Pch
Even if the threshold value of the TFT deviates from the design value, Vthn + V
The value of thp is constant. Therefore, the charge pump circuit 30 is not affected by the fluctuation of the manufacturing process.
Can constantly output a stable voltage.

For example, in one embodiment using the charge pump circuit 30 of FIG. 6, Vthn = 2.5 V, Vthp =
Also at −1.5 V, Vthn = 1.5 V, Vthp =
Even at −2.5 V, the same output voltage could be obtained.

As a comparative example, two diode circuits 36 and 38 shown in FIG.
Tth and operating under the same conditions, Vthn =
When 2.5V and Vthp = -1.5V, Vthn =
The output voltage was 2 V lower than when 1.5 V and Vthp = -2.5 V, and display unevenness was sometimes seen on the screen.

Therefore, also in the liquid crystal display device of Embodiment 3, the output voltages Vg1 and Vg2 from the charge pump circuit are not affected by the TFT manufacturing process.
Can be stabilized.

Also, in the third embodiment, the charge pump circuit is arranged on the array substrate, and the large-capacity capacitors connected to the input / output unit are arranged outside the array substrate. The output voltage can be stabilized by disposing a capacitor having a sufficient size as in the case of 1, and furthermore, the external control circuit can be made compact and low cost.

The two diode circuits 3 shown in FIG.
6 and 38, the NchTFT and the PchTFT are connected in series, but as shown in FIG.
chTFTs are connected in parallel and these two diode circuits 46 and 47 are connected in series.
Similar effects can be obtained.

Further, another charge pump circuit may be added to the circuit of FIG. 6 so that the power supply potential of the scanning line driving circuit 104 can be adjusted.

FIG. 8 is a circuit diagram showing an application example of the charge pump circuit according to the third embodiment. In FIG. 8, the configuration of the added charge pump circuit 40 is similar to that of the two diode circuits 3 included in the charge pump circuit 30.
The arrangement is the same as that in which the arrangement of the NchTFT and the PchTFT of Nos. 6 and 38 is exchanged, and a negative voltage is generated. The output voltage is adjusted by using the charge pump circuits 30 and 40 as power sources and arranging an operational amplifier 50 which is also formed of a TFT. Here, the power supply voltage VDD supplied from the outside is used as the reference voltage. With such a circuit configuration, the influence of the TFT manufacturing process can be almost eliminated, and the output voltage Vg
1, Vg2 can be stabilized. Note that the operational amplifier 50 shown in FIG. 8 may be connected to a charge pump circuit of another embodiment.

[Fourth Embodiment] Next, as a fourth embodiment, a liquid crystal display device in which circuits such as a charge pump circuit can be arranged on an array substrate without enlarging a frame will be described.

FIG. 9 is a circuit configuration diagram of a liquid crystal display device according to the fourth embodiment, and particularly shows a circuit arrangement on an array substrate. In FIG. 9, the same parts as those in FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 9, the charge pump circuit 2
Reference numeral 00 denotes an area that is opposed to an area on the array substrate 101 where the scanning line driving circuit 104 is disposed, with the pixel portion 103 interposed therebetween. Charge pump circuit 20
0 and the power supply voltage are supplied to the external signal line 11.
5, and the output voltage from the charge pump circuit 200 is supplied to the scanning line driving circuit 104 and the signal line driving circuit 105 through the internal voltage source lines 117 and 118. Although not shown, capacitors connected to the clock input unit and the output unit of the charge pump circuit 200 are arranged outside the array substrate 101 as in the first embodiment.

In the active matrix type liquid crystal display device as in the fourth embodiment, it is often unnecessary to dispose the scanning line driving circuit 104 and the signal line driving circuit 105 on both sides with respect to the pixel portion 103. Are required on both sides of the pixel portion 103 due to problems such as external attachment. Therefore, for example, when the charge pump circuit 10 is arranged on the scanning line driving circuit 104 side as shown in FIG. 1, the frame must be enlarged, but when the charge pump circuit 10 is arranged in the area A secured in advance as shown in FIG. , A charge pump circuit can be arranged without increasing the frame.

FIG. 10 is a circuit diagram showing an example in which a bypass capacitor 201 is arranged in place of the charge pump circuit 200. Also in this case, the bypass capacitor 201 can be arranged on the array substrate 101 without increasing the frame.

[0064]

According to the first aspect of the present invention, the charge pump circuit can be arranged on the array substrate without arranging a large-capacity capacitor on the array substrate. Not only can it be stabilized, but also the external control circuit can be made compact and low cost.

In the second and third aspects of the present invention,
Since the required output voltage can be obtained regardless of the variation in the threshold value of the TFT, the output voltage from the charge pump circuit can be stabilized without being affected by the manufacturing process of the TFT.

According to the fourth aspect of the present invention, there is no need to dispose the charge pump circuit on the scanning line driving circuit side.
The charge pump circuit can be arranged on the array substrate without increasing the frame.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a liquid crystal display device according to a first embodiment.

FIG. 2 is a circuit configuration diagram of a charge pump circuit shown in FIG.

FIG. 3 is a timing chart showing the operation of the charge pump circuit shown in FIG.

FIG. 4 is a circuit configuration diagram of a charge pump circuit according to a second embodiment.

5 is a timing chart showing the operation of the charge pump circuit shown in FIG.

FIG. 6 is a circuit configuration diagram of a charge pump circuit according to a third embodiment.

FIG. 7 is a circuit configuration diagram showing another configuration example of the charge pump circuit shown in FIG. 6;

FIG. 8 is a circuit configuration diagram showing an application example of the charge pump circuit according to the third embodiment.

FIG. 9 is a circuit configuration diagram of a liquid crystal display device according to a fourth embodiment.

FIG. 10 is a circuit diagram showing another configuration example of the liquid crystal display device according to the fourth embodiment.

[Explanation of symbols]

10, 20, 30, 40, 200 ... charge pump circuit, 11 ... TFT 12 ... pixel electrode, 13 ... auxiliary capacitance, 17, 25, 26 ...
NchTFT 18, 27 ... PchTFT, 36, 38, 46, 47 ...
Diode circuit 101: Array substrate, 102: External control circuit, 103:
Pixel unit 104: scanning line driving circuit, 105: signal line driving circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 612 G09G 3/20 612D 5G435 H01L 27/04 H01L 27/04 B 21/822 (72) Invention Person Hajime Sato 1-9-2, Harara-cho, Fukaya-shi, Saitama Prefecture Inside the Toshiba Fukaya Plant (72) Inventor Takanori Tsunashima 1-9-2, Hara-cho, Fukaya-shi, Saitama Prefecture Inside the Toshiba Fukaya Plant (72 Inventor Yasuyuki Hanazawa 1-9-2 Hara-cho, Fukaya-shi, Saitama Prefecture Inside the Toshiba Fukaya Plant Co., Ltd. (72) Inventor Yasutoshi Hirai 1-9-1-2 Hara-cho, Fukaya City, Saitama Prefecture Toshiba Fukaya Plant Co., Ltd. F term (reference) 2H092 GA59 JA24 NA11 NA25 PA06 2H093 NA16 NC05 NC21 NC71 ND40 ND42 ND54 ND60 5C006 AA16 AF51 BB16 BC20 BF43 BF46 FA42 FA51 5C080 AA10 BB05 D D22 DD27 EE29 FF11 JJ02 JJ03 JJ04 5F038 AV06 BB06 BG05 EZ06 EZ20 5G435 AA00 AA16 AA18 BB12 EE33 EE37 GG21 HH12

Claims (4)

[Claims] 1. A first substrate including a plurality of scanning lines and a plurality of signal lines crossing each other, a switching element disposed at each intersection of these two lines, and a pixel electrode connected to the switching element. A second substrate including a counter electrode facing the pixel electrode, a display panel having a light modulation layer held between the first substrate and the second substrate, and transmitting a data signal to the signal line. A signal line driving circuit for supplying a scanning signal to the scanning line; and an external control circuit for supplying a predetermined signal or potential to the signal line driving circuit and the scanning line driving circuit. In the flat panel display device, a voltage source circuit included in the external control circuit is disposed on the first substrate, and a capacitance between an output unit of the voltage source circuit and a ground and a capacitance of a clock input unit are set as the above. Outside the first substrate Flat display device, characterized in that the location. 2. The voltage source circuit according to claim 1, wherein the first thin film transistor and the second thin film transistor having different polarities are connected in series, and a first input unit for inputting a clock signal through a first capacitor is provided in the first input unit. A second input unit connected to the gate electrodes of the thin film transistor and the second thin film transistor and inputting an inverted clock signal of the clock signal via a second capacitor is provided between the first thin film transistor and the second thin film transistor. The first and second capacitances are arranged outside the first substrate together with a capacitance between an output of the second thin film transistor and a ground. The flat panel display according to claim 1. 3. The voltage source circuit according to claim 1, wherein the first thin film transistor and the second thin film transistor having different polarities are connected in series, and the two thin film transistors are further connected in series as a pair. Item 2. The flat panel display according to item 1. 4. The flat display device according to claim 1, wherein the voltage source circuit is disposed in a region on the first substrate opposite to a region where the scanning line driving circuit is disposed. .