JP2001183702A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that the driving circuit and the interface circuit of a polysilicone TFT liquid crystal display device are complicated because the device requires a negative power supply that provides a gate-off voltage for pixel transistors and a boosting power supply that gives a gate-on voltage to the pixel transistors besides a power supply voltage. SOLUTION: In a liquid crystal display device which utilizes thin film transistors, a driving circuit that is made up with thin film transistors and a DC/DC converter that is made up with an externally mounted capacitive element are manufactured in the same process of the thin film transistors that constitute the device and formed on the same glass substrate. Thus, the converter generates the negative power supply which provides the gate-on voltage for the pixel transistors and the boosting power supply that gives the gate-on voltage of the pixel transistors. Therefore, the driving circuit and the inferface are made simple.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display comprising an integrated circuit using thin film transistors.

[0002]

2. Description of the Related Art FIG. 10 shows an example of a conventional liquid crystal display device constituted by an integrated circuit using thin film transistors.
The thin film transistor 1 is a transistor for driving a pixel of the liquid crystal display device, 2 is a storage capacitance of the pixel, and 3 is a liquid crystal which becomes a capacitive load. The source electrode 4 is a pixel transistor 1
, And the gate electrode 5 is connected to the gate terminal of the pixel transistor 1. The common electrode 6 is an electrode connected to the storage capacitor 2 and the counter electrode of the liquid crystal 3. The source electrode drive circuit 8 drives the source electrode 4,
It is composed of an integrated circuit using thin film transistors, and its power supply voltage is about 10V. The source electrode drive circuit 8 supplies a liquid crystal drive signal based on the image data to the source electrode 4 to drive. The gate electrode drive circuit 9 scans the gate electrode 5 in order, and is constituted by an integrated circuit using thin film transistors. The source electrode drive circuit 8, the gate electrode drive circuit 9, and the pixel transistor 1 are manufactured by the same process for manufacturing a thin film transistor.

In a liquid crystal display device, a control signal and an image data signal 7 are input to a source electrode driving circuit 8 and a gate electrode driving circuit 9. The power supply voltage of the gate electrode drive circuit 9 is a positive power supply 12 and a negative power supply 13 and is supplied from outside the liquid crystal display device. The liquid crystal drive signal is written from the source electrode 4 to the pixel transistor 1 of the selected gate electrode 5 scanned by the gate electrode drive circuit 9 and the gate electrode is scanned in order to display the entire screen.

FIG. 11 is a diagram showing the configuration of one line of the gate electrode driving circuit 9, which is arranged in multiple stages for each gate electrode. D flip-flop 1
02 is used to hold scan data. The Q output of the D flip-flop 102 is connected to the input of the analog switch 101a of the gate electrode drive circuit of the next row and the input of the analog switch 101b of the gate electrode drive circuit of the previous row, forming a bidirectional shift register. It operates to scan the gate electrode. Analog switch 101
a and 101b are used to switch the scanning direction. The buffer circuit 103 has three stages of buffers connected in series, buffers the output of the D flip-flop 102, and the output drives each gate electrode. A positive power supply 12 and a negative power supply 13 are input to the gate electrode drive circuit 9 and are connected to the power supplies of the D flip-flop 102 and the buffer circuit 103.

FIG. 3 is a diagram showing waveforms for driving the liquid crystal display device. Reference numeral 33 denotes a driving waveform of the common electrode. In this example, a constant voltage of 5 V is applied. Reference numeral 32 denotes a source electrode driving waveform, which gives a liquid crystal driving waveform corresponding to the image data to the source electrode 4. Since the liquid crystal needs to be driven by an alternating current, the liquid crystal is driven by inverting the voltage polarity applied to the liquid crystal after scanning one screen. Therefore, the source electrode drive waveform has a voltage amplitude from the minimum voltage 35 to the maximum voltage 37 and is a waveform symmetric with respect to the center voltage. The amplitude of the source electrode drive waveform 32 is determined by the effective voltage value due to the electro-optical characteristics of the liquid crystal.
The maximum voltage 37 of the source electrode drive waveform is about 10V. Therefore, the power supply voltage of the source electrode drive circuit 8 becomes 10V.

The gate electrode drive waveform 31 is a waveform that becomes the gate-on voltage 38 when the gate electrode is selected, and becomes the gate-off voltage 34 when the gate electrode is not selected. The gate-on voltage 38 is set to a voltage obtained by adding a margin to the threshold voltage of the pixel transistor to the maximum voltage 37 of the source electrode drive waveform in order to write the source electrode drive waveform to the pixel transistor 1. Assuming that the threshold voltage of the pixel transistor is about 3 V, the gate-on voltage 38 is 15 V
Set to about. The gate-off voltage 34 is set to a voltage with a small off-leakage in order to hold the source electrode driving waveform in the pixel transistor 1. Since the voltage at which the pixel transistor has less off-leakage is about -3V, the gate-off voltage 34 is set to about -5V. Therefore, the gate electrode driving circuit 9 has +15 V as the positive power source 12 and −
Requires 5V.

[0007]

As described above, in the conventional liquid crystal display device shown in FIG. 10, a power supply of +10 V is used to drive the source electrode drive circuit 8, and a voltage of +15 V is used to drive the gate electrode drive circuit 9. A power supply of 5 V is required, the number of power supplies to be input to the liquid crystal display device is large, and the drive circuit and the interface are complicated.

On the other hand, in the conventional solution, the power supply voltage of the source electrode drive circuit is set to the same as the positive power supply of the gate electrode drive circuit, and the source electrode drive circuit is driven up to 15 V or the gate electrode drive circuit is driven. In order to eliminate the negative power supply, a method of driving by increasing the voltage by 5 V as a whole has been adopted. However, such a method has problems such as an increase in the power supply voltage of the liquid crystal display device and an increase in power consumption, and cannot be said to be a sufficient solution.

The liquid crystal display device of the present invention has been made in order to solve such disadvantages, and has as its object to reduce the number of power supplies input to the liquid crystal display device and to simplify the driving circuit and interface. Another object is to realize low power consumption of the liquid crystal display device.

[0010]

According to a first aspect of the present invention, there is provided a liquid crystal display device using a thin film transistor.
A drive circuit for a source electrode and a gate electrode by a thin film transistor; and D for supplying power to the gate electrode drive circuit.
The C / DC converter is formed on the same glass substrate as the thin film transistors constituting each pixel of the liquid crystal display unit.

According to this configuration, the positive power supply and the negative power supply of the gate electrode drive circuit are generated by the DC / DC converter built in the liquid crystal display device. Therefore, the number of power supplies input to the liquid crystal display device can be reduced, the driving circuit and interface can be simplified, and power consumption can be reduced.

Further, the cost can be reduced by manufacturing the DC / DC converter by the same thin film transistor manufacturing process as the pixel transistor, the source electrode driving circuit, and the gate electrode driving circuit.

According to a second aspect of the present invention, in the liquid crystal display device of the first aspect, the DC / DC converter includes first and second driving transistors connected in series between a power supply and a ground terminal; Third and fourth drive transistors connected in series between the output terminal and the output terminal, a common connection point of the first and second drive transistors, and a common connection point of the third and fourth drive transistors And a control signal generating means for supplying a switching signal to each of the driving transistors, wherein the control signal generating means inputs a driving signal to a driving circuit of the liquid crystal display device. A control signal to be input is input, and a control signal for each driving transistor is generated by dividing the frequency of the control signal.

According to a third aspect of the present invention, in the liquid crystal display device of the first aspect, the DC / DC converter includes a fifth and a sixth driving transistors connected in series between a power supply and an output terminal, and a ground. Seventh and eighth driving transistors connected in series between one end and a power supply end, a common connection point between the fifth and sixth driving transistors, and a common connection point between the seventh and eighth driving transistors. And a control signal generating means for supplying a switching signal to each of the driving transistors, wherein the control signal generating means inputs a control signal to a driving circuit of the liquid crystal display device. A control signal to be input is input, and a control signal for each driving transistor is generated by dividing the frequency of the control signal.

According to a fourth aspect of the present invention, in the liquid crystal display device according to the first aspect, the DC / DC converter includes first and second driving transistors connected in series between a power supply and a ground terminal; Third and fourth drive transistors connected in series between the output terminal and the output terminal, a common connection point of the first and second drive transistors, and a common connection point of the third and fourth drive transistors A negative voltage output unit having a first charge pump capacitor connected between the first and second transistors and first control signal generating means for providing a switching signal to each driving transistor; and a series connection between a power supply and an output terminal. Fifth and sixth driving transistors, seventh and eighth driving transistors connected in series between a ground terminal and a power supply terminal, a common connection point of the fifth and sixth driving transistors, and 7. Eighth drive A second charge pump capacitor connected between the common connection points of the driving transistors, and a boosting output unit having second control signal generating means for supplying a switching signal to each driving transistor. The first and second control signal generating means receives a control signal input to a driving circuit of the liquid crystal display device, and generates a control signal for each driving transistor by dividing the frequency of the control signal. It is a feature.

According to this configuration, there is an effect that a circuit for generating a control signal for the driving transistor of the DC / DC converter by using the liquid crystal control signal can be simply configured.

According to a fifth aspect of the present invention, in the liquid crystal display device of the first aspect, the DC / DC converter includes first and second driving transistors connected in series between a power supply and a ground terminal. A fifth driving transistor connected between the common connection point of the first and second driving transistors and the boosted output terminal, and third and fourth series connected between the ground terminal and the negative voltage output terminal. A driving transistor; a sixth driving transistor connected between a common connection point of the third and fourth driving transistors and a positive electrode terminal; and a common connection point of the first and second driving transistors. A charge pump capacitor connected between a common connection point of the third and fourth driving transistors; and a control signal input to a driving circuit of the liquid crystal display device. Pong It is characterized in that it comprises a control signal generating means for generating a control signal for each of the drive transistor for use with time division capacitor for boosting a for the negative voltage.

According to this configuration, the number of external capacitance elements can be reduced by using one capacitance element in a time-sharing manner for negative voltage and for boosting, and the circuit can be simplified.

According to a sixth aspect of the present invention, in the liquid crystal display device according to any one of the second to fifth aspects, the DC / DC
The control signal generation means of the converter generates a control signal for the driving transistor so as to have a period for turning off all the driving transistors at the same time.

According to this configuration, by providing a period in which the driving transistor is turned off, the through current of the driving transistor can be reduced, and the power consumption of the liquid crystal display device can be reduced.

According to a seventh aspect of the present invention, in the liquid crystal display device according to any one of the first to sixth aspects, the gate electrode driving circuit comprises a shift register section and a driver section,
The power supply of the driver unit is supplied from the DC / DC converter.

According to this configuration, the power of the load circuit, which is the output of the DC / DC converter, can be reduced, and the power consumption of the liquid crystal display device can be reduced.

[0023]

Embodiments of the present invention will be described below. (Embodiment 1) Embodiment 1 of the present invention will be described with reference to FIG. FIG. 1 shows a configuration diagram of a liquid crystal display device according to Embodiment 1 of the present invention. In FIG. 1, the same parts as those in FIG. 10 showing the conventional example are denoted by the same reference numerals, and the description thereof will be omitted. The difference from the conventional example is that the gate electrode driving circuit 9
A and the DC / DC converter 14. The DC / DC converter 14 includes a drive circuit unit and an external capacitor. The thin film transistors of the drive circuit portion are simultaneously manufactured on the same glass substrate by a process of manufacturing the same thin film transistor as the pixel transistor, the source electrode drive circuit 8, and the gate electrode drive circuit 9A of the liquid crystal display portion. As the input signal 15 to the DC / DC converter 14, either a horizontal clock signal for taking in an image signal or a vertical clock signal for scanning a gate electrode is used, like the control signal 7 of the liquid crystal display device. The DC / DC converter 14 operates on the same 10 V power supply as the source electrode drive circuit 8, and outputs the positive power supply 12 and the negative power supply 13 of the gate electrode drive circuit 9 A as outputs.
Is output. The gate electrode driving circuit 9A includes a shift register unit 10 and a driver unit 11. Shift register unit 1
Numeral 0 is operated with the same 10 V power supply as the source electrode drive circuit 8, and the driver unit 11 operates using 15 V, which is the positive power supply output 12 of the DC / DC converter 14, and −5 V, which is the negative power supply output 13, as power supplies. It has a configuration.

FIG. 2 is a diagram showing a configuration of the gate electrode driving circuit 9A according to the first embodiment of the present invention. In FIG. 2, the same portions as those in FIG. 11 showing the conventional example are denoted by the same reference numerals, and description thereof will be omitted. The gate electrode driving circuit 9A according to the first embodiment of the present invention is separated into a shift register section 10 including a D flip-flop 102 and a driver section 11 including a buffer circuit 103. And the shift register unit 1
0 is the same as the power supply of the source electrode drive circuit 8, and +1
The voltage is set to 0 V, and the positive power supply 12 and the negative power supply 13 which are the outputs of the DC / DC converter 14 are used as the power supply of the driver unit 11. The level shifter circuit 110 is used to convert a signal level between the shift register unit 10 and the driver unit 11.

By dividing the power supply of the gate electrode driving circuit 9A into the shift register section 10 and the driver section 11,
The load current of the DC / DC converter 14 can be reduced by the amount corresponding to the shift register circuit, the load on the DC / DC converter 14 can be reduced, and the power consumption of the DC / DC converter and the entire liquid crystal display device can be reduced.

Next, the DC / DC converter 14 will be described with reference to FIGS. FIG. 4 is a configuration diagram of the negative power supply circuit of the DC / DC converter according to Embodiment 1 of the present invention. A horizontal shift clock for capturing an image or a vertical shift clock signal for scanning a gate electrode of the liquid crystal control signal is input to the frequency dividing circuit 401 as an input signal 405. The frequency dividing circuit 401 is an integrated circuit composed of a thin film transistor and is composed of a counter circuit or the like.
7, 408, 409, 410. The level shifter 402 uses the negative voltage output of the DC / DC converter to drive transistor control signals 409 and 410.
And outputs a level-converted drive transistor control signal. The frequency dividing circuit 401 and the level shifter 402 constitute first control signal generating means for supplying a switching signal to each driving transistor.

The first to fourth driving transistors MN1,
MN2, MN3 and MN4 are composed of n-channel thin film transistors. First and second driving transistors MN
1, MN2 are connected in series between the power input terminal 406 and the ground terminal, and the third and fourth driving transistors MN3, MN2
4 is connected in series between the ground terminal and the output terminal 415.
These common connection terminals have a charge pump capacitor 40
3 is connected, and a smoothing capacitor 404 is connected between the output terminal 415 and the ground terminal. The charge pump capacitor 403 and the output smoothing capacitor 404 are external capacitors such as ceramic capacitors. It is assumed that a voltage of +5 V is input to the power input terminal 406 from the outside of the liquid crystal display device as an input voltage.

FIG. 5 shows a DC / DC converter 14 according to the present invention.
FIG. 2 is a configuration diagram of a booster circuit of FIG. A horizontal shift clock for capturing an image or a vertical shift clock signal for scanning a gate electrode of the liquid crystal control signal is input to the frequency dividing circuit 501 as an input signal 505. The frequency dividing circuit 501 is an integrated circuit composed of a thin film transistor, and is composed of a counter circuit or the like. The frequency dividing circuit 501 divides the frequency of the input signal 505 and generates a control signal 50
8, 509, 510, and 511.

The fifth and seventh driving transistors MN5,
MN7 is an n-channel thin film transistor, and the sixth and eighth driving transistors MP6 and MP8 are p-channel thin film transistors. The fifth and sixth driving transistors MN5 and MP6 are connected in series between the power input terminal 506 and the boost output terminal 507, and the seventh and eighth driving transistors MN7 and MP8 are connected to the ground terminal and the power input terminal 513. Connected in series. A charge pump capacitor 503 is connected to these common connection terminals, and a smoothing capacitor 504 is connected between the output terminal 507 and the ground terminal. The charge pump capacitor 503 and the output smoothing capacitor 504 are external capacitors such as ceramic capacitors. Power input terminal 506
It is assumed that + 5V and + 10V are input from 513 to the outside of the liquid crystal display device. The level shifter 502 converts the level of the driving transistor control signal 509 using the boosted voltage output 507 of the DC / DC converter, and outputs the level-converted control signal to the driving transistor MP6. Frequency dividing circuit 50
1, the level shift 502 constitutes a second control signal generating means for supplying a switching signal to each driving transistor.

Next, the operation of the DC / DC converter will be described with reference to FIGS. FIG. 6 shows a signal waveform of the negative power supply circuit of the DC / DC converter 14 shown in FIG. 6A shows an input signal 405, FIG. 6B shows a control signal for the driving transistors MN1 and MN2, and FIG. 6C shows a control signal for the driving transistors MN3 and MN4.
The solid line a in FIG.
, A broken line b shows a negative electrode voltage waveform of the charge pump capacitor 403, and FIG. 6E shows a negative voltage output waveform from the DC / DC converter.

The input signal 405 is frequency-divided by the frequency dividing circuit 401, and the control signals 407 and 409 of the driving transistors MN1 and MN3, the control signals 408 and 408 of the MN2 and MN4,
Generate 410. Driving transistors MN1, MN
Since MN3 and MN4 are n-channel transistors, they turn on when the control signal is at a high level and turn off when the control signal is at a low level.

In FIG. 6, first, the driving transistors MN1 and MN3 are turned on, and the charge pump capacitor 4
The positive electrode of 03 is charged to 5V, and the negative electrode is charged to 0V. At this time, the driving transistors MN2 and MN4 are off.

Next, the driving transistors MN1 and MN3
Is turned off, and all the driving transistors MN1 to MN4
Are turned off once. This is MN1, MN2, MN3
When MN4 and MN4 switch at the same time, they are both turned on at the moment of switching, so that they serve to prevent a through current from flowing.

Next, the driving transistors MN2 and MN4
Is turned on, the + electrode of the charge pump capacitor 403 is connected to 0 V,
The negative electrode is connected to the negative voltage output terminal 415 to supply electric charge to the smoothing capacitor 404, and the negative electrode is connected to the negative voltage output terminal 41.
5 outputs -5V. Thereafter, the same operation is repeated as shown.

FIG. 7 shows signal waveforms of the boost power supply circuit of the DC / DC converter shown in FIG. 7A shows the input signal 505, and FIG. 7B shows the driving transistors MN5 and MN.
7 (c) are the control signals 509 and 511 of the driving transistors MP6 and MP8, and the solid line a in FIG. 7 (d) is the positive electrode voltage waveform of the charge pump capacitor 503, and the broken line b FIG. 7E shows a negative electrode voltage waveform of the charge pump capacitor 503, and FIG.
The boosted voltage output waveforms of the C converter are shown respectively.

The frequency dividing circuit 501 divides the frequency of the input signal 505 and generates control signals for the driving transistors MN5, MP6, MN7 and MP8 as shown in FIGS. 7 (b) and 7 (c). Since the driving transistors MN5 and MN6 are n-channel transistors, they are turned on when the control signal is at a high level and turned off when the control signal is at a low level. Since the driving transistors MP1 and MP2 are p-channel transistors, they are turned on when the control signal is at a low level and turned off when the control signal is at a high level.

In FIG. 7, first, the driving transistor M
When P6 and MP8 are off, the driving transistor MN5
And MN7 are turned on, and the charge pump capacitor 503 is turned on.
+ Electrode is charged to 5V, and-electrode is charged to 0V.

Next, the driving transistors MN5, MN
6, MP7 and MP8 are all turned off. This is MN5
And MN7, and MP6 and MP8 are simultaneously turned on when they are simultaneously switched, so that they serve to prevent a through current from flowing.

Next, the driving transistors MP6 and MP8
Is turned on, the charge pump capacitor 503
The electrode is connected to 10 V of the power input terminal 513, and the + electrode of the charge pump capacitor 503 is connected to the boost output terminal 50.
7, the electric charge is supplied to the smoothing capacitor 504, and 15 V is output to the boosted output terminal 507. Thereafter, the same operation is repeated as shown.

As described above, in the liquid crystal display device of the present invention, the DC / DC converter including the driving circuit using the thin film transistor and the external capacitive element is formed on the same glass substrate by the same process as the thin film transistor constituting the liquid crystal display device. Due to the manufacture, the positive and negative power supplies for the gate electrode drive circuit are generated internally in the liquid crystal display device, reducing the number of power supplies input to the liquid crystal display device, simplifying the drive circuit and interface and reducing power consumption. can do. Further, since the DC / DC converter is manufactured at the same time as the thin film transistor manufacturing process, the cost can be reduced.

(Embodiment 2) Embodiment 2 of the present invention will be described with reference to FIGS. The liquid crystal display device according to the second embodiment of the present invention is almost the same as that of the first embodiment of the present invention, and the same portions are denoted by the same reference characters and will not be described in detail. FIG. 1 shows a second embodiment of the present invention.
Is a DC / DC converter 16 that outputs positive and negative voltages
Is used.

FIG. 8 shows a DC in Embodiment 2 of the present invention.
FIG. 3 is a diagram showing a configuration of a / DC converter 16. As the input signal 806, either a horizontal shift clock for capturing an image or a vertical shift clock signal for scanning a gate electrode among the liquid crystal control signals is used.
Is input to The frequency dividing circuit 801 is an integrated circuit composed of a thin film transistor, and is composed of a counter circuit or the like. The frequency dividing circuit 801 divides the input signal 806 to control the control signals 811 to 8 of the first to sixth driving transistors MN1 to MN4, MP5 and MP6.
Generate 16.

Driving transistors MN1, MN2, MN
3, MN4 is an n-channel thin film transistor,
The driving transistors MP5 and MP6 are p-channel thin film transistors. Charge pump capacitor 80
3. The smoothing capacitors 804 and 805 are externally mounted capacitors, such as ceramic capacitors.
The smoothing capacitors 804 and 805 serve to smooth the negative power supply output and the boosted power supply output, respectively.

The voltage input terminals 807 and 809 respectively have +5
It is assumed that a voltage of V, +10 V is input from outside the liquid crystal display device. The level shifter 802 uses the negative voltage of the negative power supply output terminal 810 of the DC / DC converter to convert the levels of the driving transistor control signals 814 and 815, and outputs the level to the driving transistors MN3 and MN4. The level shifter 819 uses the output of the boosted power supply output terminal 808 of the DC / DC converter to control the driving transistor control signal 8.
15 is level-converted and output to the driving transistor MP5. The frequency dividing circuit 801 and the level shifters 802 and 819 constitute control signal generating means for supplying a switching signal to each driving transistor.

FIG. 9 shows signal waveforms of the negative power supply circuit of the DC / DC converter. FIG. 9A shows an input signal, and FIG.
9B shows control signals 811 and 812 for the driving transistors MN1 and MN2, and FIG. 9C shows the driving transistor MN.
3D, control signals 813 and 814 of MN4, and FIG. 9D shows control signals 815 and 8 of drive transistors MP5 and MP6.
16 is shown. In FIG. 9E, a solid line a indicates a positive electrode voltage waveform of the charge pump capacitor 803, a broken line b indicates a negative electrode voltage waveform of the charge pump capacitor 803, and FIG.
In (f), a solid line c shows a DC / DC converter negative power supply output voltage waveform, and a solid line d shows a boosted power supply output waveform of the DC / DC converter.

Driving transistors MN1, MN2, MN
3 and MN4, which are n-channel transistors, turn on when the control signal is at a high level and turn off when the control signal is at a low level. The driving transistors MP5 and MP6 are p
Since it is a channel transistor, it turns on when the control signal is at low level and turns off when it is at high level.

As shown in FIGS. 9A and 9B, the input signal 806 is frequency-divided by the frequency dividing circuit 801. First, the driving transistors MN1 and MN3 are turned on, and the positive electrode of the charge pump capacitor 803 is set to 5V. -Charge the electrodes to 0V. At this time, the driving transistors MN3, MN4, M
P5 and MP6 are off.

Next, the driving transistors MN1 and MN
2, MN3, MN4, MP5 and MP6 are all turned off. This is because MN1, MN2, and MP5, and MN3, MN4, and MP6 are switched at the same time, and when both switches are turned on at the moment of switching, a through current flows.

Next, as shown in FIG. 9C, when the driving transistors MN2 and MN4 are turned on, the positive electrode of the charge pump capacitor 803 is connected to 0 V, and the negative electrode is connected to the negative voltage output terminal 810, and To the negative capacitor 805, and to the negative voltage output terminal 810,
5V is output. At this time, the driving transistor MP
5, MP6 is off.

Next, as shown in FIG. 9D, the driving transistors MN1 and MN3 are turned on, and the positive electrode of the charge pump capacitor 803 is charged to 5V and the negative electrode is charged to 0V. At this time, the driving transistors MN2, MN4, MP
5, MP6 is off.

Next, the driving transistors MN1 and MN
2, MN3, MN4, MP5 and MP6 are all turned off. This is because MN1, MN2, and MP5, and MN3, MN4, and MP6 are switched at the same time, and when both switches are turned on at the moment of switching, a through current flows.

Next, as shown in FIG. 9D, when the driving transistors MP5 and MP6 are turned on, the minus electrode of the charge pump capacitor 803 is connected to 10 V, and the plus electrode of the charge pump capacitor 813 is connected to the boosted power supply output terminal. 808, supplies electric charge to the smoothing capacitor 804, and outputs 15 V to the negative voltage output terminal 808. At this time, the driving transistors MN1 to MN4 are off.

As described above, in the DC / DC converter used in the liquid crystal display device of the present invention, the charge pump capacitor 803 is used in a time-sharing manner for the negative power supply and the boost power supply, so that one capacitor can be used for the negative power supply. And boost power supply, without increasing the circuit scale of the DC / DC converter.
Could be realized.

[0054]

As described above, the driving circuit comprising the thin-film transistor of the present invention and the DC / D comprising the external capacitance element are provided.
By using a C converter to internally generate a negative power supply for providing a gate-off voltage of the pixel transistor and a power supply for providing an on-voltage of the gate of the pixel transistor, the driving circuit and interface of the liquid crystal display device can be simplified.

Further, by manufacturing the DC / DC converter of the present invention in the same process as the thin film transistor constituting the liquid crystal display device, a liquid crystal display device having a built-in DC / DC converter could be easily realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a liquid crystal display device according to Embodiments 1 and 2 of the present invention.

FIG. 2 is a configuration diagram of a part of a gate electrode driving circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing waveforms of driving of the liquid crystal display device.

FIG. 4 is a configuration diagram of a negative power supply circuit of the DC / DC converter according to the first embodiment of the present invention.

FIG. 5 is a configuration diagram of a boost power supply circuit of the DC / DC converter according to the first embodiment of the present invention.

FIG. 6 is a diagram showing signal waveforms of a negative power supply circuit of the DC / DC converter according to the first embodiment of the present invention.

FIG. 7 is a diagram showing signal waveforms of a boost power supply circuit of the DC / DC converter according to the first embodiment of the present invention.

FIG. 8 is a configuration diagram of a DC / DC converter according to a second embodiment of the present invention.

FIG. 9 is a diagram showing signal waveforms of a DC / DC converter according to Embodiment 2 of the present invention.

FIG. 10 is a configuration diagram of a conventional liquid crystal display device.

FIG. 11 is a configuration diagram of a vertical drive circuit in a conventional liquid crystal display device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Pixel drive transistor 2 Storage capacitor 3 Liquid crystal 4 Source electrode 5 Gate electrode 6 Common electrode 7 Input control signal 8 Source electrode drive circuit 9, 9A Gate electrode drive circuit 10 Shift register part of gate electrode drive circuit 11 Gate electrode drive circuit Driver section 12 Positive power supply for gate electrode drive circuit 13 Negative power supply for gate electrode drive circuit 14, 16 DC / DC converter 15 Input signal 31 Gate electrode drive waveform 32 Source electrode drive waveform 33 Common electrode drive waveform 34 Gate off voltage 35 Source electrode drive Minimum voltage of waveform 36 Applied voltage of common electrode 37 Maximum voltage of source electrode drive waveform 38 Gate-on voltage 101a, 101b Analog switch 102 D flip-flop 103 Buffer circuit 110 Level shifter 401 Divider circuit 402 Level shifter 403 Charge pump capacitor 404 Smoothing capacitor 405 Input signal 406 Voltage input terminal 407, 408, 409, 410 Driving transistor control signal 415 DC / DC converter negative power supply output terminal 501 Divider circuit 502 Level shifter 503 Charge pump capacitor 504 Smoothing capacitor 505 Input signal 506 Voltage input terminal 507 Boost output terminal 508, 509, 510, 511 Driving transistor control signal 801 Frequency divider 802, 819 Level shifter 803 Charge pump capacitor 804, 805 Smoothing capacitor 806 Input signal 807, 809 Voltage input terminal 808 Boost output terminal 810 Negative voltage output terminal 811 to 816 Driving transistor control signal

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H092 GA59 JA24 KA04 KA07 MA58 NA25 NA28 NA30 PA06 2H093 NA16 NA80 NC05 NC22 NC23 NC25 NC26 NC90 ND44 ND49 ND50 ND54 ND58 NE07 NE10 5C006 AC02 AF84 BB16 BC03 BC06 BF13 BF06 BF22 BF34 BF37 BF46 BF49 FA43 FA45 FA47 5C080 AA10 BB05 DD22 DD26 FF03 FF09 JJ02 JJ03 JJ04

Claims (7)

[Claims] In a liquid crystal display device using a thin film transistor, a driving circuit for a source electrode and a gate electrode by the thin film transistor and a power supply for supplying power to the gate electrode driving circuit are provided.
A liquid crystal display device wherein a C / DC converter and a thin film transistor constituting each pixel of a liquid crystal display portion are formed on the same glass substrate. 2. The DC / DC converter comprises first and second driving transistors connected in series between a power supply and a ground terminal, and third and fourth drive transistors connected in series between a ground terminal and an output terminal. A driving transistor; a first charge pump capacitor connected between a common connection point of the first and second driving transistors and a common connection point of the third and fourth driving transistors; Control signal generating means for providing a switching signal to the transistor for use, wherein the control signal generating means receives a control signal input to a drive circuit of the liquid crystal display device and divides the control signal by dividing the signal. 2. The liquid crystal display device according to claim 1, wherein a control signal for each driving transistor is generated. 3. The DC / DC converter comprises: a fifth and a sixth drive transistors connected in series between a power supply and an output terminal; and a seventh and eighth drive transistors connected in series between a ground terminal and a power supply terminal. A driving transistor; a second charge pump capacitor connected between a common connection point of the fifth and sixth driving transistors and a common connection point of the seventh and eighth driving transistors; Control signal generating means for providing a switching signal to the transistor for use, wherein the control signal generating means receives a control signal input to a drive circuit of the liquid crystal display device and divides the control signal by dividing the signal. 2. The liquid crystal display device according to claim 1, wherein a control signal for each driving transistor is generated. 4. The DC / DC converter comprises: first and second drive transistors connected in series between a power supply and a ground terminal; and third and fourth drive transistors connected in series between a ground terminal and an output terminal. A driving transistor; a first charge pump capacitor connected between a common connection point of the first and second driving transistors and a common connection point of the third and fourth driving transistors; First control signal generating means for providing a switching signal to the transistor for use,
A negative voltage output unit having: a fifth and a sixth driving transistors connected in series between a power supply and an output terminal; a seventh and an eighth driving transistor connected in series between a ground terminal and a power supply terminal; A second charge pump capacitor connected between a common connection point of the fifth and sixth driving transistors and a common connection point of the seventh and eighth driving transistors, and switching to each driving transistor. Second control signal generating means for providing a signal;
Wherein the first and second control signal generating means receive a control signal input to a drive circuit of the liquid crystal display device, and divide the signal by dividing the control signal. 2. The liquid crystal display device according to claim 1, wherein a control signal for each driving transistor is generated. 5. The DC / DC converter comprises: a first and a second driving transistor connected in series between a power supply and a ground terminal; a common connection point between the first and the second driving transistor; A fifth driving transistor connected between the terminals; a third and a fourth transistor connected in series between the ground terminal and the negative voltage output terminal.
A driving transistor, a sixth driving transistor connected between a common connection point of the third and fourth driving transistors and a positive electrode end, and a common connection of the first and second driving transistors. A charge pump capacitor connected between the common connection point of the third driving transistor and the third and fourth driving transistors; and a control signal input to a driving circuit of the liquid crystal display device. 2. A control signal generating means for generating a control signal for each driving transistor such that a charge pump capacitor is used in a time-division manner for a negative voltage and for a boost.
The liquid crystal display device as described in the above. 6. The control signal generating means of the DC / DC converter generates a control signal of the driving transistor so as to have a period during which all of the driving transistors are turned off at the same time. Item 6. The liquid crystal display device according to any one of items 2 to 5. 7. The gate electrode drive circuit according to claim 1, wherein the gate electrode drive circuit includes a shift register unit and a driver unit, and supplies power to the driver unit from the DC / DC converter. The liquid crystal display device as described in the above.