JP2001056662A - Flat display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a drive load and to reduce power consumption at a drive time by short-circuiting between counter electrodes in a blanking period between a formed prescribed scanning period and a next prescribed scanning period and shifting the potential of the counter electrodes to middle potential. SOLUTION: In a first horizontal scanning period, respective switches of a common control circuit are set in a conductive state as figure (a) by a control signal. In this period, a common potential (-) is supplied to one side counter electrode through an output terminal 44, and a common potential (+) is supplied to the other counter electrode through the output terminal 45. When it becomes the blanking period, the switches 41, 42 of the common control circuit are set in the conductive state as figure (b) by the control signal. In this period, since the switch 41 is closed, and the switch 42 is opened, the place between the counter electrodes becomes a short circuit state, and the charges are re-distributed between two counter electrodes. Thus, the potential of one side counter electrode side is shifted to a negative side, and the potential of the other counter electrode side is shifted to a positive side, and each potential become middle potential between the common potential (+) and the common potential (-).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat display device, for example, to an active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art Among flat display devices, a liquid crystal display device using a liquid crystal layer as a light modulating layer has been used in a wide range of fields by utilizing the characteristics of light weight, thinness, and low power consumption.
In particular, an active matrix type liquid crystal display device provided with a switch element for each pixel is rapidly spreading as a display device of OA equipment such as a PC (personal computer).

In the conventional active matrix type liquid crystal display device, the array substrate is made of amorphous silicon (a-
Si) Most of them consisted of TFT, but recently,
Devices composed of polysilicon (p-Si) TFTs are increasing. The p-SiTFT has an advantage that the electron mobility is higher than that of the a-SiTFT, the size of the TFT can be reduced, and a part of the driving circuit can be integrally built in an empty area on the substrate. Thus, for example, data from a control IC formed on an external drive circuit board (PCB) is input to a shift register formed on a glass substrate via a bus line, and serial-to-parallel converted by the shift register. It becomes possible to transmit to the line.

In a general liquid crystal display device, the polarity of a potential difference applied between a pixel and a counter electrode of a liquid crystal panel is inverted for each frame in order to prevent deterioration of characteristics of a liquid crystal layer. As a polarity inversion drive method that further reduces the occurrence of flicker, for example, a V (vertical) line inversion drive method in which the polarity is inverted for each adjacent vertical pixel line (for each column) for each frame, or for each frame An H / V (horizontal / vertical) line inversion driving method in which the polarity is inverted for each pixel adjacent to the pixel is known.

When the black line is written on the entire surface, for example, if the potential of the common electrode is 5 V, and if one of the signal lines is written with 9 V, the adjacent signal lines are It is necessary to write 1V. In this case, the signal line driving circuit has 5 to 9 V and 5 to 1 V.
Two ICs for writing V signals or one IC for writing 1 to 9 V signals are required, resulting in an increase in cost and mounting area. However, the V-line inversion driving method is often used in a liquid crystal display device composed of p-Si TFTs because of the advantage that power consumption can be suppressed because the potential of the common electrode can be fixed.

[0006]

As a method for solving the above-mentioned drawbacks of the V-line inversion driving method, there is an H-common inversion driving method in which the polarity of the signal line is inverted every horizontal scanning period and the potential of the common electrode is simultaneously changed. . In this H common inversion driving method,
For example, when writing black on the entire surface, if the potential of a pixel electrode on one horizontal line is 5 V, the potential of the counter electrode is 1 V, and if the potential of the pixel electrode on the next horizontal line is 1 V,
The counter electrode potential is 5V. In this case, only one IC for writing a signal of 1 to 5 V needs to be arranged.

However, in this H common inversion driving method, it is necessary to charge the counter electrode potential to increase from 1 V to 5 V every one horizontal scanning period and discharge the charge to decrease the counter electrode potential from 5 V to 1 V. Therefore, there is a problem that power consumption is increased as compared with the V-line inversion driving method, and a driving circuit having a sufficient driving capability for driving the counter electrode is required.

It is an object of the present invention to provide a flat display device capable of reducing power consumption during driving.

[0009]

In order to achieve the above object, the present invention is directed to a method for controlling the vicinity of each intersection between a plurality of scanning lines crossing each other and a plurality of signal lines divided into at least two sets. A pixel electrode connected via a switch element to at least two counter electrodes set to a common potential, and a display panel in which display pixels including a light modulation layer interposed between these electrodes are arranged in a matrix, A scanning line driving circuit for supplying a scanning signal to the scanning line; a signal line driving circuit for supplying a video signal of a different polarity to each set of the signal lines for each predetermined scanning period; A common control circuit that supplies a common potential having a different polarity for each scanning period, and short-circuits the counter electrodes during a blanking period between the preceding predetermined scanning period and the next predetermined scanning period. To.

According to the above configuration, the counter electrodes are short-circuited during the blanking period between the previous predetermined scanning period and the next predetermined scanning period. Is shifted to the negative side, and the potential of the counter electrode to which the negative common potential is applied in the previous predetermined scanning period shifts to the positive side, and becomes an intermediate potential between the positive / negative common potential. . Therefore, in the next predetermined scanning period, since the potential of each counter electrode has already shifted to the intermediate potential, the predetermined potential can be obtained by charging and discharging about half of the conventional case.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the flat display device according to the present invention is applied to a liquid crystal display device will be described below.

In this embodiment, a liquid crystal display device having an active matrix type liquid crystal panel in which a driving circuit is integrally formed on a glass substrate by using a p-Si TFT will be described.

In this embodiment, the common potential refers to a potential supplied from the outside to the counter electrode, and the counter electrode potential refers to a potential actually applied to the counter electrode. Within one horizontal scanning period, the counter electrode potential = the common potential holds.

FIG. 2 is a circuit diagram of a liquid crystal panel.
(A) is a circuit configuration diagram of an array substrate on which a drive circuit is formed, and (b) is a circuit configuration diagram of a counter substrate on which a counter electrode is formed. FIG. 2 does not show wirings until video signals, control signals, and the like are input from a PC main body (not shown). Illustration of other circuit relationships is also omitted.

The array substrate 10 includes an active matrix (AM) unit 1 forming an effective display area, a scanning line driving circuit 2 for driving the active matrix unit 1, signal line driving circuits 3a and 3b, and a common control circuit. 4 are integrally formed.

The active matrix section 1 is configured such that pixel electrodes 6 constituting a plurality of liquid crystal pixels 5 are arranged in a matrix. Each liquid crystal pixel 5 includes a pixel electrode 6, a counter electrode 21 or 22, and a liquid crystal layer 7 held between these electrodes. The supply of the video signal to each pixel electrode 6 is controlled by a TFT 8 as a switch element. The gate of each TFT 8 is commonly connected to the scanning lines G1, G2... Gn for each row, and the drain is connected to the signal lines D1, D2.
The source of the TFT 8 is connected to the pixel electrode 6. In this embodiment, the active matrix section 1 includes a region 11 including the signal lines D1, D2,.
, And a region 12 including signal lines Dm + 1, Dm + 2,..., Dm + m.

The scanning line driving circuit 2 is composed of a circuit including a shift register and a buffer (not shown). The scanning line driving circuit 2 scans each of the scanning lines G1, G2,... G based on the vertical synchronizing signal STV and the vertical clock signal CKV.
n to supply a scanning signal.

The signal line driving circuits 3a and 3b convert analog video signals input from outside into signal lines D1, D2.
Dm, Dm + 1, Dm + 2,..., Dm + m, and a sample / hold circuit (not shown), and a shift register (not shown) for controlling the operation timing of the sample / hold circuit. A horizontal start signal STH, a horizontal clock signal CKH, and an analog video signal are supplied to each signal line drive circuit.

From the signal line driving circuits 3a and 3b, video signals having different polarities are supplied for each horizontal scanning period. For example, in one horizontal scanning period, a video signal having a positive polarity with respect to a reference voltage is supplied from the signal line driving circuit 3a to the signal lines D1, D2,.
, Dm + 1, Dm + 2,..., Dm + m are supplied with video signals of negative polarity with respect to the reference voltage. In the next one horizontal scanning period, the signal line driving circuit 3a outputs the signal lines D1,
Dm are supplied with a video signal of negative polarity with respect to the reference voltage, and the signal lines Dm + 1, Dm + 1,
Dm + m are supplied with a video signal having a positive polarity with respect to the reference voltage.

In this embodiment, the two signal line drive circuits 3a and 3b output video signals having different polarities every one horizontal scanning period. Dm + m may be output to the lines D1, D2... Dm and the signal lines Dm + 1, Dm + 2.

On the other hand, on the opposing substrate 20, an electrically divided opposing electrode 2 made of a transparent conductive film such as ITO is used.
1 and 22 are formed. These counter electrodes 21 and 2
Reference numeral 2 corresponds to each of the divided regions 11 and 12 of the active matrix unit 1 and is connected to the common control circuit 4 on the array substrate 10 via a transfer (not shown).

The liquid crystal panel configured as described above is connected to a drive circuit board (PCB) (not shown) via a flexible wiring board (FPC). The drive circuit board includes a power supply circuit, a D / A converter circuit, a control IC, and the like. The drive circuit board receives a synchronization signal including a reference clock signal from a PC main body (not shown), a digital video signal, and the like, and sends an analog video signal to a liquid crystal panel. And control signals.

Next, the circuit configuration and operation of the common control circuit 4 will be described.

FIG. 1 is a circuit diagram of the common control circuit 4. The common control circuit 4 includes switches 41, 42 and 4
3 as a combinational circuit. Switch 4
Switching of the switch 1 and the switch 42 is controlled by a control signal a supplied from a control IC (not shown), and switching of the switch 43 is controlled by a control signal b supplied from a control IC (not shown). By switching the switch 43 every horizontal scanning period, positive (+) or negative (−) common potential with respect to the reference voltage from the output terminals 44 and 45 to the counter electrodes 21 and 22 alternates every horizontal scanning period. Supplied to Incidentally, in the state of FIG. 1, the common potential (−) is supplied to the output terminal 44 (the counter electrode 21 side), and the common potential (+) is supplied to the output terminal 45 (the counter electrode 22 side).

Here, (+) at the common potential,
The polarity of (−) does not mean a positive polarity or a negative polarity with respect to the ground potential, but is relatively determined such that one is a positive potential and the other is a negative potential with respect to a certain reference potential. Things.

Next, the operation when black data is written on the entire surface of the liquid crystal panel will be described with reference to FIG. In this example, it is driven by the H common inversion driving method.

When the scanning line G1 is selected by the scanning line driving circuit 2 and the gates of all the TFTs 8 on this one horizontal line are opened, the signal lines D1 and D2 from the signal line driving circuit 3a.
.. A video signal of 5 V is applied to the pixel electrode 6 via Dm. At this time, each switch of the common control circuit 4 is set to the state shown in FIG. 1 by control signals a and b from a control IC (not shown), and the common potential (−) is supplied to the counter electrode 21. Here, the common potential (-) is set to 1 V
Then, a potential difference of 4 V between 5 V of the pixel electrode 6 and 1 V of the common potential (−) is applied to the liquid crystal layer 7. Thereby, in the scanning line G1, the signal lines D1, D2,.
Black is written to the liquid crystal pixel 5 connected to.

On the other hand, when the gates of all the TFTs 8 on one horizontal line of the scanning line G1 are opened at the same timing, the signal lines Dm + 1, Dm + 2,.
A video signal of 1 V is applied to the pixel electrode 6 via Dm + m. At this time, the common potential (+) is supplied to the counter electrode 22. Here, assuming that the common potential (+) is 5 V,
The liquid crystal layer 7 has 1 V of the pixel electrode 6 and 5 of the common potential (+).
A potential difference of 4 V from V is applied. Thereby, in the scanning line G1, the signal lines Dm + 1, Dm + 2 ·
Black is written in the liquid crystal pixel 5 connected to Dm + m.

In this manner, black is written to all the liquid crystal pixels 5 on one horizontal line of the scanning line G1.

In the next one horizontal scanning period, the switch 43 of the common control circuit 4 is controlled by a control IC (not shown).
1 is set to a phase opposite to that in FIG. 1, and 5 V of the common potential (+) is supplied to the counter electrode 21 and 1 V of the common potential (-) is supplied to the counter electrode 22. The signal line driving circuit 3a outputs a signal line D1,
Dm via D2... Dm, and signal lines Dm + 1, Dm + 2.
A video signal of 1 V is applied to each pixel electrode 6 via m + m. Accordingly, black is written to all the liquid crystal pixels 5 on one horizontal line of the scanning line G2 by applying the potential difference of 4V.

Thereafter, the same operation is repeated every horizontal scanning period, so that black is written on the entire surface of the liquid crystal panel in one frame period.

Next, the operation of the blanking period between the above-described writing to each horizontal line will be described.

FIG. 3 is a timing chart showing the relationship between the control signal and the potential of the common electrode. In addition, FIG.
(C) is a circuit configuration diagram showing a conduction state of each switch in the common control circuit 4 for each period, and (a) to (c) of FIG.
(C) corresponds to the first horizontal scanning period, the blanking period, and the second horizontal scanning period in FIG.

In the first horizontal scanning period, each switch of the common control circuit 4 is set to a conductive state as shown in FIG. 4A by the control signals a and b. In this period, the counter electrode 21
Is supplied with a common potential (−) through an output terminal 44, and the common electrode (+) is supplied to the counter electrode 22 through an output terminal 45.

Next, in the blanking period, the switches 41 and 42 of the common control circuit 4 are set to the conductive state as shown in FIG. 4B by the control signal a. In this period, the switch 41 is closed and the switch 42 is opened, so that the counter electrodes 21 and 22 are in a short-circuit state, and the charge is redistributed between the two counter electrodes. As a result, the counter electrode 21
The potential on the side shifts to the negative side, and the potential on the counter electrode 22 shifts to the positive side, and each becomes an intermediate potential between the common potential (+) and the common potential (−).

Next, in the second horizontal scanning period, the switches of the common control circuit 4 are controlled by the control signals a and b as shown in FIG.
The conduction state is set as shown in FIG. During this period,
Since the switch 43 is set in a phase opposite to that of the first horizontal scanning period, the common potential (+) is supplied to the counter electrode 21 through the output terminal 44 and the common potential (−) is supplied to the counter electrode 22 through the output terminal 45. Will be. Here, the counter electrode 2
Since the potential of 1 has already been shifted to the intermediate potential, it reaches a predetermined potential (1 V in this case) by about half of the conventional discharge. In addition, since the potential of the counter electrode 22 has already shifted to the intermediate potential, it reaches a predetermined potential (5 V in this case) by charging about half of the related art.

As described above, in the liquid crystal panel of the present embodiment, the opposing electrodes are short-circuited during the blanking period between one horizontal scanning period and the next one horizontal scanning period. In order to lower the potential of the counter electrode 22 from 5 V to 1 V, it is sufficient to discharge a charge corresponding to about 2 V. To raise the potential of the counter electrode 22 from 1 V to 5 V, about 2 V
In other words, it is only necessary to charge the electric charge for minutes. That is, the charge / discharge of the electric charge is about half as compared with the case where the counter electrode potential is charged / discharged between 1 and 5 V, so that the power consumption can be reduced to about half as compared with the normal H common inversion driving method. it can.

FIG. 5 shows another embodiment of the liquid crystal panel, and is a circuit diagram of an array substrate on which a drive circuit is formed. In FIG. 5, the same parts as those in FIG. 2A are indicated by the same reference numerals.

In the circuit configuration as shown in FIG. 2, the active matrix section 1 is driven by the two signal line driving circuits 3a and 3b, and writing is performed on the two regions with different polarities. A large difference occurs in the parasitic capacitance between the pixel and another pixel. This allows
A gradation difference appears between the boundary portion and another portion, and a cut may be recognized at the center of the screen.

The active matrix section 1 of this embodiment
No. 00 solves the above problem by devising the arrangement of the liquid crystal pixels and adding a signal line for coupling compensation.

The active matrix section 100 shown in FIG.
In this embodiment, the active matrix (AM) unit 100 is divided into two regions 101 and 102, and the arrangement of the liquid crystal pixels and the signal lines is changed, as in the previous embodiment. That is, in the region 101, the liquid crystal pixels 5
Are arranged to the left of the liquid crystal pixel 5 in the region 102. As a result, the relationship between the liquid crystal pixels and the signal lines becomes symmetric with respect to the boundary between the regions. Further, a coupling compensation signal line 103 is arranged between the regions 101 and 102. The coupling compensation signal line 103 is connected to the signal line drive circuit 3a, and an intermediate potential of the video signal is applied.

According to the above configuration, since the parasitic capacitance is generated between the coupling compensation signal line 103 and the adjacent pixel, the difference in the parasitic capacitance generated between the boundary portion and another pixel becomes gentle. In addition, the gradation difference between pixels at the boundary is reduced. For this reason, the difference in gradation at the boundary portion is less conspicuous than in the related art, and a high-quality image can be obtained.

[0043]

As described above, in the flat panel display according to the present invention, the opposing electrodes are short-circuited during the blanking period between the first and second predetermined scanning periods, and the potential of the opposing electrodes is reduced. Is shifted to the intermediate potential, so that a predetermined potential can be obtained by charging and discharging about half as compared with the related art, the driving load is reduced, and the power consumption during driving can be reduced. .

In particular, when the arrangement of the pixel electrodes, the switching elements, and the signal lines of the display panel is symmetrical and the signal line for coupling compensation is arranged at the center of the display panel, the boundary between the center of the panel and the other parts is removed. The difference in parasitic capacitance between the pixel and the pixel becomes gradual, and the difference in gradation between the pixels at the boundary is reduced. Image can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a common control circuit.

FIG. 2 is a circuit diagram of a liquid crystal panel.

FIG. 3 is a timing chart showing a relationship between a control signal and a common potential.

FIG. 4 is a circuit diagram showing the conduction state of each switch in the common control circuit for each period.

FIG. 5 is a circuit diagram showing another embodiment of the liquid crystal panel.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Active matrix (AM) part 2 Scan line drive circuit 3a, 3b Signal line drive circuit 4 Common control circuit 5 Liquid crystal pixel 10 Array substrate 20 Counter substrate 21, 22 Counter electrode 41, 42, 43 Switch 44, 45 Output terminal 103 cup Signal line for ring compensation

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) G02F 1/133 550 G02F 1/133 550 1/1345 1/1345 1/1368 G09F 9/30 338 G09F 9/30 338 G09G 3/36 G09G 3/36 G02F 1/136 500 F term (reference) 2H092 GA59 JA24 JB04 JB14 JB32 NA26 PA06 2H093 NA16 NA32 NA34 NA43 NC21 NC34 ND09 ND15 ND39 NE03 NE07 5C006 AA01 AC27 AF44 AF51 AF73 AF82 BB14 BC20 BF11 FA22 FA47 5C080 AA10 BB05 DD05 DD26 EE29 FF11 FF13 JJ02 JJ03 JJ04 5C094 AA02 AA22 BA03 BA43 EA02 EA04 EA07 EB02

Claims (5)

[Claims] 1. A pixel electrode connected via a switch element near each intersection of a plurality of scanning lines crossing each other and a plurality of signal lines divided into at least two sets, and is set to a common potential. A display panel in which display pixels including at least two opposing electrodes and a light modulation layer interposed between the electrodes are arranged in a matrix; a scanning line driving circuit for supplying a scanning signal to the scanning lines; A signal line driving circuit for supplying a video signal having a different polarity to each set of lines for each predetermined scanning period; supplying a common potential having a different polarity for each counter electrode to the respective counter electrodes for each predetermined scanning period; A common control circuit for short-circuiting between the opposing electrodes during a blanking period between a period and a next predetermined scanning period. 2. The flat display device according to claim 1, wherein the predetermined scanning period is one horizontal scanning period. 3. The flat display device according to claim 1, wherein the predetermined scanning period is one vertical scanning period. 4. The flat display device according to claim 1, wherein the common control circuit is formed integrally with the scanning line driving and signal line driving circuit on the same substrate. 5. An arrangement of pixel electrodes, switch elements and signal lines of the display panel, which is symmetrical with respect to a boundary of a set unit of the signal lines, and coupling compensation between the pixel electrodes adjacent to the boundary. 2. The flat display device according to claim 1, further comprising: arranging a signal line for connection, and applying an intermediate potential between a video signal supplied to the signal line and a common potential to the signal line for coupling compensation. 3.