JP2003318406A - Transistor circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To drive a transistor by a driving voltage similar to a conventional case or above it without dielectric breakdown even if film thickness of a gate insulating film is reduced since an element shape is reduced in a pixel driving circuit and a periphery driving circuit of a liquid crystal element. <P>SOLUTION: At least one capacitor is connected to a gate of the transistor constituting a level shifter 11 and a pixel circuit part 12. A voltage applied to the gate is divided by the capacitor and therefore the transistor is driven by the driving voltage similar to the conventional case or above it without the dielectric breakdown even if gate breakdown voltage of the transistor is set to be low. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a liquid crystal element and an organic EL device.
The present invention relates to a transistor circuit used in a pixel drive circuit such as an L element or a peripheral drive circuit.

[0002]

2. Description of the Related Art In recent years, since polycrystalline silicon and amorphous silicon can be formed into a film on a transparent substrate by a CVD method or the like, they are actively applied to liquid crystal display devices. The transistors formed of these silicon films are used not only as switching elements in the pixel section but also as polycrystalline silicon films as peripheral driving circuits for operating the switching elements, and as organic EL display elements. The application has been put to practical use.

In a flat-panel display such as a liquid crystal display device, there is a demand for a larger screen and higher definition, a narrower frame, and power saving. Therefore, in the peripheral drive circuit, it is necessary to miniaturize the circuit elements in order to increase the circuit scale and reduce the area, and it is also necessary to reduce the drive voltage in order to reduce the power consumption.

Generally, since the driving voltage of the element itself such as liquid crystal or organic EL is higher than the driving voltage of the peripheral driving circuit, when the driving voltage of the peripheral driving circuit is lowered, the peripheral driving of low driving voltage is performed. It is necessary to provide a level shifter (voltage conversion circuit) between the output stage of the circuit and the pixel drive circuit having a high drive voltage, and drive the pixel by raising the drive voltage to a predetermined voltage.

[0005]

By the way, in the case of miniaturizing the peripheral drive circuit and lowering the drive voltage, it is general to reduce the element shape according to the scaling side of the semiconductor. . At this time, since the film thickness of the gate insulating film is reduced, the dielectric breakdown voltage (hereinafter, gate withstand voltage) is reduced. Usually, the transistors of the peripheral drive circuit and the transistors of the pixel portion and the level shifter are often manufactured in the same process. Therefore, a transistor with a low gate breakdown voltage is driven by a liquid crystal similar to the conventional one or a liquid crystal or EL which is driven by a higher drive voltage than the conventional one. If such a switching element is used, the pixel portion and the transistor of the level shifter may be destroyed, resulting in a problem of reduced reliability.

In order to solve the above problem, it is difficult to form a thick gate insulating film for a pixel portion or a transistor of a level shifter for a transistor of a peripheral driving circuit in the same process, and it is formed in another process. However, there is a problem that the manufacturing cost increases.

An object of the present invention is to provide a transistor circuit capable of being driven at a driving voltage similar to or higher than the conventional one without causing dielectric breakdown even when the film thickness of the gate insulating film is reduced due to the reduction of the element shape. To provide.

[0008]

In order to solve the above-mentioned problems, the invention according to claim 1 is characterized in that, according to the potential of an input signal,
A first transistor circuit that outputs one of a power supply voltage and a second power supply voltage having a lower potential than the first power supply voltage;
It is connected to a plurality of scanning lines and a plurality of signal lines arranged in a matrix, and pixel electrodes arranged for each grid of the matrix, and is turned on by the first power supply voltage or the second power supply voltage supplied to the scanning lines. A second transistor circuit that is turned on / off and conducts a connection between the signal line and the pixel electrode when turned on to write a data signal supplied to the signal line to the pixel electrode. A gate electrode of each transistor element that forms the circuit and the second transistor circuit,
At least one capacitive element is connected.

According to a second aspect of the present invention, in the first transistor circuit according to the first aspect, the first transistor element, the second transistor element and the third transistor element have the first power supply voltage and the second power supply voltage, respectively. And a fourth transistor element, a fifth transistor element, and a sixth transistor element connected in series between the first power supply voltage and the second power supply voltage.
The gate of the first transistor element is connected in series with a power supply voltage, the gate of the first transistor element is connected to the drain of the fifth transistor element, the scan line and the source of the sixth transistor element, and the gate of the fourth transistor element is The drain of the second transistor element and the source of the third transistor element are connected, and the gates of the second and third transistor elements are connected to a second input terminal to which a complementary input signal of the input signal is supplied; The first and fifth gates of the fifth and sixth transistor elements are supplied with the input signal.
The second transistor circuit is connected to an input terminal,
A gate of the transistor element is connected to the scanning line, a source thereof is connected to the signal line, and a drain thereof is connected to the pixel electrode.

According to a third aspect of the present invention, in the first or second aspect, the capacitance of the capacitance element is equal to the gate capacitance of each of the transistor elements in the conductive state.

According to a fourth aspect of the present invention, in the second transistor circuit according to the first aspect, the drain of the eighth transistor element and the source of the ninth transistor element are connected to each other, and the eighth transistor element and the ninth transistor element are connected. A gate of the device is connected to the scanning line, a source of the eighth transistor device is connected to the signal line, and a drain of the ninth transistor device is connected to the pixel electrode.

According to a fifth aspect of the present invention, in the first to fourth aspects, the glass substrate is formed of the same metal as the gate electrode of the transistor, the polycrystalline silicon doped with phosphorus at a high concentration, the gate insulating film, It is characterized by including a capacitor in which an electrode is formed such that an area of a portion where the polycrystalline silicon and the metal overlap each other becomes equal to a channel area of a transistor having the polycrystalline silicon as an active layer.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments in which a transistor circuit according to the present invention is applied to a liquid crystal display device will be described below with reference to the drawings.

FIG. 2 is a circuit diagram of the liquid crystal display device according to this embodiment. On the array substrate 1, a pixel portion 2 in which a plurality of pixels are formed, a scanning line driving circuit 3 and a signal line driving circuit 4 which are peripheral driving circuits are arranged.

The pixel section 2 has a plurality of signal lines S1 and S.
2, ... Sm (hereinafter, generic name S) and a plurality of scanning lines G1, G2, ... Gn (hereinafter, generic name G) intersecting with the matrix are arranged in a matrix, and an n-type pixel is provided for each grid of this matrix. A transistor 120 is provided. Signal line S
The scanning line G and the scanning line G are electrically insulated by an insulating film (not shown).

The pixel transistor 120 has a gate on the scanning line G, a source on the signal line S, and a drain on the pixel electrode 123.
Respectively connected to. Although not shown in FIG.
A common counter electrode facing each pixel electrode 123 is also formed on a counter substrate (not shown). Array substrate 1
The counter substrate and the counter substrate are arranged at a predetermined interval so that their electrode surfaces face each other, and the periphery thereof is sealed with a sealing material. Then, a liquid crystal material (not shown) is filled inside the both substrates as a display layer.

Further, in the array substrate 1, the pixel electrodes 12
A storage capacitor 3 (not shown) for holding a potential relationship with a counter electrode (not shown) is connected in parallel with 3. This auxiliary capacitance forms a capacitance Cs between the pixel electrode 123 and an auxiliary capacitance line (not shown). Further, a constant common voltage is applied to the counter electrode (not shown) from the external control circuit 5.

The scanning line drive circuit 3 is composed of a plurality of shift registers, inverters, level shifters, buffers and the like, which are not shown. In the shift register not shown, the vertical start signal S supplied from the external control circuit 5
The TV is output while shifting by one stage in synchronization with the vertical clock signal CKV also supplied from the external control circuit 5. The vertical start signal output from the shift register is supplied to an inverter (not shown) and a level shifter, raised to a predetermined voltage, and then output to the corresponding scan lines G1, G2 ... As a scan signal via a buffer.

The signal line drive circuit 4 is composed of a plurality of shift registers, a video bus, a plurality of analog switches and the like which are not shown. The shift register is a horizontal clock signal C supplied as a control signal from the external control circuit 5.
An ON / OFF signal is output to an analog switch (not shown) based on KH and the horizontal start signal STH to electrically connect the video bus and the signal line S, and a data signal supplied from the external control circuit 5 through the video bus is supplied. Signal line S
1, S2, ...

The scanning line drive circuit 3 and the signal line drive circuit 4 are supplied with VDD as a high level power supply voltage and VSS as a low level power supply voltage. In the scanning line drive circuit 3, the power supply voltage VDD is VD
Converted to D1 and VDD2, and the power supply voltage VSS is VS
Converted to S1 and VSS2. These power supply voltages are supplied to the inverter 10 and the level shifter 11 described later.

The external control circuit 5 is composed of a control IC (not shown), a D / A converter, a level shifter, etc., and appropriately converts and processes an externally supplied reference clock signal, digital data signal, etc. to generate an analog signal. Data signals and control signals (CKV, CKH, STV, ST
H), power supply voltage (VDD, VSS), common voltage, etc. are supplied to each drive circuit on the array substrate 1. The external drive circuit 5 and the array substrate 1 are electrically connected by an FPC (flexible wiring substrate) not shown.

FIG. 1 is a circuit configuration diagram of a part of the pixel portion 2 shown in FIG. 2 and an output stage of the scanning line driving circuit 3. In FIG. 1, the same parts as those in FIG. 2 are represented by the same reference numerals. The inverter 10 and the level shifter 11 shown in FIG.
1 shows a circuit configuration corresponding to one scanning line G, and the number of scanning lines (G
1, G2, ... Gn) are arranged. Further, the buffer and its circuit are omitted.

First, the inverter 10 will be described.
The inverter 10 includes n-type transistors 101 and 103.
And p-type transistors 102 and 104. VDD1 is supplied to the power supply line 14 as a high-level power supply voltage, and Low is supplied to the power supply line 15.
VSS1 is supplied as the level power supply voltage.

The transistors 101 and 102 are connected in series between the power supply voltage VDD1 and the same VSS1 and the transistors 103 and 104 are also connected to the power supply voltage VDD1 and the same V1.
It is connected in series between SS1. Transistor 10
The sources of 2 and 104 are the power supply voltage VDD at the node 154.
1 and the drains of the transistors 101 and 103 are connected to the power supply voltage VSS1 at a node 153. Further, the gates of the transistors 101 and 102 are connected to the inverter input terminal 13 at the node 151, and the drain of the transistor 102 and the source of the transistor 101 are connected to the output terminal 152 of the inverter 10 together with the gates of the transistors 104 and 103. . Similarly, the drain of transistor 104 and transistor 10
The source of No. 3 is connected to the output terminal 155 of the inverter 10.

Next, the level shifter 11 will be described. The level shifter 11 includes an n-type transistor 111,
113, p-type transistors 112, 114, 115,
116 and capacitors (capacitance elements) 131 to 138, 14 described later that are connected to the gates of these transistors.
1 to 144.

First, the structure of the transistor will be described. The capacitors will be described later.
Here, only the structure of the transistor will be described.

H is connected to the power supply line 16 of the level shifter 11.
VDD2 is supplied as a high level power supply voltage, and VSS2 is supplied to the power supply line 17 as a low level power supply voltage. Transistors 111 and 112
And 115 are connected in series between the power supply voltage VDD2 and the same VSS2, and are connected to the transistors 113, 114 and 11
Similarly, 6 is connected in series between the power supply voltage VDD2 and the same VSS2. Of these, the transistors 111 and 112 are connected at the node 160, and
Is connected to the drain of transistor 115 at node 161. Also, transistors 113 and 11
4 is connected at node 170, and the source of transistor 114 is connected at node 171 to the drain of transistor 116.

The sources of transistors 115 and 116 are connected to power supply voltage VDD2 at node 165, and the drains of transistors 111 and 113 are connected to power supply voltage VSS2 at node 166. Also, the transistor 1
The gate 162 of 15 is connected to the drain of the transistor 114 and the source of the transistor 113 via the node 164, and the gate 169 of the transistor 116 is connected to the node 16.
7 to the drain of the transistor 112 and the source of the transistor 111. Further, the gate 157 of the transistor 111 and the gate 159 of the transistor 112 are connected to the output terminal 155 of the inverter 10,
The gate 172 of the transistor 113 and the transistor 1
The gate 175 of node 14 is connected to the inverter 10 at node 174.
Is connected to the output end 152 of the. Note that the node 164
Is an output terminal of the level shifter 11 and is connected to the scanning line G.

In FIG. 1, transistors 111 and 11 are provided.
2, 113 and 114 form an input / output stage transistor, and the transistors 115 and 116 form the transistor 11
It is configured to improve the source / drain breakdown voltage of 1,112,113,114 and to widen the switching operation range. Among these, the transistors 115, 112, and 111 respectively form the first transistor element, the second transistor element, and the third transistor element in the present embodiment, and the transistors 116, 114, and 113 are the fourth transistor element and the third transistor element in the present embodiment, respectively. A five-transistor element and a sixth-transistor element are respectively configured.

Further, the power supply voltage VDD2 supplied to the power supply line 16 constitutes the first power supply voltage in this embodiment, and the power supply voltage VSS2 supplied to the power supply line 17 in this embodiment is higher than the first power supply voltage. Low potential second
Configure the power supply voltage. Then, the level shifter 11 constitutes the first transistor circuit in this embodiment.

In the above structure, when the scanning signal output from the shift register (not shown) is supplied from the inverter input terminal 13 as the input of the inverter circuit, the output terminals 152 and 155 of the inverter 10 receive the power supply voltage VDD1,
The same VSS1 is output as signals of opposite phase and same phase, respectively. Then, when these signals are input to the node 174 of the level shifter 11 and the node 155 which is common to the output terminal (155) of the inverter 10, the power supply voltage VDD
A signal having a potential of 1 or VSS1 appears at nodes 160 and 170 as a level-shifted output signal.

The node 155 constitutes the second input end in this embodiment, and the node 174 constitutes the first input end in this embodiment.

Next, the structure of the capacitor connected to the gate of each transistor will be described.

The capacitors 131 and 132 connected in series at the node 156 are connected to the output terminal 155 of the inverter 10 and the gate 157 of the transistor 111 of the level shifter 11.
And capacitors 133 and 134 connected in series at node 158 are connected between the output 155 of the inverter 10 and the gate 159 of the transistor 112 of the level shifter 11. Similarly, node 17
The capacitors 135 and 136 connected in series at 3 are connected between the output terminal 152 of the inverter 10 and the gate 172 of the transistor 113, and the capacitors 137 and 138 connected in series at the node 176 are connected to the inverter 10. Output terminal 152 and gate 17 of transistor 114
It is connected between 5 and.

Further, the capacitors 141 and 142 connected in series at the node 163 are connected to the transistors 114 and 1.
Node 170 and transistor 115, which are the output terminals of 13
Capacitors 143 and 144 connected in series with the gate 162 of the transistor 168 and connected in series with the node 168 are connected between the node 160 which is the output terminal of the transistors 112 and 111 and the gate 169 of the transistor 116. .

Next, the operation of the capacitor configured as described above will be described.

In FIG. 1, the capacitances of the capacitors 131 and 132 are made equal to the gate capacitance of the transistor 111, respectively, and the capacitors 133 and 1
The capacitance of 34 is made equal to the gate capacitance of the transistor 112, respectively. Further, the capacities of the capacitors 135 and 136 are made equal to the gate capacities of the transistors 113, respectively, and the capacitors 137 and 138 are set.
Is set to be equal to the gate capacitance of the transistor 114. Further, the capacitances of the capacitors 141 and 142 are made equal to the gate capacitance of the transistor 115, respectively, and the capacitances of the capacitors 143 and 144 are
The gate capacitance of each transistor 116 is made equal. In the case of such capacitance distribution, the transistor 11
The voltage applied to the gates 1-116 is divided into about 1/3 by the two capacitors connected in series to the gates. Can be set as low as about 1/3.

For example, the power supply line 14 of the inverter 10
When a DC voltage of 3V is applied to the power supply line 15, a DC voltage of 21V is applied to the power supply line 16 of the level shifter 11, and a DC voltage of 0V is applied to the power supply line 17, a digital scan signal is input to the inverter input terminal 13. , In-phase scanning signals are output to the scanning line G with amplitudes of 0V and 21V. At this time, the transistors 111, 112, 11
The voltage applied between the gates of 3,114, 115, and 116 and the source / drain (which means a source or a drain; the same applies hereinafter) is 21V / 3, and therefore is a maximum of 7V. Therefore, the gate breakdown voltage can be set low in device design. Specifically, in the above embodiment in which 21 V is applied to the gate, the gate breakdown voltage is 7
It can be about V.

For comparison, the structure of the conventional example, that is, the structure in which the capacitor is not connected to the gate of each transistor will be described. Liquid crystal 21 ±
When driving at 5 V (amplitude 10 V), the counter electrode 182
The power line 20 of 7V is connected to the
A 12V data signal will be supplied. At this time,
In order to drive the pixel transistor 120, it is necessary to apply a digital scanning signal of about 0V / 15V to the scanning line G. For example, a DC voltage of 5V is applied to the power supply line 14 of the inverter 10 as a power supply voltage VDD1, a DC voltage of 0V is applied to the power supply line 15 as a power supply voltage VSS1, and a power supply voltage VDD2 of 1V is applied to the power supply line 16 of the level shifter 11.
5V, 0V DC voltage is applied to the power supply line 17 as the power supply voltage VSS2, and 0V is applied to the inverter input terminal 13.
When a / 5V scan signal is input, a 0V / 15V in-phase signal is output to the node 164 of the level shifter 11, and a 15V / 0V anti-phase voltage is output to the node 167 as a scan signal. In this case, a voltage of 0V / 15V is output as a scan signal to the scan line G connected to the node 164, and the pixel transistor 120 is driven, so that the transistor 111 included in the level shifter 11 is driven.
As for -116, a gate breakdown voltage of at least 15V is required.

As described above, in the structure of the conventional example, the gate withstand voltage corresponding to the power supply voltage VDD2 supplied to the power supply line 16 is required, so that the peripheral drive circuit can be miniaturized and the drive voltage can be lowered. It has been difficult to reduce the gate breakdown voltage by reducing the device shape of the transistor. However, in the present embodiment, the gate-source voltage of the transistor is divided according to the capacitance of the capacitor connected in series to the gate, so that the gate breakdown voltage can be set low in the element design, The thickness of the gate insulating film can be reduced. Specifically, comparing the case of the conventional example in which a power supply voltage of 15 V is applied to the power supply line 16, the gate insulating film can be thinned to about 1/2.

Next, the pixel circuit section 12 will be described.
The pixel circuit section 12 shows a circuit configuration of one pixel of the pixel section 2 shown in FIG. The gate 180 of the pixel transistor 120 is connected to the scan line G at a node 178. And a capacitor 12 connected in series at node 179.
1 and 122 are the gate 180 of the pixel transistor 120
And the scanning line G. The source of the pixel transistor 120 is connected to the signal line S at a node 177, and the drain is connected to the pixel electrode 123 at a node 181. The liquid crystal 2 is provided between the pixel electrode 123 and the counter electrode 182.
1 is held. The counter electrode 182 is the power supply line 20.
, And a predetermined common voltage is applied from the external control circuit 5 (FIG. 2).

The pixel circuit section 12 constitutes the second transistor circuit in this embodiment.

Next, the function of the capacitor connected in series to the gate of the pixel transistor 120 in the pixel circuit section 12 will be described.

In FIG. 1, the capacitances of the capacitor 121 and the capacitor 122 are respectively represented by the pixel transistor 120.
Equal to the gate capacitance of. In the case of such capacitance distribution, the voltage applied to the gate of the transistor 120 is divided into about 1/3 by the two capacitors connected in series to the gate, so that the voltage applied to the gate is the same. In this case, the gate breakdown voltage can be set as low as about 1/3 of the conventional value.

For example, the power supply line 14 of the inverter 10
When a DC voltage of 3V is applied to the power supply line 15, a DC voltage of 21V is applied to the power supply line 16 of the level shifter 11, and a DC voltage of 0V is applied to the power supply line 17, a digital scan signal is input to the inverter input terminal 13. , In-phase scanning signals are output to the scanning line G with amplitudes of 0V and 21V. At this time, the voltage applied between the gate and the source / drain of the transistor 120 is 21 V / 3, which is 7 V at maximum. Therefore, the gate breakdown voltage can be set low in device design. Specifically, in the above embodiment in which 21V is applied to the gate, the gate breakdown voltage can be set to about 7V.

As described above, in this embodiment, since the gate-source / drain voltage of the pixel transistor is divided according to the capacitance of the capacitor connected in series to the gate, the gate breakdown voltage is set low in the element design. Therefore, the thickness of the gate insulating film can be reduced. Specifically, the power supply line 16 has a power supply voltage of 1
Comparing the case of the conventional example in which 5 V is applied, the gate insulating film can be thinned by about ½.

Therefore, according to this embodiment, as the transistors 101 to 104 of the inverter 10, the transistors 111 to 116 of the level shifter 11, and the pixel transistor 120 of the pixel circuit section 12, transistors having a low gate breakdown voltage are formed in the same process. Since it can be manufactured, the driving voltage can be lowered. As a result, the element shape can be reduced in accordance with the scaling side of the semiconductor, the peripheral drive circuit can be miniaturized, and the drive voltage can be lowered.

In particular, in the above embodiment, the power supply voltage of the level shifter 11 can be raised from 15V to 21V while lowering the gate breakdown voltage. In addition, the inverter 1
The power supply voltage 5V of 0 can be reduced to 3V.

Next, an embodiment showing another connection example of the capacitors connected to the input stage of the level shifter 11 will be described with reference to FIG.
It will be described together with (a) to (d). 3 (a)-(d)
Then, the same parts as in FIG. 1 are represented by the same reference numerals.

FIG. 3 (a) shows an embodiment in which the capacitor 211 is connected between the nodes 155 and 157 and the capacitor 212 is connected between the nodes 155 and 159. By designing the capacitance of the capacitor 211 to be equal to the gate capacitance of the transistor 111 and the capacitance of the capacitor 212 to be equal to the gate capacitance of the transistor 112,
The gate breakdown voltage can be set as low as about half that of the conventional one. FIG. 3B shows a capacitor 22 connected in series.
1, 222 and 223 are connected between nodes 155 and 157, and capacitors 224, 225 and 2 are connected in series.
26 shows an embodiment in which 26 is connected between the nodes 155 and 159. By designing the capacities of the capacitors 221, 222, and 223 to be equal to the gate capacity of the transistor 111 and the capacities of the capacitors 224, 225, and 226 to be equal to the gate capacity of the transistor 112, respectively, the gate breakdown voltage can be reduced to about 1 It can be set as low as / 4. The number of capacitors connected between the nodes 155 and 157 and between the nodes 155 and 159 may be three or more.

In FIG. 3C, the capacitor 231 is connected between the nodes 155 and 234 and the capacitor 232 is connected between the nodes 23 and 23.
4 and 157, a capacitor 233 is connected to nodes 234 and 1
It shows an embodiment in which 59 are connected to each other. FIG. 3D shows a capacitor 24 connected in series.
1 shows an embodiment in which Nos. 1 and 242 are connected between the nodes 155 and 243, and the gates of the transistors 111 and 112 are connected to the node 243.

Subsequently, an embodiment showing another connection example of the capacitors connected to the pixel circuit section 12 will be described with reference to FIGS.
It will be described together with (f). 4A to 4F, the same parts as those in FIG. 1 are represented by the same reference numerals.

FIG. 4A shows an embodiment in which one capacitor 311 is connected to the gate of the pixel transistor 120, and FIG. 4B shows the pixel transistor 12.
Three capacitors 321, 322, 323 on the gate of 0
2 shows an embodiment in which are connected in series. The number of capacitors connected to the gate of the pixel transistor 120 may be three or more.

The pixel transistor may be a p-type transistor as shown in FIG. 4 (c). here,
A capacitor 1 is provided at the gate of the p-type pixel transistor 330.
It shows an embodiment in which 21, 122 are connected in series.
Even when the p-type pixel transistor 330 is used, the number of capacitors to be connected may be three or more.

Further, the transistor 1 of the level shifter 11
The embodiments shown in FIGS. 4A to 4C can be applied to the capacitors connected to the gates of 15 and 116.

On the other hand, the pixel transistor may be one in which two sources and two drains on one side are connected in series. FIG. 4D shows pixel transistors 341 and 342.
Are connected in series, capacitors 343 and 344 are connected to the gate of the pixel transistor 341, and
2 shows an embodiment in which capacitors 345 and 346 are respectively connected in series to the gate of 2.

Further, a part or all of the capacitors connected to the gates of the pixel transistors may be commonly connected to the gates of the two pixel transistors.
FIG. 4E shows an embodiment in which some of the capacitors are commonly connected. Capacitors 351 and 352 are connected to the gates of the pixel transistors 341 and 342, respectively, and a capacitor 353 is also commonly connected. Figure 4
(F) is an embodiment in which all capacitors are commonly connected, and capacitors 361 and 362 are connected in series to the commonly connected gates of the pixel transistors 341 and 342.

The transistors 341 and 342 respectively form the eighth transistor element and the ninth transistor element in this embodiment.

Further, the object driven by the pixel may be other than the liquid crystal, and as shown in FIG.
Even if 0 is driven, the same effect can be expected. Also in this case,
The connection of capacitors is shown in FIGS. 3 (a) to 3 (d) and 4 (a) to
The embodiment shown in (f) can be applied.

Next, a specific element structure of the transistor and the capacitor in the level shifter 11 of FIG. 1 will be described.

FIG. 6 shows an n-type transistor 103 and a p-type transistor 10 located at the output stage of the inverter 10.
4 is a plan structural view of elements that configure an n-type transistor 111, a p-type transistor 112, a capacitor 131, a capacitor 132, a capacitor 133, and a capacitor 134 located at the input stage of the level shifter 11 and 4. 6, the same parts as those in FIG. 1 are represented by the same reference numerals.

The gate electrode 511 of the transistor 103 and the gate electrode 521 of the transistor 104 have the common wiring 5
01 connects to the node 152. The source / drain electrode 512 of the transistor 103 is connected to the node 153 (FIG. 1) not shown. The source / drain electrode 522 of the transistor 104 is connected to a node 154 (FIG. 1) not shown. A drain source electrode 513 of the transistor 103 (meaning a drain or a source; the same applies hereinafter) and a drain source electrode 523 of the transistor 104 are connected to the wiring 502 through a contact hole 504.

The wiring 502 is formed by the wiring common to the upper electrode 561 of the capacitor 132 and the upper electrode 581 of the capacitor 134. Capacitor 132 and capacitor 13
The lower electrode of No. 1 is formed of the common polysilicon films 552 and 562, and the upper electrode 551 of the capacitor 131 is formed of the same wiring as the gate electrode 531 of the transistor 111. The lower electrodes of the capacitors 134 and 133 are formed of common polysilicon films 572 and 582, and the upper electrode 571 of the capacitor 133 is connected to the transistor 112.
The gate electrode 541 is formed by a common wiring. The source / drain electrode 532 of the transistor 111 is connected to the node 166 (not shown) (FIG. 1). Transistor 11
The second source / drain electrode 542 is the node 16 not shown.
1 (FIG. 1). The drain / source electrode 533 of the transistor 111 and the drain / source electrode 543 of the transistor 112 are connected through the contact hole 505 to the wiring 503.
Connected to.

Here, by making the electrode areas of the capacitors 131 and 132 equal to the channel area of the transistor 111, the capacitances of the capacitors 131 and 132 become equal to the gate capacitance of the transistor 111, respectively. Further, by forming the electrode areas of the capacitors 133 and 134 equal to the channel area of the transistor 113, the capacitances of the capacitors 133 and 134 are equal to the gate capacitance of the transistor 113, respectively.

Next, the cross-sectional structure of the transistor and the capacitor configured as described above will be described.

FIG. 7A is a sectional structural view taken along the line AA of FIG. Plasma CVD on glass substrate 601
A silicon nitride film, a silicon oxide film, or a laminated film 602 of these is formed by a method of about 150 nm,
50 n of isolated polysilicon film is formed on the glass substrate 601.
It is formed with a thickness of about m. n-type transistor 1
03, the polysilicon film has a thickness of 1E between the gate electrode 511 and the channel region 613 formed immediately below the gate electrode 511.
A source region (unsigned) and a drain region 611 and 1E1 doped with about 20 atm / cm3 of phosphorus.
LDD doped with phosphorus at about 8 atm / cm3
(light doped drain) region 612. In the p-type transistor 104, the polysilicon film is the gate electrode 521 and the channel region 6 formed immediately below the gate electrode 521.
The drain region 614 is composed of a source region (unsigned) doped with boron at about 1E20 atm / cm3.

A silicon oxide film 603 having a thickness of about 60 nm is formed as a gate insulating film on each polysilicon film. Gate electrodes 511 and 521 made of molybdenum-tungsten alloy are formed on the gate insulating film with a thickness of about 30 nm. On these gate electrodes,
A silicon oxide film 604 is formed, and source / drain electrodes 512, 513, 522, 523 made of a molybdenum and aluminum laminated film are formed on the silicon oxide film 604 with a thickness of about 600 nm. These source / drain electrodes are connected to the source / drain regions 611, 61 of the polysilicon film through contact holes (not shown).
4 is connected. The source / drain electrode 513 and the source / drain electrode 523 are connected to the wiring 502 through a contact hole (no reference numeral). In addition, 2 is formed on the source / drain electrodes 512, 513, 522, and 523.
A silicon nitride film 605 having a thickness of about 00 nm is formed.

FIG. 7B is a sectional structural view taken along the line BB in FIG. Plasma CVD on glass substrate 601
A silicon nitride film, a silicon oxide film, or a laminated film 602 of these is formed by a method of about 150 nm,
50 n of isolated polysilicon film is formed on the glass substrate 601.
It is formed with a thickness of about m. In the capacitor 131, the polysilicon film is doped with about 1E20 atm / cm 3 of phosphorus, which is the capacitor 13
1,132,133,134 lower electrodes 552,56
2,572,582. At this time, the capacitor 552
And 562 or capacitors 572 and 582 may be the same island as shown. A silicon oxide film 603 having a thickness of about 60 nm is formed as a gate insulating film on each polysilicon film. On the gate insulating film, upper electrodes 551, 5 made of molybdenum-tungsten alloy are formed.
61, 571 and 581 are formed. A silicon oxide film 604 and a silicon nitride film 605 are further formed on these upper electrodes.

FIG. 7C is a sectional structural view taken along the line CC of FIG. Plasma CVD on glass substrate 601
A silicon nitride film, a silicon oxide film, or a laminated film 602 of these is formed by a method of about 150 nm,
50 n of isolated polysilicon film is formed on the glass substrate 601.
It is formed with a thickness of about m. n-type transistor 1
11, the polysilicon film has a thickness of 1E between the gate electrode 531 and the channel region 633 formed immediately below the gate electrode 531.
Source region (no reference numeral) and drain regions 631 and 1E1 doped with phosphorus at about 20 atm / cm3
Ringer-doped LDD of about 8 atm / cm3
It consists of region 632. p-type transistor 112
In, the polysilicon film is 1E20 between the gate electrode 541 and the channel region 635 formed thereunder.
It is composed of a source region (unsigned) doped with boron of about atm / cm 3 and a drain region 634.

A silicon oxide film 603 having a thickness of about 60 nm is formed as a gate insulating film on each polysilicon film. On the gate insulating film, gate electrodes 531 and 541 made of molybdenum-tungsten alloy are formed with a thickness of about 30 nm. A silicon oxide film 604 is formed on the gate electrode, and the silicon oxide film 604 is formed.
A source / drain electrode 532, 533, 543, 542 made of a laminated film of molybdenum and aluminum is formed on the upper surface of about 600 n.
It is formed with a thickness of m. These source / drain electrodes are connected to the source / drain regions 631 and 634 of the polysilicon film through contact holes (no reference numeral). Further, the source / drain electrode 533 and the source / drain electrode 543 are connected to the wiring 503 through a contact hole (no reference numeral). A silicon nitride film 6 having a thickness of about 200 nm is formed on the source / drain electrodes.
05 is deposited.

In FIGS. 6 and 7, the inverter 10 is used.
N-type transistor 103 and p-type transistor 104 located at the output stage of n, and n-type transistor 111, p-type transistor 112, capacitor 131, capacitor 132, capacitor 133, and capacitor 134 located at the input stage of level shifter 11. However, other transistors and capacitors forming the level shifter 11 can be similarly formed.

Next, a specific element structure of the transistor and the capacitor in the pixel circuit section 12 will be described.

FIG. 8 is a plan structural view of elements forming the n-type transistor 120, the capacitor 121, and the capacitor 122 of the pixel circuit section 12. 8, the same parts as those in FIG. 1 are represented by the same reference numerals.

The source / drain electrode 712 of the transistor 120 is formed in the same wiring as the signal line S, and the source / drain electrode 713 is connected to the pixel electrode 123 through the contact hole 702. Gate electrode 721 (711)
Are formed with the same wiring as the upper electrode of the capacitor 121. The lower electrodes of the capacitors 121 and 122 are formed of common polysilicon 722 and 732, and the upper electrode 731 of the capacitor 122 is formed of a wiring common to the scanning line G.

Here, by forming the electrode areas of the capacitors 121 and 122 to be equal to the channel area of the transistor 120, the capacitances of the capacitors 121 and 122 and the gate capacitance of the transistor 120 become equal to each other.

FIG. 9A is a sectional structural view taken along the line AA of FIG. Plasma CVD on glass substrate 601
A silicon nitride film, a silicon oxide film, or a laminated film 602 of these is formed by a method of about 150 nm,
50 n of isolated polysilicon film is formed on the glass substrate 601.
It is formed with a thickness of about m. n-type transistor 1
20, the polysilicon film has a thickness of 1E between the gate electrode 711 and the channel region 813 formed immediately below the gate electrode 711.
Source region (no reference numeral) and drain regions 811 and 1E1 doped with about 20 atm / cm3 of phosphorus
Ringer-doped LDD of about 8 atm / cm3
It consists of region 812.

A silicon oxide film 603 having a thickness of about 60 nm is formed as a gate insulating film on each polysilicon film. A gate electrode 711 made of molybdenum-tungsten alloy is formed on the gate insulating film with a thickness of about 30 nm. A silicon oxide film 604 is formed on the gate electrode 711, and source / drain electrodes 712 and 713 made of a molybdenum and aluminum laminated film are formed on the silicon oxide film 604 to a thickness of about 600 nm. These source / drain electrodes are connected to the source / drain regions 812 of the polysilicon film through contact holes (no reference numeral). A silicon nitride film 605 having a thickness of about 200 nm is formed on the source / drain electrodes 712 and 713, and the silicon nitride film 605 is formed.
A resin color filter 801 having a thickness of about 1 μm is formed thereon. Furthermore, color filter 80
The pixel electrode 123 made of ITO has a thickness of 200 nm
It is formed to a thickness of about 100 nm and is connected to the source / drain electrode 713 through the contact hole 702 (FIG. 8).
On the pixel electrode 123, an alignment film 802 of liquid crystal containing polyimide as a main component is formed with a thickness of about 200 nm.

FIG. 9B is a sectional structural view taken along the line BB of FIG. Plasma CVD on glass substrate 601
A silicon nitride film, a silicon oxide film, or a laminated film 602 of these is formed by a method of about 150 nm,
50 n of isolated polysilicon film is formed on the glass substrate 601.
It is formed with a thickness of about m. Capacitors 121, 1
22, the polysilicon film is 1E20 atm / cm.
About 3 phosphorus is doped, and this becomes the lower electrodes 722 and 732 of the capacitors 121 and 122. At this time, the lower electrodes 722 and 732 may be the same island as shown.

A silicon oxide film 603 having a thickness of about 60 nm is formed on each polysilicon film, and upper electrodes 721 and 731 made of molybdenum-tungsten alloy are formed on the silicon oxide film 603. Upper electrode 72
1, 731, a silicon oxide film 604, a silicon nitride film 605, a resin color filter 801, a pixel electrode 123 made of ITO, and an alignment film 802 are sequentially formed.

[0080]

As described above, according to the present invention,
Since the voltage applied to the gate of each transistor is divided by the capacitor, even if the film thickness of the gate insulating film is reduced due to the reduction in the element shape, the liquid crystal will be driven at a higher drive voltage than before without causing transistor breakdown. Also, the EL element can be driven.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a part of a pixel portion shown in FIG. 2 and an output stage of a scanning line driving circuit.

FIG. 2 is a circuit configuration diagram of a liquid crystal display device according to an embodiment.

3A to 3D are circuit configuration diagrams showing other connection examples of capacitors connected to the input stage of the level shifter.

FIGS. 4A to 4F are circuit configuration diagrams showing other connection examples of capacitors connected to the pixel circuit section.

FIG. 5 is a circuit configuration diagram when an organic EL is connected as a display element.

FIG. 6 is a plan structural view of elements forming an inverter and a level shifter.

7A is a cross-sectional structural view taken along the line AA of FIG. 6B is a cross-sectional structural view taken along the line BB of FIG.
FIG. 7C is a sectional structural view taken along the line CC of FIG. 6.

FIG. 8 is a plan structural view of an element forming a pixel circuit section.

9A is a cross-sectional structural view taken along the line AA of FIG. FIG. 9B is a sectional structural view taken along the line BB of FIG. 8.

[Explanation of symbols]

2 ... Pixel part, 3 ... Scan line drive circuit, 4 ... Signal line drive circuit, 5 ... External control circuit, 10 ... Inverter, 11 ... Level shifter, 12 ... Pixel circuit part, 14-17 ... Power supply line, 21 ... Liquid crystal, 101-104, 111-116 ... Transistor, 120 ... Pixel transistor, 121, 12
2, 131-138, 141-144 ... Capacitor, 1
23 ... Pixel electrode, 182 ... Counter electrode, S ... Signal line, G ...
Scan line

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09F 9/35 H01L 29/78 612B H01L 21/822 27/04 H 27/04 29/78 614 (72) Inventor Norio Tada 1-9-2, Hara-cho, Fukaya-shi, Saitama, Ltd. Fukaya Plant, Toshiba Corp. (72) Inventor, Yasuhiro Yoshida 1-9, Harara-cho, Fukaya-shi, Saitama F-term, Toshiba Fukaya Plant (reference) 2H092 GA24 GA28 JA24 JA37 JB61 JB63 JB67 NA14 NA21 PA06 5C094 AA15 AA23 AA31 BA03 BA27 BA43 CA19 DA15 EA04 EA07 FB19 5F038 BH03 BH15 EZ20 5F110 AA26 BB02 CC02 DD02 DD13 DD14 EE06 FF02 GG02 GG13 GG25 HJ01 HJ04 HL03 HL04 HL11 HM15 NN01 NN24 NN72 NN73

Claims (5)

[Claims] 1. A first transistor circuit for outputting either a first power supply voltage or a second power supply voltage lower than the first power supply voltage according to the potential of an input signal, and a plurality of matrix-arranged first transistor circuits. Connected to a scanning line, a plurality of signal lines, and a pixel electrode arranged for each grid of the matrix,
ON / OFF control is performed by the first power supply voltage or the second power supply voltage supplied to the scanning line, and when the pixel is turned on, the data line and the pixel electrode are electrically connected to each other and the data signal supplied to the signal line is supplied to the pixel. In a transistor circuit including a second transistor circuit for writing in an electrode, at least one capacitor element is connected to a gate electrode of each transistor element forming the first transistor circuit and the second transistor circuit. Characteristic transistor circuit. 2. The first transistor circuit, wherein a first transistor element, a second transistor element and a third transistor element are connected in series between the first power source voltage and the second power source voltage, and a fourth transistor element is provided. A transistor element, a fifth transistor element, and a sixth transistor element are connected in series between the first power supply voltage and the second power supply voltage, the gate of the first transistor element being the drain of the fifth transistor element, The scan line is connected to the source of the sixth transistor element, the gate of the fourth transistor element is connected to the drain of the second transistor element and the source of the third transistor element, and
And a gate of the third transistor element is connected to a second input terminal to which a complementary input signal of the input signal is supplied, and gates of the fifth and sixth transistor elements are connected to a first input terminal to which the input signal is supplied. 2. The second transistor circuit according to claim 1, wherein the second transistor circuit has a gate of the seventh transistor element connected to the scanning line, a source connected to the signal line, and a drain connected to the pixel electrode. Transistor circuit. 3. The transistor circuit according to claim 1, wherein the capacitance of the capacitance element is equal to the gate capacitance of each of the transistor elements in a conductive state. 4. In the second transistor circuit, the drain of the eighth transistor element and the source of the ninth transistor element are connected, the gates of the eighth transistor element and the ninth transistor element are connected to the scanning line, and the eighth transistor element is connected to the eighth line. 4. The transistor circuit according to claim 1, wherein the source of the transistor element is connected to the signal line, and the drain of the ninth transistor element is connected to the pixel electrode. 5. An area of a portion where a polycrystalline silicon doped with phosphorus at a high concentration, a gate insulating film, and the same metal as the gate electrode of the transistor are formed on a glass substrate, and the polycrystalline silicon and the metal overlap each other. 5. The transistor circuit according to claim 1, further comprising a capacitor having an electrode formed so as to be equal to a channel area of the transistor having the polycrystalline silicon as an active layer.