JP2001339379A - System clock interpolation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system clock interpolation circuit that can quickly and accurately re-lock a synchronizing signal in a short time even when a phase relation between a synchronizing signal of an input signal and a synchronization interpolation counter is largely deviated due to an external disturbance or the like. SOLUTION: The system clock interpolation circuit is provided with a synchronizing signal period detection circuit 7 that detects a period of a synchronization detection pulse 12 independently of a mask operation by a synchronization position mask signal 42 and when the detection circuit 7 confirms that the period of the detected synchronization detection pulse 12 is a normal period, the synchronization is locked again by the synchronization detection pulse 12 to reduce the time until synchronization re-locking.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing signal interpolation circuit for interpolating a synchronizing signal serving as an operation reference clock in a PLL or the like for resynchronization at the time of disturbance input.

[0002]

2. Description of the Related Art Conventionally, in a synchronous signal detecting circuit,
When a synchronization signal is lost due to noise of an input signal or the like, a synchronization signal interpolation circuit is widely used in order to prevent a subsequent circuit from receiving all data shifted by one synchronization signal.

The prior art of such a synchronization signal interpolation circuit will be described below. FIG. 6 is a block diagram showing a configuration of a conventional synchronization signal interpolation circuit. FIG. 7 is a timing chart showing a normal operation in the conventional example. FIG. 8 is a timing chart showing an operation at the time of disturbance input in the conventional example.

In FIG. 6, reference numeral 1 denotes a synchronization detection circuit.
The synchronization signal portion is detected from the input signal 11 and output as a synchronization detection pulse 12. Reference numeral 3 denotes a synchronous interpolation counter, the count value of which is initially reset by a reset input 32, and makes a cycle with the same cycle as the synchronous signal component included in the input signal 11. Reference numeral 4 denotes a decoder which decodes the output 31 of the synchronous interpolation counter 3 (retrieves and restores a signal that satisfies a predetermined condition) to convert the interpolation synchronization signal 41, the synchronization position mask signal 42, and "5". A decoded signal (a signal corresponding to the fifth pulse of the clock signal 6 counted after the synchronous interpolation counter 3 is reset by the reset input 32) 52 is output. Reference numeral 5 denotes a counter for measuring the number of times of non-synchronization detection, which is reset at the same time as the reset of the synchronous interpolation counter 3, and the "5" decode signal 52 from the decoder 4 is used as a clock input, and the count value is incremented at that timing. .

Reference numeral 2 denotes a synchronization signal mask control circuit. The comparator 24 compares the output 51 of the counter 5 for measuring the number of times of non-synchronization detection with a fixed value set in advance, and selects a selector 25 based on the comparison result. And synchronous position mask signal 4
2 and a fixed output of "H level",
The logical product of the output signal 26 from 5 and the synchronization detection pulse 12 is obtained by an AND gate 27, and the logical product is output as the reset input 32 of the synchronous interpolation counter 3.

The operation of the conventional synchronous signal interpolation circuit configured as described above will be described below. First, FIG.
As shown in (1), when the synchronization detection pulse 12 included in the input signal 11 is normally detected (period (1)), the reset input 32 of the synchronization interpolation counter 3 is input, and at that timing, the synchronization interpolation counter 3 is input. 3 is initially reset to "0", and its output 31 also becomes "0". The synchronous interpolation counter 3 is configured so as to make a single round in the cycle of the synchronous signal included in the input signal 11.

In the example shown in FIG. 7, the period is "6". Therefore, the synchronous interpolation counter 3 outputs the reset input 32
Does not enter, but the output 3 as in period (2)
It is preset to “0” at the next clock after 1 becomes “5”. Further, the synchronous position mask signal 42 has the “H” level (mask valid) period only when the output 31 of the synchronous interpolation counter 3 is “5”, “0”, or “1”.

While the synchronization signal is normally detected within the mask period, the reset input 32 of the synchronous interpolation counter 3 is input, and the synchronous interpolation counter 3 resets the output 31 to a normal value each time. adjust. The synchronization detection pulse 12 detected during the period in which the synchronization position mask signal 42 is at the “L” level is highly likely to have erroneously detected a false synchronization signal as in the period (3). It is ignored by the mask control circuit 2, the reset input 32 to the synchronous interpolation counter 3 is not generated, and the synchronous interpolation counter 3 does not perform the reset operation.

Then, even when the synchronization detection pulse 12 cannot be detected at a regular position as in the period (4), the cycle of the synchronization interpolation counter 3 makes a round at "6", and the interpolation synchronization signal 41 is output normally.

When the case of FIG. 7 is summarized, in the period (1), the synchronization detection pulse 12 is detected at a regular cycle, and the synchronization interpolation counter 3 itself and the reset by the reset input 32 occur simultaneously. In the period (2), the period of the synchronization detection pulse 12 is longer by one clock but is within the mask period. Therefore, the synchronization interpolation counter 3 is reset again by the synchronization detection pulse 12, and the interpolation synchronization signal 41 is normal. Is output to Further, in the period (3), a false synchronizing signal is detected, but is ignored because the synchronizing position mask signal 42 is invalid.
Synchronization detection is not disturbed. Finally, in the period (4), the synchronization signal is lost and the synchronization interpolation counter 3 is not reset.
1 is output at regular timing.

However, as shown in FIG. 8, when the phase relationship between the synchronization detection pulse 12 from the input signal 11 and the reset input 32 to the synchronization interpolation counter 3 is greatly shifted due to some disturbance, the synchronization detection pulse 12 may jump out during the “L” period of the synchronous position mask signal 42. In this case, the number of times the synchronization signal has been interpolated is counted by the counter 5 for measuring the number of times of non-synchronization detection.
When the value of 1 is equal to or more than "8" count, the output signal 26 of the selector 25 for fully opening the mask is fixed at "H" level, the synchronous position mask state is fully opened, and the synchronous detection pulse 1 is set.
2, the synchronization interpolation counter 3 is reset again, and synchronization re-pulling is executed.

[0012]

However, in the above-described conventional synchronous signal interpolation circuit, as shown in FIG. 8, the phase relationship between the synchronous signal of the input signal 11 and the synchronous interpolation counter 3 becomes large due to some disturbance. In the case of deviation, if the count value of the counter 5 for measuring the number of times of non-synchronization detection is not counted until it becomes “8”, the interpolation synchronization signal 4
The correction operation to the normal timing of 1 is not started.

In such a state, the interpolation synchronization signal 4
1 cannot be corrected to the regular timing in a short time, so that it takes a lot of time to complete the pull-in once synchronization is lost, and the pull-in operation becomes very slow. Was.

The present invention solves the above-mentioned conventional problems. Even when the phase relationship between the synchronization signal of the input signal and the synchronization interpolation counter is greatly shifted due to disturbance or the like, the interpolation synchronization signal is re-established. Provided is a synchronization signal interpolation circuit that can perform pull-in quickly, quickly, and accurately.

[0015]

In order to solve the above-mentioned problems, the synchronization signal interpolation circuit according to the present invention is provided with a method of synchronizing all the synchronization detection pulses separately from the masking operation of the false synchronization signal by the synchronization position mask signal. Are monitored, and when the period of the synchronization detection pulse is a regular period in the monitoring, the synchronization interpolation counter is immediately reset by the synchronization detection pulse.

As described above, even when the phase relationship between the synchronization signal of the input signal and the synchronization interpolation counter is greatly shifted due to disturbance or the like, re-pulling of the interpolation synchronization signal can be performed quickly and accurately in a short time. Can be.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A synchronization signal interpolation circuit according to a first aspect of the present invention includes: a synchronization detection circuit for detecting a portion of the synchronization signal from an input signal including a synchronization signal having a predetermined period. The count value is reset to zero by a reset input, and a synchronous interpolation counter that loops in the same cycle as the synchronization signal, an output of the synchronization interpolation counter is decoded, and an interpolation synchronization signal and a synchronization position mask signal are output. A synchronization signal cycle detection circuit that detects that the cycle of the synchronization signal output from the synchronization detection circuit matches a regular cycle; and that the synchronization signal cycle detection circuit has a normal cycle of the synchronization signal. The synchronous detection circuit detects the synchronous signal during the period when the synchronous position mask signal from the decoder is valid, and the synchronous detect circuit detects the synchronous signal during the period in which the synchronous position mask signal from the decoder is valid. A structure in which a sync signal mask control circuit for applying the reset input to the interpolation counter.

According to a second aspect of the present invention, there is provided a synchronous signal interpolating circuit, wherein the synchronous signal cycle detecting circuit according to the first aspect of the present invention is configured such that when the synchronous signal cycle completely coincides with the normal cycle only once, Is configured to detect that the period is normal.

According to these configurations, apart from the masking operation of the false synchronization signal by the synchronization position mask signal, the periods of all the synchronization detection pulses are monitored, and the period of the synchronization detection pulse is regular during the monitoring. If the period is the period, the synchronous interpolation counter is immediately reset by the synchronous detection pulse.

According to a third aspect of the present invention, there is provided a synchronous signal interpolating circuit, wherein the synchronous signal cycle detecting circuit according to the first aspect of the present invention is configured such that when the cycle of the synchronous signal completely coincides with the normal cycle continuously plural times,
It is configured to detect that the period of the synchronization signal is normal.

According to this configuration, the probability of erroneous re-locking due to a false synchronizing signal is reduced. According to a fourth aspect of the present invention, there is provided a synchronization signal interpolating circuit, wherein the synchronization signal cycle detection circuit according to the first aspect is configured such that when the cycle of the synchronization signal is within a certain range with respect to a normal cycle only once, It is configured to detect that the period of the synchronization signal is normal.

According to this configuration, even when the PLL has not completed the frequency pull-in, the synchronization re-pull is performed regardless of the frequency pull-in. According to a fifth aspect of the present invention, there is provided a synchronous signal interpolation circuit comprising the synchronous signal cycle detecting circuit according to the first aspect,
When the period of the synchronization signal is within a certain range with respect to the normal period continuously for a plurality of times, it is configured to detect that the period of the synchronization signal is normal.

According to this configuration, the probability of erroneous re-locking due to a false synchronizing signal is reduced, and P
Even when the LL does not complete the frequency pull-in, the synchronization re-pull is performed regardless of the frequency pull-in.

Hereinafter, a synchronization signal interpolation circuit according to an embodiment of the present invention will be specifically described with reference to the drawings. (Embodiment 1) A synchronization signal interpolation circuit according to Embodiment 1 of the present invention will be described.

FIG. 1 is a block diagram showing the configuration of the synchronization signal interpolation circuit according to the first embodiment. FIG. 2 is a timing chart showing the operation of the synchronization signal interpolation circuit according to the first embodiment. 1, an input signal 11, a synchronization detection circuit 1, a synchronization interpolation counter 3, and a decoder 4 are shown in FIG.
This is the same as the conventional example shown in FIG.

Reference numeral 7 denotes a synchronization signal cycle detection circuit for detecting that the cycle of the synchronization detection pulse 12 coincides with the normal cycle. A decoder 72 for detecting that the output value of the synchronization signal period detection counter 71 is "5", a delay element 73 for delaying the output of the decoder 72 by one clock of the clock signal 6,
An AND gate 74 that takes the logical product of the output from the delay element 73 and the synchronization detection pulse 12 is provided.

By configuring the synchronization signal cycle detection circuit 7 as described above, when the cycle of the synchronization detection pulse 12 is "6", which is a normal cycle, the synchronization signal cycle normal detection signal 75 becomes "H". ".

Reference numeral 8 denotes a synchronization signal mask control circuit, which performs an OR gate operation on an output obtained by passing the synchronization position mask signal 42 and the synchronization detection pulse 12 through an AND gate 81 and an output signal 75 of the synchronization signal period detection circuit 7. The output passed through 82 is used as the reset input 32 of the synchronous interpolation counter 3.

By configuring the synchronization signal mask control circuit 8 as described above, even if the synchronization detection pulse 12 jumps out of the synchronization position mask signal 42, the synchronization signal cycle detection circuit 7 When the normal cycle detection signal 75 is detected, the synchronization detection pulse 12
, The synchronous interpolation counter 3 can be reset again.

The operation of the synchronization signal interpolation circuit configured as described above will be described below. First, when the synchronization detection pulse 12 is normally detected, when the period slightly changes within the period of the synchronization position mask signal 42, when it is detected at an incorrect position by a false synchronization signal, or when it is missing, Since the operation of the synchronization signal cycle detection circuit 7 does not matter, it operates in the same manner as the timing of the conventional synchronization signal interpolation circuit shown in FIG.

As shown in FIG. 8 in the conventional example, the phase relationship between the synchronization detection pulse 12 from the input signal 11 and the synchronization interpolation counter 3 is greatly shifted due to some disturbance, and the synchronization detection pulse 12 is shifted to the synchronization position. When the signal jumps out during the "L" period of the mask signal 42, the operation is as shown in FIG.

First, while the synchronization detection pulse 12 is normally detected, the output of the synchronization signal period detection counter 71 is decoded to be "5", and the delay element 73 delays the output by one clock of the clock signal 6. The generated signal is generated at the same timing as the synchronization detection pulse 12.

Accordingly, the synchronization signal period normal detection signal 75 is also generated at the same timing as the synchronization detection pulse 12. However, as in the period (5) shown in FIG.
If the period of 2 is disturbed, the synchronization signal period normal detection signal 75 is not generated for one clock of the clock signal 6.

However, during the period (6) shown in FIG. 2, the period of the synchronization detection pulse 12 returns to the normal period, so that the synchronization signal period normal detection signal 75 is output. The insertion counter 3 is reset again.

As a result, as shown in FIG. 2, the period during which the interpolation synchronization signal 41 deviates from the normal timing is one.
The number of frames is limited, and the period until re-synchronization is greatly reduced as compared with the case where the conventional example shown in FIG. 8 has eight frames. (Embodiment 2) A synchronization signal interpolation circuit according to Embodiment 2 of the present invention will be described.

FIG. 3 is a block diagram showing a configuration of a synchronization signal cycle detection circuit in the synchronization signal interpolation circuit according to the second embodiment. FIG. 3 shows only a configuration corresponding to the synchronization signal cycle detection circuit 7 of the first embodiment shown in FIG. 1, and all other components in FIG. And In FIG. 3, a synchronization signal cycle detection counter 71, a decoder 72, a delay element 73,
AND gate 74 is the same as that of the first embodiment shown in FIG.

In FIG. 3, reference numeral 76 denotes the synchronization detection pulse 12
AND that detects that was not detected in the regular cycle
The gate. Reference numeral 77 denotes a counter for measuring the number of times that the synchronization detection pulse 12 is continuously detected at regular timing. Reference numeral 78 denotes a comparator for detecting that the value of the counter 77 has exceeded a fixed value set internally, and a signal obtained by taking the logical product of the output of the counter 77 and the synchronization detection pulse 12 by the AND gate 74 indicates that the synchronization signal period is normal. It becomes the detection signal 75.

In the circuit shown in FIG. 3, unlike the first embodiment shown in FIG. 1, when the period of the synchronization detection pulse 12 is normal plural times continuously, the synchronization signal period becomes normal. It operates to output the detection signal 75 at the timing of the synchronization detection pulse 12.

By doing so, it is possible to reduce the probability that a false synchronizing signal will lead to an incorrect phase state during re-locking. (Embodiment 3) A synchronization signal interpolation circuit according to Embodiment 3 of the present invention will be described.

FIG. 4 is a block diagram showing a configuration of a synchronization signal cycle detection circuit in the synchronization signal interpolation circuit according to the third embodiment. FIG. 4 shows only a configuration corresponding to the synchronization signal cycle detection circuit 7 of the first embodiment shown in FIG. 1, and all other components in FIG. And 4, a synchronization signal cycle detection counter 71, a delay element 73, an AND gate 7
4 is the same as Embodiment 1 shown in FIG.

In FIG. 3, the decoder 70 sets the output of the synchronization signal period detection counter 71 to "4" or "5".
"6" is decoded and output. In the circuit shown in FIG. 4, unlike the first embodiment shown in FIG. 1, the period of the synchronization detection pulse 12 is “5” or “7” except for the case where the period is the regular “6”. Even in such a case, the synchronization re-locking can be performed, so that the synchronization re-locking can be performed even in a state where the frequency locking such as the PLL is not completed. (Embodiment 4) A synchronization signal interpolation circuit according to Embodiment 4 of the present invention will be described.

FIG. 5 is a block diagram showing a configuration of a synchronization signal cycle detection circuit in the synchronization signal interpolation circuit according to the fourth embodiment. FIG. 5 shows only a configuration corresponding to the synchronization signal cycle detection circuit 7 of the first embodiment shown in FIG. 1, and all other components in FIG. And Each component in FIG. 5 is the same as the component in FIG. 3 and FIG. 4, respectively, and its operation also includes the advantages of FIG. 3 and FIG.

That is, in the configuration of FIG. 3, the condition for detecting the period is stricter than in the configuration of FIG. 1, so that the probability of being pulled into the wrong phase state by a false synchronization signal at the time of re-locking can be reduced. On the other hand, there is a disadvantage that the time until re-synchronization is extended. Further, in the configuration of FIG. 4, the synchronization re-locking can be performed even when the frequency lock-in such as the PLL is not completed. On the other hand, if a false synchronizing signal is generated and the period detection is disturbed even once, the synchronization is re-drawn to an incorrect position.

However, in the configuration of FIG. 5, it is possible to confirm that the period of the synchronization signal is within a certain range a plurality of times, so that the synchronization re-pulling can be performed even when the frequency pull-in such as PLL is not completed. In addition, even when the period detection is disturbed by the false synchronization signal, it is possible to prevent the synchronization re-pulling to the wrong position.

As described above, the synchronization signal interpolation circuit of the present embodiment has the configuration shown in FIG. 1 so that all synchronization signals can be synchronized with the false synchronization signal masking operation by the synchronization position mask signal 42. The period of the detection pulse 12 is monitored, and when the period of the synchronization detection pulse 12 is a regular period in the monitoring, the synchronization interpolation counter 3 can be immediately reset by the synchronization detection pulse 12.

Further, by adopting the configuration shown in FIG. 3, the probability of erroneous re-locking due to a false synchronizing signal can be reduced. Further, with the configuration shown in FIG. 4, even if the PLL has not completed the frequency pull-in, the synchronization re-pull can be performed regardless of the frequency pull-in.

Further, by adopting the configuration shown in FIG. 5, the probability of erroneous re-locking due to a false synchronizing signal is reduced, and even if the PLL does not complete frequency locking, regardless of the frequency locking. , Synchronization re-pulling can be performed.

As a result, even when the phase relationship between the synchronization signal of the input signal and the synchronization interpolation counter is greatly shifted due to disturbance or the like, the re-pulling of the interpolation synchronization signal is performed quickly and accurately in a short time. be able to.

[0049]

As described above, according to the present invention, apart from the masking operation of the false synchronizing signal by the synchronizing position mask signal, the periods of all the synchronizing detection pulses are monitored, and the synchronizing detection is performed during the monitoring. When the pulse period is a regular period, the synchronous detection counter can immediately reset the synchronous interpolation counter.

Further, it is possible to reduce the probability that an erroneous synchronization re-pull is performed by a false synchronization signal. Also, PL
Even when L has not completed the frequency pull-in, the synchronization re-pull can be performed regardless of the frequency pull-in.

Further, it is possible to reduce the probability of erroneous re-locking due to a false synchronization signal and to perform re-locking irrespective of the frequency pull-in even when the PLL has not completed the frequency lock-in.

As described above, even when the phase relationship between the synchronization signal of the input signal and the synchronization interpolation counter is largely shifted due to disturbance or the like, re-pulling of the interpolation synchronization signal is performed quickly and accurately in a short time. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a synchronization signal interpolation circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the synchronization signal interpolation circuit according to the first embodiment;

FIG. 3 is a block diagram showing a configuration of a synchronization signal cycle detection circuit in a synchronization signal interpolation circuit according to a second embodiment of the present invention;

FIG. 4 is a block diagram showing a configuration of a synchronization signal cycle detection circuit in a synchronization signal interpolation circuit according to a third embodiment of the present invention;

FIG. 5 is a block diagram showing a configuration of a synchronization signal cycle detection circuit in a synchronization signal interpolation circuit according to a fourth embodiment of the present invention;

FIG. 6 is a block diagram showing a configuration of a conventional synchronization signal interpolation circuit.

FIG. 7 is a timing chart showing a normal operation in the conventional example.

FIG. 8 is a timing chart showing an operation when a disturbance is input in the conventional example.

[Explanation of symbols]

 Reference Signs List 1 synchronization detection circuit 3 synchronization interpolation counter 4 decoder 41 interpolation synchronization signal 42 synchronization position mask signal 6 clock signal 7 synchronization signal cycle detection circuit 70 decoder 71 synchronization signal cycle detection counter 72 decoder 73 delay element 74 AND gate 75 synchronization signal cycle Normal detection signal 76 AND gate 77 Counter 78 Comparator 8 Synchronous signal mask control circuit 81 AND gate 82 OR gate 11 Input signal 12 Synchronous detection pulse

Claims (5)

[Claims] 1. A synchronization detection circuit for detecting a portion of a synchronization signal from an input signal including a synchronization signal having a predetermined period, and a reset input, wherein a count value is reset to zero by a reset input, and at a same period as the synchronization signal. A synchronous interpolation counter that loops, a decoder that decodes the output of the synchronous interpolation counter and outputs an interpolation synchronization signal and a synchronization position mask signal, and a period of the synchronization signal output by the synchronization detection circuit is a regular one. A synchronization signal period detection circuit for detecting that the period coincides with the period; a case where the synchronization signal period detection circuit detects that the period of the synchronization signal is normal; and a case where the synchronization position mask signal from the decoder is valid. The synchronization for applying the reset input to the synchronization interpolation counter is performed under two conditions when the synchronization detection circuit detects a synchronization signal during a period of A synchronization signal interpolation circuit comprising: a signal mask control circuit. 2. The synchronization signal cycle detection circuit according to claim 1, wherein when the cycle of the synchronization signal completely coincides with the normal cycle only once, the synchronization signal cycle detection circuit detects that the cycle of the synchronization signal is normal. The synchronization signal interpolation circuit according to claim 1. 3. The synchronization signal cycle detection circuit is configured to detect that the cycle of the synchronization signal is normal when the cycle of the synchronization signal completely coincides with the normal cycle a plurality of times in succession. 2. The synchronization signal interpolation circuit according to claim 1, wherein: 4. A synchronizing signal cycle detecting circuit for detecting that the cycle of the synchronizing signal is normal when the cycle of the synchronizing signal is within a certain range with respect to a normal cycle only once. The synchronization signal interpolation circuit according to claim 1, wherein the synchronization signal interpolation circuit is configured. 5. A synchronizing signal cycle detection circuit detects that the cycle of the synchronizing signal is normal when the cycle of the synchronizing signal is within a certain range with respect to a normal cycle continuously plural times. 2. The synchronization signal interpolation circuit according to claim 1, wherein