JP2001332730A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a method for manufacturing the device capable of assuring a transistor function even when a thin element forming region is salicided in the device using an SOI substrate, reducing in size of the device, flattening and saliciding the region in a same step and raising its manufacturing efficiency. SOLUTION: An island-like silicon layer formed in an insulating layer is formed as an element forming region 22, gate electrodes 26 are formed on a front surface of the region 22, a source region 28 is formed on one of the electrode 26, and the other is formed on a drain region 30. A polycrystal silicon layer 24 is formed on the region 28, and the region 30 and silicide layers 32 are respectively formed on front surface sides of the layer 24 and the electrodes 26.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SOI (Silicon) in which a single crystal silicon layer is provided on a supporting substrate via an insulating layer.
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device in which a transistor having a MOS structure is formed on a con on insulator (substrate) substrate, and more particularly to a semiconductor device and a method of manufacturing a semiconductor device in which a surface portion of a silicon layer is salicided.

[0002]

2. Description of the Related Art Conventionally, in increasing the speed of a semiconductor device, the parasitic capacitance of a transistor becomes a problem. When the thickness of the silicon layer of the semiconductor device is large, the parasitic capacitance of the formed transistor becomes large, which hinders high speed operation. For this reason, it is desired to reduce the parasitic capacitance by reducing the thickness of the silicon layer. To reduce such parasitic capacitance, an SOI substrate is receiving attention.

The SOI (Silicon on In)
The sullator substrate has a structure in which a thin single-crystal silicon layer is formed on the surface side of the support substrate via an insulating layer. Selective oxidation (Silicon Oxidation of Silicon) is applied to the surface of the single crystal silicon layer of the SOI substrate.
on) to form an element formation region on the surface. Techniques for forming a MOS transistor in the element formation region have been developed.

FIGS. 5, 6 and 7 show a conventional semiconductor device 1.
FIG. 3 is a process chart showing a manufacturing process of the present invention. FIG. 4 is a cross-sectional view showing the conventional semiconductor device 1. The SOI substrate provided with the element formation region 4 has a three-layer structure in which an insulating layer 3 is formed on a supporting substrate 2 and a thin single-crystal silicon 14 is formed on the insulating layer 3 as shown in FIG. It has a structure. Then, a nitride film (Si ₃ N ₄ ) 15 is formed on the thin single crystal silicon 14 at a location where the element formation region 4 is formed by CVD.
(Chemical Vapor Deposition
n) and the like. After the entire surface of the single crystal silicon layer 14 is oxidized, the nitride film 15 is removed. FIG. 5B is a cross-sectional view showing one of the element forming regions 4 after removing the nitride film 15. The surface portion of the single crystal silicon layer 14 is oxidized to become the insulating layer 3. The portion of the single-crystal silicon layer 14 where the nitride film 15 is formed is not oxidized and is kept as single-crystal silicon to form the element formation region 4.

In the element formation region 4 thus formed, M
A transistor having an OS structure is formed. That is, FIG.
As shown in (a), a gate electrode 5 is formed at the center of the surface of the element forming region 4 with a gate insulating film 6 interposed therebetween. Then, as shown in FIG. 6 (b), over the entire surface, SiO ₂
An insulating film 16 is deposited. Then, FIG. 7 (a)
As shown in FIG. 5, the insulating film 16 is removed by anisotropic etching or the like, and a sidewall 10 is formed on the side of the gate electrode 5. Impurity ions are implanted into such an element formation region to form a source region 11 and a drain region 12 as shown in FIG. Thus, M
A transistor having an OS structure is formed.

The gate electrode 5 to which a voltage is applied
When a wiring electrode is directly connected to the surface of the transistor or the surface of the source region 11 or the drain region 12, the operating voltage of the MOS transistor increases because the resistance of the surface of the silicon layer to be connected is large. For this reason, it is necessary to reduce the resistance values of the surfaces of the source region 11, the drain region 12, and the gate electrode 5 to increase the operation efficiency of the MOS transistor. As such a technique, as shown in FIG. 4, a technique of forming a silicide layer 13 on the surface layer of the gate electrode 5 and the surface layer of the source region 11 and the drain region 12 has been developed.

That is, as shown in FIG. 7B, a metal film 18 is formed over the entire surface of the element formation region 4 and heat treatment is performed. Thereby, the gate electrode 5 and the source region 1
1. By alloying the surface of the drain region 12, a silicide layer 13 is formed on the surface of the element forming region 4 as shown in FIG. Thereby, the resistance value of each surface layer can be reduced.

[0008]

However, there have been the following problems in the prior art.

As described above, conventionally, the resistance value of the surface layer is reduced by forming a silicide layer in the surface layer of each of the source region, the drain region, and the gate electrode formed in the element formation region. However, since the thickness of the element formation region is extremely small, the whole or most of the source region and the drain region may be occupied by the silicide layer. When the silicide layer is formed in this manner, there is a problem that the function as a transistor cannot be exhibited because the PN junction is eliminated.

In some cases, the semiconductor device may be multi-layered. However, as described above, the height of the gate electrode is different from the height of the source region and the drain region. For this reason, when depositing the electrode wiring and the like on the upper part, it is necessary to flatten after the deposition, so that the process is troublesome. Further, when openings are formed in the gate electrode, the source region, and the drain region, defocus occurs due to a difference in height, and it is difficult to form a uniform opening. For this reason, the manufacturing process becomes complicated, and the top surface of the processing is complicated.

An object of the present invention has been made to solve the above problems, and even if a silicide layer is formed,
It is an object of the present invention to provide a semiconductor device and a method for manufacturing a semiconductor device, which can secure a source region and a drain region and can increase the speed of a transistor while reducing surface resistance.

Still another object of the present invention is to provide a MOS
It is an object of the present invention to provide a semiconductor device and a method for manufacturing a semiconductor device, in which a surface flattening step and a silicide layer forming step of a transistor having a structure can be performed in a continuous step, and the manufacturing efficiency of a transistor having a MOS structure can be increased. .

[0013]

In order to achieve the above object, a semiconductor device according to the present invention is characterized in that a single crystal silicon layer provided on a supporting substrate via an insulating layer has a plurality of element forming regions formed by isolation regions. A gate electrode provided in the element formation region with an insulating film interposed therebetween, a source region on one side of the gate electrode, and a drain region on the other side, the semiconductor device comprising: The structure includes a silicon layer provided on the drain region and a silicide formed on a surface portion of the silicon layer. By doing so, the resistance value can be reduced by the silicide layer provided on the surface while securing the thickness of the source region and the drain region by the thickness necessary for the transistor operation.
The speed of the formed MOS transistor can be increased, and the operation efficiency of the MOS transistor can be increased.

In the above structure, the silicon layer may be formed at the same height as the gate electrode, and silicide may be formed on a surface layer of the gate electrode. Because of this, even when wiring or the like is deposited on the silicon layer, there is no possibility of distortion,
Further, it can be preferably used for stacking transistors. Further, even when an opening or the like is provided in the gate electrode, the source region, or the drain region, the focal point is the same in each case, so that the gate electrode, the source region, and the drain region can be formed uniformly. Thus, a high-quality semiconductor device can be formed.

In the above structure, the silicide may be formed in a self-aligned manner. Such technology is known as Salicide technology (SALIDE; Self)
-Aligned Silicide). Such a silicide can be formed by depositing a metal film on the surface of the silicon layer and performing a heat treatment. As described above, by forming silicide in a self-aligned manner, a step of depositing a mask becomes unnecessary, and the processing step can be simplified.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming an isolation region in a single crystal silicon layer provided on a support substrate via an insulating layer; A step of dividing the silicon layer into a plurality of element formation regions, a step of forming a gate electrode in the element formation region via an insulating film, a step of forming a sidewall on a side portion of the gate electrode, and a step of covering a surface. Forming a silicon layer, flattening the silicon layer to expose the isolation region, and leaving the silicon layer in a portion corresponding to a source region and a drain region, and forming a metal layer over the surface. Forming a metal silicide on the surface layer of the remaining silicon layer. By doing so, the surface resistance can be reduced while the function of the transistor formed in the element formation region is ensured, so that the transistor can be operated efficiently. Further, as a substrate to which such a method for manufacturing a semiconductor device is applied, an SOI substrate is preferable, but the present invention can also be applied to a case where a transistor is formed in a thin element formation region.

In the above structure, the silicon layer may be planarized by exposing the gate electrode together with the isolation region and forming a metal silicide together with the silicon layer on a surface layer of the gate electrode. By doing so, the flattening step and the salicidation step can be continuously performed, and the manufacturing efficiency can be increased. As a method of flattening the silicon layer, CMP (Chem), which is a polishing technique by a chemical method, is used.
Ical Mechanical polish
g) or RIE (Reacting Ion Etchi) for removing the polycrystalline silicon layer by activating plasma.
ng) is preferred.

In the above structure, the source region and the drain region may be formed by implanting impurity ions after flattening the silicon layer.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device and a method of manufacturing the semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings. In the present embodiment, a transistor having an NMOS structure is formed in an element formation region partitioned by an insulating film which is an isolation region, and the formed NMOS transistor is formed.
A case where a silicide layer is provided on the surface side of a transistor having a structure will be described.

FIG. 1 shows a semiconductor device 2 according to this embodiment.
0 is a sectional view. The semiconductor device 20 has a single crystal silicon layer provided on a supporting substrate 60 made of silicon via an insulating layer 50 made of an oxide film (SiO ₂ ), and the insulating layer 50 serves as an isolation region. The silicon layer is divided into a plurality of element formation regions 22. In FIG. 1, one of the plurality of element forming regions 22 has NM
1 shows a semiconductor device 20 in which a transistor having an OS structure is formed. That is, the element formation region 22
A gate electrode 26 is provided on the center of the surface with a gate insulating film 40 interposed therebetween. Then, the element forming region 22
Comprises a source region 28 on one side of the gate electrode 26 and a drain region 30 on the other side.
The region between the drain region 8 and the drain region 30 is a channel region 29. In the present embodiment, the source region 28 and the drain region 30 are formed by N-type diffusion layers,
The channel region 29 is formed by a P-type diffusion layer,
The transistor has an S structure.

In this embodiment, the polycrystalline silicon layer 24 is provided on the source region 28 and the drain region 30. Further, a silicide layer 32 is formed on the surface layer of the polycrystalline silicon layer 24. Thus, even when the element forming region 22 is very thin, the resistance of the surface layer portion can be reduced while securing the thickness of the source region 28 and the drain region 30 by the thickness necessary for the transistor operation.

The polycrystalline silicon layer 24 is formed at the same height as the gate electrode 26.
A silicide layer 32 is formed on the surface of the gate electrode 26. For this reason, even when wiring and the like are deposited on the polycrystalline silicon layer 24, there is no possibility that distortion occurs, and the present invention can be preferably used for stacking transistors. Further, also in the case where an opening or the like is provided in the gate electrode, the source region, or the drain region, since the height is the same in each case, the focal point is the same, and the gate electrode and the source region and the drain region can be formed uniformly.

The operation of the semiconductor device 20 thus formed is as follows. Gate electrode 26, source region 2
8, a wiring electrode (not shown) is connected to each surface layer of the drain region 30. And the gate electrode 2
The operating voltage is applied to 6. As described above, by providing polysilicon on the source region 28 and the drain region 30, salicide can be achieved even when the element formation region 22 is extremely thin. Such salicidation makes it possible to operate an NMOS transistor having a small resistance value. As described above, N having a small resistance value
Since the MOS transistor can operate, high-speed operation and low-voltage operation can be performed.

A method for manufacturing the semiconductor device 20 according to the present embodiment will be described. In the present embodiment, a case will be described in which the element formation region 22 is formed using a single crystal silicon layer having an SOI structure, a transistor having an NMOS structure is formed in the element formation region 22, and a silicide layer 32 is provided in a surface layer portion. I do. The steps of forming the element formation region 22 and the step of forming the gate electrode 26 are the same as those shown in FIGS.

FIGS. 2 and 3 are process diagrams showing a method for manufacturing the semiconductor device 20 according to the present embodiment. First, FIG.
As shown in (a), the element forming region 22 has an insulating layer (Si
O ₂ ). In the present embodiment,
The element forming region 22 is formed of P-type single crystal silicon. On the center of the surface of the element forming region 22,
A gate electrode 26 made of polysilicon is provided via a gate oxide film 40. As shown in FIG.
Insulating layer 50 which is an isolation region more than the height of gate electrode 26
Are formed higher. The periphery of the gate electrode 26 is covered with an insulating film 41. The insulating film 41 is formed by depositing SiO ₂ over the entire surface of the element forming region 22,
It is formed by removing iO ₂ by anisotropic etching except for the periphery of the gate electrode 26. The insulating film 41 thus formed prevents the gate electrode 26 from short-circuiting with the surroundings.

As shown in FIG. 2B, a polycrystalline silicon layer 24 is deposited over the entire surface of the element forming region 22 on which the gate electrode 26 is formed. The polycrystalline silicon layer 24 formed as described above is evenly removed to the height indicated by the dotted line in FIG. This flattening operation is performed by CMP (Chem), which is a chemical mechanical polishing method.
Ical Mechanical polish
g) or RIE (Reacting Ion Etchi) for removing the polycrystalline silicon layer by activating plasma.
ng) is preferred. In the present embodiment, planarization is performed to a height at which the surface of the gate electrode 26 is exposed. Therefore,
While exposing the insulating layer 50 which is the isolation region,
The polycrystalline silicon layer 24 can be left in portions corresponding to the source region 28 and the drain region 30.
Further, the insulating film 41 provided on the side surface of the gate electrode 26 can be used as the sidewall 42. As described above, since the outer surface of the gate electrode 26 is covered with the insulating film 41,
The surface of the sidewall 42 where the insulating film 41 is flattened also has a predetermined thickness, and the gate electrode 26 and the polycrystalline silicon layer 24 can be separated. This can prevent the gate electrode 26 from short-circuiting with the polycrystalline silicon layer 24.

Then, as shown in FIG. 3A, N-type impurity ions (for example, phosphorus (P), arsenic (As), etc.) are implanted into the element forming regions 22 on both sides of the gate electrode 26, respectively. The region 28 and the drain region 30 are modified into an N-type region. As described above, since the element formation region 22 is formed of the P-type silicon layer, the channel region 29 between the source region 28 and the drain region 30 is formed.
Is held in the P-type region. Thus, a transistor having an NMOS structure can be formed in the element formation region 22. By forming the source region 28 and the drain region 30 in such an element formation region 22, the parasitic capacitance can be reduced, and the speed of the formed transistor can be increased.

Then, as shown in FIG. 3 (b), salicide (SALIDE; Self-Ali) is formed over the entire surface of the polycrystalline silicon layer 24 and the gate electrode 26.
gned Silicide). Salicidation is a technique for forming a silicide layer on the surface of a silicon layer. That is, the polycrystalline silicon layer 24
A metal film 70 of titanium or the like is deposited on the surface of the
The silicide layer 32 is formed on the surface of the gate electrode 26. By doing so, the step of depositing a mask when forming the silicide layer is not required, and the processing efficiency can be improved. As described above, the silicide layer 3
2 is formed in the surface layer of the polycrystalline silicon layer 24 deposited on the source region 28 and the drain region 30. For this reason, the thickness of the source region 28 and the drain region 30 formed in the element formation region 22 can be ensured, and the transistor function formed in the element formation region 22 can be maintained by forming the silicide layer 32, and the surface resistance can be reduced. . Therefore, the formed NMOS transistor can be operated efficiently. As a material for forming the metal film 70, cobalt or tungsten may be used in addition to titanium.

In this embodiment, the case where a transistor having an NMOS structure is formed using a P-type silicon layer has been described. However, the present invention is not limited to this, and a transistor having a PMOS structure can be formed using an N-type silicon layer. It can also be used in the case of manufacturing, and in the case of using a transistor having a CMOS structure.

[0030]

As described above, according to the present invention, a MOS transistor can be formed in a thin element formation region to increase the speed of the transistor, and a silicide layer can be formed on the surface side of the element formation region. Having
The operation efficiency of the MOS transistor can be improved.

Further, in the present invention, a mask is not required when forming the silicide layer, and the silicide layer can be formed in a self-aligned manner.

Further, in the present invention, since the surface resistance can be reduced while ensuring the function of the transistor formed in the element formation region, the transistor can be operated efficiently.

Further, in the present invention, the step of flattening the surface of the MOS-structured transistor and the step of forming the silicide layer can be performed in a continuous step, and the efficiency of manufacturing the MOS-structured transistor can be increased.

[0034]

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a process chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a conventional semiconductor device.

FIG. 5 is a process chart showing a conventional method for manufacturing a semiconductor device.

FIG. 6 is a process chart showing a conventional method for manufacturing a semiconductor device.

FIG. 7 is a process chart showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 2 ... Support substrate 3 ... Insulating layer 4 ... Element formation region 5 ... Gate electrode 6 ... Gate insulating film 7 ... Channel region 10 ... Side wall 11 source region 12 drain region 13 silicide layer 14 single crystal silicon layer 15 nitride film 16 insulating film 18 metal film 20 semiconductor device 22 ... element formation region 24 ... polycrystalline silicon layer 26 ... gate electrode 28 ... source region 29 ... channel region 30 ... drain region 32 ... silicide layer 40 ... gate Insulating film 41 Insulating film 42 Sidewall 50 Insulating layer 60 Supporting substrate 70 Metal film

Continued on the front page F term (reference) 4M104 AA09 BB20 BB25 BB28 CC01 CC05 DD02 DD84 FF14 FF26 GG09 GG10 GG14 HH16 5F110 AA03 AA16 AA18 CC02 DD05 DD13 EE05 EE09 EE14 EE32 FF02 GG02 GG12 HJ01 HK12 HK12 HK12 HK12 HK12 QQ19

Claims (6)

[Claims] A single-crystal silicon layer provided on a supporting substrate with an insulating layer interposed therebetween is divided into a plurality of element forming regions by an isolation region, and a gate electrode provided in the element forming region with an insulating film interposed therebetween; A semiconductor device comprising a source region on one side of the gate electrode and a drain region on the other side, comprising: a silicon layer provided on the source region and the drain region; A semiconductor device comprising: a silicide; 2. The semiconductor device according to claim 1, wherein said silicon layer is formed at the same height as said gate electrode, and silicide is formed on a surface portion of said gate electrode. 3. The semiconductor device according to claim 1, wherein said silicide is formed in a self-aligned manner. 4. A step of forming an isolation region in a single crystal silicon layer provided on a supporting substrate with an insulating layer interposed therebetween, and dividing the single crystal silicon layer into a plurality of element formation regions; Forming a gate electrode through a film, forming a sidewall on the side of the gate electrode, forming a silicon layer covering the surface, flattening the silicon layer to expose the isolation region Together with the step of leaving the silicon layer in a portion corresponding to the source region and the drain region, and after forming a metal layer covering the surface, a step of forming a metal silicide on the surface portion of the remaining silicon layer A method for manufacturing a semiconductor device, comprising: 5. The flattening of the silicon layer includes exposing the gate electrode together with the isolation region, and forming a metal silicide together with the silicon layer in a surface layer of the gate electrode. Of manufacturing a semiconductor device. 6. The method according to claim 4, wherein the source region and the drain region are formed by implanting impurity ions after flattening the silicon layer.