JP2001331126A - Electro-optical device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase a pixel opening rate and also a storage capacity at the same time, and moreover, decrease degradation of a display picture which is caused by irregularities generated on an alignment film surface near pixel electrodes, in an electro-optical device of a type provided with an intermediate conductive layer for relaying between pixel electrodes and TFTs for switching the pixels. SOLUTION: The electro-optical device is provided with TFTs (30), data lines (6a), scanning lines (3a), capacitance lines (3b), a 1st intermediate conductive layer (80), a 2nd intermediate conductive layer (180), and pixel electrodes (9a). First contact holes (8a) for connecting drains of TFTs with the 1st intermediate conductive layer are opened at the position superimposed on the data lines is viewed from the top.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention belongs to the technical field of an electro-optical device of an active matrix drive system, and particularly to a pixel electrode and a thin film transistor (Thin) for pixel switching.
Film Transistor (hereinafter appropriately referred to as TFT), which belongs to the technical field of an electro-optical device of a type in which an intermediate conductive layer for obtaining good electrical conductivity is provided in a laminated structure on a substrate.

[0002]

2. Description of the Related Art Conventionally, in an electro-optical device of an active matrix drive system using a TFT drive, when a scan signal is supplied to a gate electrode of a TFT via a scan line, a TF is used.
T is turned on, and an image signal supplied to the source region of the semiconductor layer via the data line is supplied to the pixel electrode via the TFT. The supply of such an image signal is performed at each T
Since only a very short time is performed for each pixel electrode via the FT, in order to hold the voltage of the supplied image signal for a much longer time than the time in which the pixel is turned on,
Generally, a storage capacitor is added to each pixel electrode.

On the other hand, in this type of electro-optical device, a scanning line, a data line and the like are formed between a conductive film such as an ITO film forming a pixel electrode and a semiconductor layer forming a TFT for pixel switching. Various conductive films and a gate insulating film and an interlayer insulating film for electrically insulating these conductive films from each other are laminated, and the distance between the pixel electrode and the semiconductor layer is long, for example, about 1000 nm. Therefore, it is technically difficult to electrically connect the pixel electrode and the semiconductor layer with one contact hole. Therefore, a technique has been developed in which an intermediate conductive layer is provided between interlayer insulating films, and the intermediate conductive layer is relayed to electrically connect the pixel electrode and the semiconductor layer.

[0004]

In this type of electro-optical device, there is a general demand for a high quality display image. To this end, the pixel aperture ratio is increased while the pixel pitch is reduced. (That is, in each pixel, it is extremely important to widen the opening area through which the display light is transmitted with respect to the light-blocking area through which the display light is not transmitted.)

In particular, the provision of the intermediate conductive layer as described above not only increases the number of manufacturing steps, but also increases the number of layers and the number of contact holes to make the laminated structure more complicated. As a result, there is a problem that it becomes more difficult to produce the above-described storage capacitance, or it becomes difficult to secure an area for forming a contact hole. When the number of necessary contact holes is increased by providing the intermediate conductive layer in this way, the surface of the interlayer insulating film located above the substrate on the substrate due to the presence of the contact holes causes irregularities, Specifically, unevenness occurs on the surface of the pixel electrode and the alignment film formed thereon. When irregularities are generated on the surface of the alignment film in the vicinity of the pixel electrode, a malfunction occurs due to a poor alignment of a liquid crystal, which is an example of an electro-optical material. As a result of these,
Causing display defects such as a decrease in contrast ratio,
There is a problem that the image quality is greatly reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is possible to increase the pixel aperture ratio and reduce the unevenness of the surface of the alignment film near the pixel electrode.
It is an object to provide an electro-optical device capable of displaying high-quality images.

[0007]

(1) In order to solve the above problems, an electro-optical device according to the present invention is electrically connected to a thin film transistor provided on a substrate and a drain region of a semiconductor layer of the thin film transistor. A plurality of wirings provided between a semiconductor layer of the thin film transistor and the pixel electrode via an insulating film, and electrically connecting a drain region of the semiconductor layer of the thin film transistor and the pixel electrode. An intermediate conductive layer, and a first contact hole that electrically connects a drain region of a semiconductor layer of the thin film transistor and the intermediate conductive layer below a region of at least one of the plurality of wirings. Features.

According to the electro-optical device of the present invention, since the drain region of the semiconductor layer and the pixel electrode are electrically connected via the intermediate conductive layer, even if the film thickness therebetween is large, Both can be satisfactorily connected by two contact holes having a relatively small diameter. The area where each contact hole is formed can be made smaller, and the pixel aperture ratio can be increased.

In addition, since the first contact hole is formed under the area of at least one wiring, irregularities are not generated in the opening area of each pixel due to the presence of the first contact hole. As a result, the rubbing process in the vicinity of the pixel electrode can be performed uniformly, and the layer thickness of the electro-optical material can be made uniform. As a result, it is possible to reduce malfunctions such as poor alignment in electro-optical materials such as liquid crystals.

As described above, according to the electro-optical device of the present invention, the aperture ratio of a pixel can be increased, and the quality of a displayed image is degraded due to the occurrence of irregular irregularities on the surface of an alignment film near a pixel electrode. Can be reduced. As a result, a bright, high contrast ratio, and high-quality image display can be performed.

(2) In one aspect of the electro-optical device of the present invention, a diameter of the first contact hole is smaller than a diameter of a second contact hole for electrically connecting the intermediate conductive layer and the pixel electrode. It is characterized by the following.

According to this aspect, the second conductive layer is formed by the intermediate conductive layer.
This prevents penetration of the etching when the contact hole is opened. Further, by making the diameter of the first contact hole smaller than the diameter of the second contact hole, it becomes possible to narrow the non-pixel opening region.

(3) In another aspect of the electro-optical device of the present invention, at least one of the plurality of wires is a data line electrically connected to a source region of a semiconductor layer of the thin film transistor. The first contact hole may be located below a region of the data line.

According to this aspect, the first pixel is provided in the non-pixel opening region.
Since the contact holes can be arranged, irregularities generated on the surface of the alignment film can be reduced.

(4) In another aspect, it is preferable that the first contact hole is arranged near the intersection of the data line and the scanning line.

According to this structure, since the data line and the scanning line are arranged in the vicinity of the intersection, the unevenness generated on the surface of the alignment film can be reduced in a relatively large area, and the rubbing process near the pixel electrode can be uniformly performed. And alignment defects of the liquid crystal layer can be reduced.

(5) In another aspect, at least one of the plurality of wirings forms a scanning line arranged to intersect the data line, and the intermediate conductive layer is formed of the data line. It is desirable to extend from the region along the scanning line.

According to this structure, since the intermediate conductive layer extends along the scanning line from the region of the data line, the positions of the first contact hole and the second contact hole are set along the data line and the scanning line. Since it can be formed in a region, it can contribute to miniaturization of the pixel pitch.

(6) Further, a second contact hole for electrically connecting the intermediate conductive layer and the pixel electrode is provided in an extending portion of the intermediate conductive layer arranged along the scanning line. desirable.

According to this structure, the second contact hole having a smaller diameter than the conventional contact hole for connecting the drain region and the pixel electrode.
Since the contact holes are arranged in the extending portions along the scanning lines, it is possible to reduce the unevenness generated on the surface of the alignment film while reducing the spread of the non-pixel opening region near the scanning lines.

(7) Further, it is preferable that the second contact hole is located substantially at the center between adjacent data lines.

According to this structure, the adverse effect of the unevenness of the alignment film on the second contact hole can be made symmetrical for each pixel, and the display failure of each pixel when all the pixels are viewed macroscopically can be averaged. .

(8) In another aspect, the intermediate conductive layer extends along the data line.

According to this structure, the region of the first contact hole can be covered with the intermediate conductive layer without expanding the non-pixel opening region below the data line.

(9) In another aspect of the electro-optical device according to the present invention, at least one of the plurality of wirings is a capacitance line extending below the intermediate conductive layer, and the capacitance line is the capacitance line. It is characterized by extending so as to avoid the region of one contact hole.

According to this aspect, since the capacitance line extends avoiding the region of the first contact hole having a smaller diameter than the conventional contact hole connecting the drain region and the pixel electrode, the capacitance area is secured. In addition, unevenness generated on the surface of the alignment film can be reduced.

(10) In another aspect of the electro-optical device according to the present invention, a depth of the first contact hole is smaller than a depth of a second contact hole between the intermediate conductive layer and the pixel electrode. I do.

According to this aspect, in the region of the first contact hole, irregularities generated on the surface of the alignment film can be reduced.

(11) In another aspect of the electro-optical device of the present invention, the intermediate conductive layer is at least partially opposed to a capacitor electrode made of the same film as the scanning line via an interlayer insulating film. It is characterized by the following.

According to this aspect, since the intermediate conductive layer is opposed to the capacitor electrode formed of the same film as the scanning line via the interlayer insulating film, it is possible to add a storage capacitor connected to the pixel electrode. Can be. That is, since the storage capacitor can be constructed three-dimensionally not only below the capacitor electrode but also above the capacitor electrode, the storage capacitance can be increased by effectively using the limited light-shielding region.

(12) In another aspect, the second contact hole may be formed so as to be opened at a position overlapping the capacitor electrode when viewed in plan.

According to this configuration, the intermediate conductive layer portion at the plane position where the second contact hole is opened also overlaps the capacitor electrode, that is, is disposed opposite to the capacitor electrode via the insulating film. In addition, a storage capacitor can be constructed even in a plane region where the second contact hole is opened.

(13) In another aspect, the capacitance electrode is:
A portion extending along the scanning line and a portion extending along the data line from a portion intersecting the data line when viewed in a plan view, wherein the intermediate conductive layer has an interlayer between at least a part of the capacitor electrode; They are stacked via an insulating film.

According to this structure, in the light-shielding region along the data line, the electrode extending from the drain region of the semiconductor layer and the capacitor electrode can be arranged to face each other, and the capacitor electrode and the intermediate conductive layer can be arranged in a manner opposed to each other. Can be arranged to face each other. Therefore, a three-dimensional storage capacitor can be constructed also in the light-shielded area along the data line.

(14) In another aspect of the electro-optical device of the present invention, the intermediate conductive layer is made of a light-shielding conductive film.

According to this aspect, the channel region of the thin film transistor and its adjacent region can be shielded from light by the intermediate conductive layer made of the light-shielding conductive film. That is, generally, when light enters a channel region of a semiconductor layer included in a thin film transistor or a region adjacent to the channel region, a leakage current occurs due to photoexcitation. Accordingly, characteristics of the thin film transistor in an off state change. On the other hand, according to the present invention, such a change in transistor characteristics due to light incidence can be prevented by utilizing the intermediate conductive layer.

(15) In another aspect, the intermediate conductive layer may be configured to define a part of the light shielding region.

According to this configuration, for example, a light-shielding film for defining a light-shielding region is formed on the opposite substrate, which is the other substrate disposed opposite to the one substrate on which the pixel electrodes and the like are formed, or the light-shielding region is formed. It is possible to at least partially eliminate the case where the width of the data line is widened for the purpose of defining, or the case where a built-in light-shielding film for defining the light-shielding region is separately formed in one substrate. That is, since the light-shielding film or the like for defining the light-shielding region is at least partially unnecessary, the transmittance of the electro-optical device does not decrease due to misalignment at the time of bonding one substrate and the other substrate. . Thereby, the failure of the electro-optical device can be significantly reduced.

(16) Further, the intermediate conductive layer includes a portion extending along the data line when seen in a plan view, and a part of the light shielding region in a direction along the data line is defined. May be configured.

According to this structure, a light-shielding film for defining the light-shielding region is formed on the counter substrate in a portion where the light-shielding region is defined by the intermediate conductive layer along the data line, or the light-shielding region is defined. Therefore, it is possible to eliminate the need to increase the width of the data line or to separately form the built-in light shielding film. Thereby, the variation in transmittance of the electro-optical device can be significantly reduced.

(17) Further, the capacitor electrode has a portion extending along the data line as viewed in plan, and at a position along the data line, each has a width W of the data line.
d, the width Wc of the capacitor electrode, and the width Wm of the intermediate conductive layer portion extending along the data line, Wd <Wc
<Wm may be established.

According to this structure, the data line and the intermediate conductive layer can double-block incident light from the opposing substrate side of the pair of substrates. Here, as a material of a data line for supplying an image signal, an Al (aluminum) film is generally used with priority given to a low wiring resistance.
In the case of the 1 film, it is a light-shielding film and at the same time a reflective film having a very high reflectance. Therefore, when the thin film transistor is shielded only by the data line made of the Al film, the projected light or return light inclined with respect to the substrate surface is reflected on the inner surface of the data line (that is, the surface facing the thin film transistor). As a result, multiple reflection occurs in the laminated structure, which eventually causes a problem of reaching the channel region and its adjacent region. However, according to the present invention, the intermediate conductive layer provided under the data line is formed of a low-reflection high-melting point metal film or a polysilicon film to attenuate the multiple reflection light due to the internal reflection as described above. It is possible to adopt a configuration that performs On the other hand, a larger storage capacitor can be constructed by the capacitor electrode and the intermediate conductive layer which are wider than the data line.

(18) Further, when viewed two-dimensionally, an edge portion of the pixel electrode along the data line may be configured to overlap an edge portion of the intermediate conductive layer.

According to this structure, the data line width can be reduced. Thereby, the parasitic capacitance between the data line and the pixel electrode can be minimized. As a result, it is possible to significantly reduce display defects such as a decrease in contrast ratio, crosstalk, and ghost.

(19) In another aspect of the electro-optical device according to the present invention, the semiconductor layer is formed below a region of the data line.

According to this configuration, a region for electrically connecting the semiconductor layer and the pixel electrode can be secured, and the non-opening region along the scanning line can be formed at a narrow pitch.

(20) Further, the first contact hole is formed at a position symmetric with respect to a third contact hole connecting the source region of the semiconductor layer and the data line with respect to a channel region of the semiconductor layer. It is characterized by being performed.

According to this configuration, the shape of the step formed by the multilayer wiring can be made symmetrical with respect to the data line, and the difference in light leakage due to the rotation direction of the liquid crystal can be eliminated.

(21) Further, below the semiconductor layer,
A second contact hole for electrically connecting the intermediate conductive layer and the pixel electrode has a lower light-shielding film projecting from the scanning line as viewed in plan, and the lower light-shielding film is formed as It is characterized by being located in a region protruding from a scanning line.

According to this structure, since the semiconductor layer is not formed along the scanning line, the non-opening area along the scanning line can be narrowed, and the intermediate conductive layer and the pixel electrode can be electrically connected. it can.

(22) According to another electro-optical device of the present invention, a thin film transistor provided on a substrate, a data line electrically connected to a source region of a semiconductor layer of the thin film transistor, and a thin film transistor of the thin film transistor A pixel electrode electrically connected to the drain region, a light-shielding intermediate conductive layer electrically connecting the drain region of the semiconductor layer of the thin film transistor and the pixel electrode, and provided along the data line; A capacitance line located in a drain region of a semiconductor layer of a thin film transistor, a light-shielding film formed of the same film as the intermediate conductive layer, and an electric connection between the capacitance line and the light-shielding film under a region of the data line. And a contact hole to be formed.

According to this aspect, by covering the contact hole connecting the light shielding film and the capacitance line with the data line,
In the region of the contact hole, unevenness generated on the surface of the alignment film can be reduced. Further, the light-shielding film can be formed as a capacitor electrode to increase the capacity.

These effects and other advantages of the present invention are:
This will be apparent from the embodiment described below.

[0054]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a configuration of a liquid crystal device which is a first embodiment of the electro-optical device according to the present invention.
This will be described with reference to FIG. FIG. 1 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels formed in a matrix forming an image display area of the electro-optical device. FIG. 2 is a diagram illustrating data lines, scanning lines, pixel electrodes, and the like. TF
FIG. 3 is a plan view of a plurality of pixel groups adjacent to each other on the T array substrate, and FIG. 3 is a cross-sectional view taken along line AA ′ of FIG. In FIG. 3, the scale of each layer and each member is different so that each layer and each member have a size that can be recognized in the drawing. FIG. 4 is a diagram showing one example of a capacitance line and a scanning line, showing a plane pattern of a capacitance line and a scanning line in the present embodiment (FIG. 4A) in comparison with a plane pattern of the comparative example (FIG. 4B). It is a top view which expands and shows a part.

In FIG. 1, a plurality of pixels which are formed in a matrix and form an image display area of the electro-optical device according to the present embodiment have a TF for controlling a pixel electrode 9a.
T30 is formed, and the data line 6a to which an image signal is supplied is electrically connected to the source of the TFT 30. The image signals S1, S2,
, Sn may be supplied line-sequentially in this order.
A plurality of adjacent data lines 6a may be supplied for each group. Further, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,.
m are applied line-sequentially in this order. The pixel electrode 9a is electrically connected to the drain of the TFT 30. By closing the switch of the TFT 30, which is a switching element, for a certain period, the image signals S1, S2,... Write at a predetermined timing. The image signals S1, S2 of a predetermined level written in the liquid crystal through the pixel electrode 9a,
, Sn are held for a certain period of time between a counter electrode (described later) formed on a counter substrate (described below). The liquid crystal is
By changing the orientation and order of the molecular assembly according to the applied voltage level, the light is modulated to enable a gray scale display. In the normally white mode, the transmitted light quantity of the incident light decreases according to the applied voltage, and in the normally black mode, the transmitted light quantity of the incident light increases according to the applied voltage. Light having a contrast ratio according to an image signal is emitted from the electro-optical device. Here, in order to prevent the held image signal from leaking,
In parallel with the liquid crystal capacitance formed between the pixel electrode 9a and the counter electrode, a dielectric substance is formed between the capacitance electrode electrically connected to the pixel electrode 9a and the capacitance electrode that is a part of the capacitance line 3b. A storage capacitor 70 is added via the film. For example, the voltage of the pixel electrode 9a is held by the storage capacitor 70 for a time that is three orders of magnitude longer than the time during which the source voltage is applied. Thereby, the holding characteristics are further improved, and an electro-optical device having a high contrast ratio can be realized.

In FIG. 2, a plurality of transparent pixel electrodes 9 are arranged in a matrix on a TFT array substrate of the electro-optical device.
a (the outline is indicated by a dotted line portion 9a ′), and the data line 6a, the scanning line 3a, and the capacitor line 3b are provided along the vertical and horizontal boundaries of the pixel electrode 9a. The pixel electrode 9a is a first electrode forming an example of an intermediate conductive layer.
Via the intermediate conductive layer 80, the first contact hole 8a
In addition, the semiconductor layer 1a is electrically connected to a later-described drain region via the second contact hole 8b. The data line 6a is electrically connected to a source region described later in the semiconductor layer 1a made of a polysilicon film or the like via the third contact hole 5. In addition, the scanning line 3a is arranged so as to face the channel region 1a '(the hatched region on the lower right in the figure) of the semiconductor layer 1a.
Functions as a gate electrode. Thus, the scanning line 3a
And the data line 6a intersect, the capacitance line 3b provided with the TFT 30 in which the scanning line 3a is opposed to the channel region 1a 'as a gate electrode is provided in the channel region 1a'.
and a portion extending substantially linearly in parallel with the scanning line 3a and a portion intersecting the data line 6a from the vicinity of the third contact hole 5 related to a pixel adjacent along the data line 6a. An extending portion.

In FIG. 2, a region shown by a thick line in the figure is a first light-shielding film 11a, and this first light-shielding film 11a is arranged at least below the semiconductor layer 1a of the TFT 30. More specifically, in FIG. 2, the first light-shielding films 11a are each formed in a striped shape along the scanning lines 3a, and the portions that intersect with the data lines 6a are formed wide at the bottom in the figure. The wide portion is provided at a position covering the channel region 1a 'of each TFT and its adjacent region as viewed from the TFT array substrate side. The first light-shielding film 11
a may be formed so as to extend below the scanning line 3a in a stripe shape in the direction along the scanning line 3a as shown in the present embodiment, or the data line may be formed in the direction along the data line 6a. The lower part of 6a may be formed to extend in stripes. Alternatively, they may be formed so as to extend below each other in a grid along the scanning lines 3a and the data lines 6a. In addition, the first light shielding film 11a
A pixel electrode 9a extending outside the image display area in which a plurality of pixels are formed in a matrix, and a negative power supply supplied to peripheral circuits such as a scanning line driving circuit and a data line driving circuit for driving the electro-optical device; It is preferable to be electrically connected to an optimal constant potential among a constant potential source such as a positive power source, a ground power source, and a constant potential source supplied to the counter electrode. As described above, by fixing the first light-shielding film 11a to a constant potential, malfunction of the TFT 30 can be prevented.

In this embodiment, in particular, the first contact hole 8a for electrically connecting the drain region 1e and the first intermediate conductive layer 80 is provided below the data line 6a. The second contact hole 8b for electrically connecting the pixel electrode 9a is connected to the adjacent data line 6a.
It is provided on the capacitance line 3b near the center therebetween.
An island-shaped second intermediate conductive layer 180 made of the same film as the first intermediate conductive layer 80 is formed along the data line 6a. The second intermediate conductive layer 180 is overlapped on a portion of the capacitor line 3b extending along the data line 6a.
The intermediate conductive layer 180 and the capacitor line 3b are electrically connected to each other by a contact hole 18a provided below the data line 6a. The capacitance line 3b is a light-shielding region that intersects the data line 6a in a region below the data line 6a where the first contact hole 8a is formed, and is formed so as to avoid the first contact hole 8a. Line 3b
Are not electrically connected to the first contact hole 8a.

As shown in the cross-sectional views of FIGS. 2 and 3, the channel region 1a 'is arranged corresponding to the intersection of the scanning line 3a and the data line 6a. Further, a high-concentration source region 1d, a low-concentration source region 1b composed of the semiconductor layer 1a,
The channel region 1a ', the low-concentration drain region 1c, and the high-concentration drain region 1e are arranged so as to overlap the data line 6a and to be covered by the data line. Further, the high-concentration source region 1d, the low-concentration source region 1b, the channel region 1a ', the low-concentration drain region 1c and the high-concentration drain region 1e are located below the data line 6a extending to one side with the scanning line 3a interposed therebetween. 1d and a low-concentration source region 1b are arranged, and a low-concentration drain region 1c and a high-concentration drain region 1e are provided below a data line 6a extending to the other side.
Is arranged. Further, the high concentration drain region 1e is connected to the first intermediate conductive layer 80 through the first contact hole 8a.
The first intermediate conductive layer 80 is electrically connected to the pixel electrode 9a via the second contact hole 8b, and the high-concentration source region 1d is electrically connected to the data line 6a via the third contact hole 5. It is connected to the. Since the first contact hole 8a and the third contact hole 5 are formed so as to overlap the data line 6a serving as a non-display area, a decrease in aperture ratio due to the contact hole can be prevented. In addition, the presence of the contact holes can prevent the occurrence of irregular irregularities in the opening region of each pixel. Further, since the semiconductor layer is arranged so as to overlap with the data line 6a, the data line functions as a light-shielding film and can prevent light from entering the semiconductor layer.

Next, as shown in the cross-sectional view of FIG. 3, the electro-optical device includes a transparent TFT array substrate 10 as an example of a substrate and a transparent counter substrate 20 disposed opposite to the TFT array substrate. . The TFT array substrate 10 is made of, for example, a quartz substrate, a glass substrate, or a silicon substrate.
Is made of, for example, a glass substrate or a quartz substrate. The pixel electrode 9a is provided on the TFT array substrate 10, and an alignment film 16 on which a predetermined alignment process such as a rubbing process is performed is provided above the pixel electrode 9a. The pixel electrode 9a is, for example,
It is made of a transparent conductive film such as an ITO (Indium Tin Oxide) film. The alignment film 16 is made of, for example, an organic film such as a polyimide film.

On the other hand, a counter electrode 21 is provided on the entire surface of the counter substrate 20, and an alignment film 22 on which a predetermined alignment process such as a rubbing process is performed is provided below the counter electrode 21. I have. The counter electrode 21 is made of, for example, a transparent conductive film such as an ITO film. The alignment film 22 is made of an organic film such as a polyimide film.

Each pixel electrode 9 is provided on the TFT array substrate 10.
A pixel switching TFT 30 that controls switching of each pixel electrode 9a is provided at a position adjacent to the pixel electrode 9a.

As shown in FIG. 3, the opposing substrate 20 is further provided with a second light shielding film 23 in a light shielding region of each pixel. As will be described in detail later, the second light-shielding film 23 and the like allow incident light from the side of the counter substrate 20 to cause the channel region 1a 'of the semiconductor layer 1a of the pixel switching TFT 30, the low-concentration source region 1b and the low-concentration drain region. There is no intrusion into the region adjacent to the channel region 1a 'including 1c.
Further, the second light-shielding film 23 has a function of improving a contrast ratio and preventing color mixture of color materials when a color filter is formed.

The space between the TFT array substrate 10 and the opposing substrate 20, which is configured as described above and in which the pixel electrode 9a and the opposing electrode 21 face each other, is placed in a space surrounded by a sealing material described later. A liquid crystal, which is an example of an optical material, is sealed, and a liquid crystal layer 50 is formed. The liquid crystal layer 50 has the alignment film 16 in a state where no electric field is applied from the pixel electrode 9a.
A predetermined orientation state is obtained by means of and. The liquid crystal layer 50
For example, it is composed of a liquid crystal in which one or several kinds of nematic liquid crystals are mixed. The sealing material is an adhesive made of, for example, a photo-curing resin or a thermosetting resin for bonding the TFT array substrate 10 and the opposing substrate 20 around them,
A gap material, such as glass fiber or glass beads, for adjusting the distance between the two substrates to a predetermined value is mixed.

Further, as shown in FIG. 3, a first light shielding film 11a is provided between the TFT array substrate 10 and each pixel switching TFT 30 at a position facing each of the pixel switching TFTs 30. First light shielding film 1
1a is preferably a non-transparent high melting point metal such as Ti (titanium), Cr (chromium), W (tungsten), Ta
(Tantalum), Mo (molybdenum), Pb (lead), and the like, and are composed of a metal simple substance, an alloy, a metal silicide, or the like. With such a material, the first light-shielding film 11a can be prevented from being broken or melted by the high-temperature treatment in the process of forming the pixel switching TFT 30. Since the first light-shielding film 11a is formed, the channel region 1a ', the low-concentration source region 1b, and the low-concentration drain region of the pixel switching TFT 30 in which the reflected light from the TFT array substrate 10 easily excites light. 1c can be prevented beforehand, and a pixel-switching T
The characteristics of the FT 30 do not change.

Further, a base insulating film 12 is provided between the first light shielding film 11a and the plurality of pixel switching TFTs 30. The base insulating film 12 is formed by forming the semiconductor layer 1a constituting the pixel switching TFT 30 into a first light shielding film 11a.
It is provided to electrically insulate from the surface. Further, the base insulating film 12 is formed on the entire surface of the TFT array substrate 10 so that the pixel switching TFT 30 is formed.
It also has a function as a base film for the purpose. That is, TFT
It has a function of preventing deterioration of the characteristics of the pixel switching TFT 30 due to roughness at the time of polishing the surface of the array substrate 10 or contamination remaining after washing. The base insulating film 12 is made of, for example, NSG (non-doped silicate glass), PSG
(Phosphorus silicate glass), high insulating glass such as BSG (boron silicate glass), BPSG (boron phosphor silicate glass), or a silicon oxide film, a silicon nitride film, or the like. The first light-shielding film 1 is formed by the base insulating film 12.
It is also possible to prevent a situation in which 1a contaminates the pixel switching TFT 30 and the like.

As shown in FIGS. 2 and 3, the capacitance line 3b made of the same conductive polysilicon film as the scanning line 3a has a lower portion extending from the drain region 1e of the semiconductor layer 1a. It has a portion which is arranged to face the capacitor electrode 1f via the insulating thin film 2 and functions as a second capacitor electrode. As a result, a large storage capacitor 7 is formed by using the insulating thin film 2 including the gate insulating film constituting the TFT 30.
0 can be formed. Further, a part of the capacitance line 3b is on the upper side with respect to a part of the first intermediate conductive layer 80.
They are arranged to face each other with the first interlayer insulating film 81 interposed therebetween. By reducing the thickness of the first interlayer insulating film 81, a larger storage capacitor 70 can be formed. in this way,
Not only below the capacitance line 3b but also above the capacitance line 3b,
Since the storage capacitor 70 can be constructed three-dimensionally, the storage capacitor 70 can be increased by effectively using the limited light-shielded area.

In the present embodiment, the capacitor line 3b is formed by extending the second capacitor electrode made of the same film as the scanning line 3b. However, according to this embodiment, no dedicated wiring is required. This is advantageous without increasing the number of steps. When the capacitance line 3b cannot be formed with the same film as the scanning line 3b, a second capacitance electrode is formed in an island shape for each pixel, and a constant potential is supplied to the second capacitance electrode. The wiring may be used instead. In this case, the first light shielding film 11 is provided for each pixel.
It is preferable to electrically connect a to the second capacitor electrode. The second capacitor electrode includes a constant potential source such as a negative power source and a positive power source supplied to a peripheral circuit (eg, a scanning line driving circuit, a data line driving circuit, and the like) for driving the electro-optical device, a ground power source, a counter power source, and the like. Since the optimum constant potential is supplied from the constant potential sources supplied to the electrodes, a stable storage capacitor 70 can be constructed between the first capacitor electrode 1f and the intermediate conductive layer 80.

In this embodiment, as shown particularly in FIGS. 2 and 3, the first contact hole 8a is opened at a position overlapping the data line 6a in plan view. Accordingly, there is a first contact hole 8a that connects the semiconductor layer 1a and the first intermediate conductive layer 80 located below and above the conductive polysilicon film forming the scanning line 3a and the capacitance line 3b, respectively. Also, the scanning lines 3a and the capacitance lines 3b are connected to the first contact holes 8 using the light-shielding region extending along the data lines 6a.
It becomes easy to wire avoiding a. Figure 4 shows this situation.
FIG.

As in the comparative example shown in FIG.
In the case where the first contact hole 8a 'is formed in a region where the scanning line 3a' and the capacitor line 3b 'which do not overlap with the data line 6a' are arranged side by side, the first contact hole 8a 'is formed. Avoid the capacitor line 3b 'and the scanning line 3
a ′ needs to be constricted around the first contact hole 8a ′. However, if the constricted portion is large, the capacitance line 3
The wiring width of b ′ and the scanning line 3a ′ is locally reduced, and the wiring resistance is increased. This causes display defects such as signal delay and crosstalk. Therefore, the scanning line 3
The width W 'of the light shielding area in the a' direction is larger than the width W of the light shielding area in the scanning line 3a direction in this embodiment shown in FIG. 4A (that is, W '> W). That is, compared to the comparative example, in the present embodiment, it is possible to increase the opening area of each pixel by the extent that the width W of the light shielding area in the scanning line 3a direction is narrow.

Further, as shown in FIG.
By providing the first contact hole 8a at the intersection of the light shielding area in the direction a and the light shielding area in the scanning line 3a direction,
Due to the existence of the contact hole 8a and the existence of the capacitance line 3b which is routed avoiding the contact hole 8a, the contact hole 8a is located above them (the alignment film 1
6) can be reduced. Further, it is separated from the opening area of the pixel. For this reason, the influence of irregular irregularities caused by opening the first contact hole 8a can be efficiently reduced. If the unevenness of the surface of the alignment film 16 in the vicinity of the pixel electrode 9a is reduced as described above, the rubbing process in the vicinity of the pixel electrode 9a can be performed uniformly, and the thickness of the liquid crystal layer 50 can be made uniform. As a result, poor alignment of the liquid crystal layer 50 can be reduced.

Further, the portion of the capacitor line 3b extending along the scanning line 3a has a portion corresponding to the portion of the second capacitor electrode which is disposed opposite to the first capacitor electrode 1f by the amount of no constriction for avoiding the first contact hole 8a. The area can be increased, and the storage capacitance 70 that can be constructed by the second capacitance electrode and the first capacitance electrode 1f can be increased.

In this embodiment, as shown in FIG.
The second contact hole 8b is provided with the scanning line 3a in plan view.
Is opened substantially at the center between two adjacent data lines 6a in the light-shielding region of each pixel along. For this reason, the unevenness of the alignment film 16 on the second contact hole 8b can be arranged near the center of the light-shielding region along one side of the opening region of each pixel. As a result, the adverse effect of the unevenness of the surface of the alignment film 16 on the second contact hole 8b can be made symmetrical for each pixel, and the display failure of each pixel when all the pixels are viewed macroscopically can be averaged.

As described above, in the present embodiment, the degree of freedom regarding the opening position of the second contact hole 8b is high, and
The second contact hole 8b can be opened at any position on the intermediate conductive layer 80 as long as it does not overlap with the data line 6a.

For this reason, in the present embodiment, the storage capacitor 70 is formed in the plane region where the second contact hole 8b is opened by opening the second contact hole 8b at a position overlapping the capacitance line 3b. Is advantageous.

Note that the insulating thin film 2 as one dielectric film in the storage capacitor 70 is nothing but the gate insulating film of the TFT 30 formed on the polysilicon film by high-temperature oxidation or the like. The first interlayer insulating film 81 as another dielectric film can be formed as thin as the insulating thin film 2. Therefore, by making these dielectric films thin, a large-capacity storage capacitor 70 can be constructed in a much smaller area.

As described above, according to the electro-optical device of the present embodiment, it is possible to increase the pixel aperture ratio and at the same time to increase the storage capacitance 70, and furthermore, the surface of the alignment film 16 near the pixel electrode 9a has an irregular surface. It is possible to reduce the deterioration of the quality of the displayed image due to the occurrence of the unevenness. As a result, it is possible to display a high-quality image that is bright, has a high contrast ratio, and has reduced display defects such as flicker, ghost, and crosstalk.

Referring again to FIG. 3, the pixel switching T
The FT 30 has an LDD (Lightly Doped Drain) structure, and includes a scanning line 3a and a channel region 1 of a semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a.
a ', the insulating thin film 2 for insulating the scanning line 3a from the semiconductor layer 1a, the data line 6a, and the low concentration source region 1 of the semiconductor layer 1a.
b and a low-concentration drain region 1c, a high-concentration source region 1d of the semiconductor layer 1a, and a high-concentration drain region 1e. A plurality of pixel electrodes 9 are provided in the high-concentration drain region 1e.
A corresponding one of a is connected via the first intermediate conductive layer 80. In the present embodiment, in particular, the data line 6a
Is formed of a light-shielding and conductive thin film such as a low-resistance metal film such as Al or an alloy film such as metal silicide.

The first interlayer insulating film 81 provided on the scanning line 3a and the capacitor line 3b has a third contact hole 5 and a high concentration drain region 1e leading to the high concentration source region 1d.
The first contact holes 8a are formed respectively.

On first interlayer insulating film 81, first intermediate conductive layer 80 connected to high-concentration drain region 1e via first contact hole 8a, and capacitor line 3b via contact hole 18a. The second intermediate conductive layer 180 is formed.

On the first intermediate conductive layer 80, the second interlayer insulating film 4 is formed. A data line 6a is formed on the second interlayer insulating film 4, and the data line 6a is electrically connected to the high-concentration drain region 1d via a third contact hole 5 opened in the second interlayer insulating film 4. Connected.

Further, the data line 6a and the second interlayer insulating film 4
A third interlayer insulating film 7 in which a second contact hole 8b to the first intermediate conductive layer 80 is formed is formed thereon.
The pixel electrode 9a is electrically connected to the first intermediate conductive layer 80 via the second contact hole 8b. The pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 7 configured as described above.

The pixel switching TFT 30 preferably has an LDD structure as described above, but may have an offset structure in which impurities are not implanted into the low-concentration source region 1b and the low-concentration drain region 1c.
A high concentration source region 1d and a high concentration drain region 1e in a self-aligned manner.
It may be FT.

In the present embodiment, the gate electrode of the pixel switching TFT 30 which is a part of the scanning line 3a is connected between the high-concentration source region 1d and the high-concentration drain region 1e.
Although only the single gate structure is used, two or more gate electrodes may be provided between them. When a TFT is formed with a dual gate or a triple gate or more as described above, a leak current at a junction between a channel and a source / drain region can be prevented, and a current in an off state can be reduced. At least one of these gate electrodes is LD
With the D structure or the offset structure, the off current can be further reduced, and a stable switching element can be obtained.

Next, the first intermediate conductive layer 80 will be further described.

As shown in FIGS. 2 and 3, the first intermediate conductive layer 80 is interposed between the semiconductor layer 1a and the pixel electrode 9a, and connects the high-concentration drain region 1e and the pixel electrode 9a to each other. Contact hole 8a and second contact hole 8b
To make an electrical connection.

For this reason, the semiconductor layer 1a is removed from the pixel electrode 9a.
The diameters of the first contact hole 8a and the second contact hole 8b can be made smaller than in the case where one contact hole is opened. That is, when one contact hole is opened, if the selectivity at the time of etching is low, the etching accuracy decreases as the contact hole is opened deeper, so that penetration through a very thin semiconductor layer 1a of, for example, about 50 nm is prevented. In order to achieve this, dry etching that can reduce the diameter of the contact hole is stopped halfway, and finally the semiconductor layer 1 is wet-etched.
The process must be designed so as to open the hole to a. Alternatively, it is necessary to separately provide a film for preventing penetration through dry etching.

On the other hand, in the present embodiment, the pixel electrode 9
a and the high-concentration drain region 1e may be connected by two serial first contact holes 8a and second contact holes 8b.
And the second contact hole 8b can be opened by dry etching. Or,
This makes it possible to shorten at least the opening distance by wet etching. However, in order to slightly taper the first contact hole 8a and the second contact hole 8b, wet etching may be performed after dry etching. As described above, according to the present embodiment, the first contact hole 8
a and the diameters of the second contact holes 8b can be reduced, and the depressions and irregularities formed on the surface of the first intermediate conductive layer 80 in the first contact holes 8a can be reduced. Flattening of the part is promoted. Further, since the depressions and irregularities formed on the surface of the pixel electrode 9a in the second contact hole 8b can be small, flattening of the pixel electrode 9a is promoted. Further, in the present embodiment, the first
By forming the interlayer insulating film 81 thin, the diameter of the second contact hole 8b can be further reduced.

As a specific material of the first intermediate conductive layer 80, for example, at least one of Ti, Cr, W, Ta, Mo, and Pb, which are opaque refractory metals, like the first light shielding film 11a. Including metal simple substance, alloy, metal silicide and the like. With this configuration, even if the refractory metal contacts the ITO film forming the pixel electrode 9a, the refractory metal does not corrode.
A good electrical connection can be established between the first intermediate conductive layer 80 and the pixel electrode 9a via b. However, the first intermediate conductive layer 80
May be composed of a conductive polysilicon film. Even in this case, the function of increasing the storage capacity 70 and the relay function can be sufficiently exhibited. In this case, in particular, stress due to heat or the like hardly occurs between the first interlayer insulating film 81 and the first interlayer insulating film 81, which is useful for preventing cracks.

The thickness of the first intermediate conductive layer 80 is preferably, for example, about 50 nm or more and 500 nm or less. If the thickness of the first intermediate conductive layer 80 is about 50 nm, the possibility that the first intermediate conductive layer 80 will penetrate at the time of opening the second contact hole 8b in the manufacturing process is low, and the thickness is 500 nm.
This is because irregularities on the surface of the pixel electrode 9a cause no problem or can be relatively easily flattened. However, if the first intermediate conductive layer 80 is formed of a refractory metal film or an alloy film thereof, the selectivity in etching between the metal film and the interlayer insulating film is greatly different. Almost no.

In addition to the above, in the present embodiment, particularly, the first intermediate conductive layer 80 and the second intermediate conductive layer 180 are made of a refractory metal film which is a light-shielding conductive film. Therefore, the counter substrate 2
The channel region 1 a ′ of the TFT 30 and its adjacent region are formed by the first intermediate conductive layer 80 and the second intermediate conductive layer 180, as well as the second light-shielding film 23 on the substrate 0 and the data line 6 a on the TFT array substrate 10. Can be shaded. This allows
Even if strong incident light is incident from the counter substrate 20 side, a change in transistor characteristics can be prevented. For this reason, the electro-optical device of the present embodiment is effective when strong incident light is incident, for example, for a light valve of a projector.

Further, in the present embodiment, the first light-shielding first intermediate conductive layer 80 and the second light-transmitting intermediate conductive layer 180 are formed wide so as to define a part of the opening region of each pixel. In the light-shielding region where these exist, the opposing substrate 2
It is not necessary to increase the width of the data line 6b in order to form the second light-shielding film 23 or define the opening area on the zero.

Here, in particular, as shown in FIG. 2, in the light shielding area of each pixel along the data line 6a, the width Wd of the data line 6a, the width Wc of the protruding portion of the capacitor line 3b, the second intermediate conductive layer The data line 6a, the capacitance line 3b, and the second intermediate conductive layer 180 are laid out in a plane so that the relation of Wd <Wc <Wm is established between the data line 180 and the width Wm. Therefore, for the incident light from the opposite substrate 20 side, double shielding of the data line 6a and the second intermediate conductive layer 180 on the TFT array substrate 10 becomes possible.
If the TFT 30 is shielded only by the data line 6a made of an Al film having a high reflectivity, the projected light or the return light inclined with respect to the substrate surface is reflected by the inner surface of the data line 6a as multiple reflected light. Eventually, it reaches the channel region 1a 'and its adjacent region. However, in the present embodiment, the first intermediate conductive layer 80 and the second intermediate conductive layer 180 are formed from a high-reflection metal film or a polysilicon film having a low reflectance, and the second intermediate conductive layer 180 is separated from the data line 6a. Is formed to be wide (Wd <Wm), it is possible to attenuate the multiple reflection light due to the internal reflection as described above. Therefore, the configuration of the present embodiment is very useful in applications where strong incident light or reflected light exists, such as light valve applications for projectors.

Furthermore, in the present embodiment, particularly, the edge portion along the data line 6a of the pixel electrode 9a is overlapped with the edge portion of the second intermediate conductive layer 180 in plan view.
An edge portion of the pixel electrode 9a along the data line 6a is:
It hardly overlaps the edge of the data line 6a. In this manner, by defining the light-shielding region by the second intermediate conductive layer 180 and preventing the data line 6a from overlapping the pixel electrode 9a as much as possible, the parasitic capacitance between the source and the drain can be significantly reduced. As a result, the contrast ratio decreases,
Suppress the occurrence of display defects such as crosstalk and ghost,
A high-quality electro-optical device can be realized.

In the present embodiment, preferably, the second interlayer insulating film 4 between the data line 6a and the second intermediate conductive layer 180 is formed to have a thickness of 500 to 2000 nm. In addition to such a film thickness condition, the second intermediate conductive layer 180 is connected to the capacitance line 3b via the contact hole 18a, so that a parasitic capacitance between the data line 6a and the second intermediate conductive layer 180 is formed. Can also be reduced to a practically negligible value. It should be noted that a more specific film thickness may be individually and specifically determined by experiments, theoretical calculations, simulations, and the like in accordance with required image quality and device specifications.

In the embodiment described above, preferably, the first
The light-shielding film 11a is drawn out to a peripheral region on the TFT array substrate 1 and connected to a constant potential line. With this configuration, the first light-shielding film 11a can be fixed at a constant potential, and the TF formed on the first light-shielding film 11a with the base insulating film 12 interposed therebetween.
The characteristics of T30 are not changed by the potential fluctuation in the first light shielding film 11a. In this case, as the constant potential source, a constant potential source such as a negative power supply and a positive power supply supplied to peripheral circuits such as a scanning line drive circuit and a data line drive circuit for driving the electro-optical device, a ground power supply, A constant potential source supplied to the electrode 21 is exemplified. The capacitance line 3a and the first light-shielding film 11a may be electrically connected. With such a configuration, the wiring for forming the storage capacitor can be formed in a redundant structure, which is advantageous.

(Manufacturing Process of Electro-Optical Device) Next, a manufacturing process of the electro-optical device having the above-described configuration according to the first embodiment will be described with reference to FIGS. FIGS. 5 and 6 are process diagrams sequentially showing each layer on the TFT array substrate side in each process corresponding to the AA ′ cross section of FIG. 2 similarly to FIG.

First, as shown in step (1) of FIG. 5, a TFT array substrate 10 such as a quartz substrate, a glass substrate, a silicon substrate, etc. is prepared. Here, heat treatment is preferably performed in an inert gas atmosphere such as N ₂ (nitrogen) and at a high temperature of about 900 to 1300 ° C., and pre-processing is performed so that distortion generated in the TFT array substrate 10 in a high-temperature process performed later is reduced. Keep it. That is, the TFT array substrate 10 is preliminarily heat-treated at the same temperature or higher in accordance with the highest processing temperature at the highest temperature in the manufacturing process. And
On the entire surface of the TFT array substrate 10 thus treated,
Metals such as Ti, Cr, W, Ta, Mo and Pb and metal alloy films such as metal silicide are formed by sputtering or the like.
A film thickness of about 100 to 500 nm, preferably about 200 n
After forming a light-shielding conductive film having a thickness of m, the first light-shielding film 11 is formed by performing photolithography and etching.
a is formed. Note that an anti-reflection film such as a polysilicon film may be formed on the first light-shielding film 11a to reduce surface reflection.

Next, as shown in step (2) of FIG.
A TEOS (tetra-ethyl-ortho-silicate) gas, a TEB (tetra-ethyl-borate) gas, and a TMOP (tetra-methyl-oxy-phosphate) are formed on the light-shielding film 11a by, for example, normal pressure or reduced pressure CVD. ) NSG, PSG, BSG, BPS using gas etc.
A base insulating film 12 made of a silicate glass film such as G, a silicon nitride film, a silicon oxide film, or the like is formed. The thickness of the base insulating film 12 is, for example, about 500 m to 2000 m.
nm.

Next, as shown in step (3) of FIG. 5, a flow rate of about 400 to 600 ° C. is formed on the underlying insulating film 12 in a relatively low temperature environment of about 450 to 550 ° C., preferably about 500 ° C.
Low pressure CVD (for example, CV with a pressure of about 20
After forming the amorphous silicon film by D), the amorphous silicon film is subjected to a heat treatment in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 10 hours, preferably for 4 to 6 hours, so that the amorphous silicon film is The polysilicon film is formed by solid phase growth to a thickness of 50 to 200 nm, preferably about 100 nm. As a method for solid phase growth, heat treatment using RTA (Rapid Thermal Anneal) or laser annealing using an excimer laser or the like may be used.

At this time, when an n-channel type pixel switching TFT 30 is formed as the pixel switching TFT 30, a V group element such as Sb (antimony), As (arsenic), or P (phosphorus) is formed in the channel region. May be slightly doped by ion implantation or the like. When the pixel switching TFT 30 is a p-channel type, B (boron), Ga (gallium), In
A group III element impurity such as (indium) may be slightly doped by ion implantation or the like. The polysilicon film 1 may be directly formed by a low pressure CVD method or the like without passing through the amorphous silicon film. Alternatively, the polysilicon film 1 may be formed by implanting silicon ions into a polysilicon film deposited by a low-pressure CVD method or the like to make the film amorphous once, and then recrystallizing the film by a heat treatment or the like.

Next, as shown in step (4) of FIG. 5, the semiconductor layer 1a constituting the pixel switching TFT 30 is thermally oxidized at a temperature of about 900 to 1300 ° C., preferably at a temperature of about 1000 ° C. About 20-150nm
The insulating thin film 2 having a single-layer structure made of a relatively thin thermally oxidized silicon film is formed. However, after forming such a thermally oxidized silicon film as thin as about 30 nm or less, the reduced pressure CVD is performed.
An insulating thin film made of a high-temperature silicon oxide film (HTO film) or a silicon nitride film is deposited to a relatively thin thickness of about 50 nm by a method or the like, and an insulating thin film 2 having a multilayer structure including these thermal silicon oxide film and the insulating thin film May be formed. With such a multi-layer structure, warping due to heat can be prevented by shortening the high-temperature thermal oxidation time, particularly when a large substrate of 8 inches or more is used.

As a result, the thickness of the semiconductor layer 1a is about 30 to 150 nm, preferably about 35 to 50 nm.
And the thickness of the insulating thin film 2 is about 20 to 150 n
m, preferably about 30-100 nm.

Next, as shown in step (5) of FIG. 5, after a resist layer 500 is formed on the semiconductor layer 1a excluding a portion to be the first capacitor electrode 1f by a photolithography step, an etching step, etc. Ion dose about 3 ×
The first capacitor electrode 1f may be doped with 10 ¹² / cm ² to reduce the resistance.

Next, as shown in step (6) in FIG. 6, first, a capacitor line 3b is formed together with the scanning line 3a by a photolithography step using a resist mask, an etching step, or the like. Further, the pixel switching TFT 30 is replaced with an LDD.
In the case of an n-channel TFT having a structure, first, in order to form a low-concentration source region 1b and a low-concentration drain region 1c in the semiconductor layer 1a, a gate electrode, which is a part of the scanning line 3a, is used as a mask. the impurities of a group V element, such as low concentrations (e.g., P ions 1~3 × ^{10 1} 3 / cm
(Dose of ² ). This makes the scanning line 3a
The lower semiconductor layer 1a becomes the channel region 1a '.

Next, as shown in step (7) of FIG. 6, in order to form the high concentration source region 1d and the high concentration drain region 1e constituting the pixel switching TFT 30, a mask wider than the scanning line 3a is formed. in after the resist layer 600 is formed on the scanning line 3a, also at a high concentration of impurities of a group V element such as P (eg, P ions 1 to 3 × ^{10 1 5}
/ Cm ² (dose amount). When the pixel switching TFT 30 is of a p-channel type, B or the like is used to form the low-concentration source region 1b and the low-concentration drain region 1c and the high-concentration source region 1d and the high-concentration drain region 1e in the semiconductor layer 1a. What is necessary is just to dope using the impurity of Group III element of this.

Next, as shown in step (8) of FIG. 6, after the resist layer 600 is removed, the scanning lines 3a and the capacitance lines 3b are removed.
A high-temperature silicon oxide film (HTO film) or a silicon nitride film is formed on the
The first interlayer insulating film 81 is formed by depositing a thin film having a thickness of not more than nm. However, before depositing the insulating film, a high-temperature process on the TFT array substrate 10 made of a quartz substrate or the like is used to form an oxide film having a high withstand voltage and a relatively thin and few defects. A first interlayer insulating film 81 having a multi-layer structure including an oxide film may be formed.

Next, as shown in step (9) of FIG.
A first contact hole 8a for electrically connecting the intermediate conductive layer 80 and the high-concentration drain region 1e is opened in the first interlayer insulating film 81 by dry etching such as reactive ion etching or reactive ion beam etching. I do.
Since such dry etching has high directivity, the first contact hole 8a having a small diameter can be formed.
Alternatively, wet etching which is advantageous for preventing the first contact hole 8a from penetrating the semiconductor layer 1a may be used together. This wet etching is also effective from the viewpoint of providing a taper for better electrical connection to the first contact hole 8a. In the present embodiment, the contact hole 18a for connecting the second intermediate conductive layer 180 and the capacitor line 3b is also opened at the same time as the opening of the first contact hole 8a. Thereby, an increase in the number of steps can be prevented.

Next, as shown in the step (10) of FIG. 6, the T layer is formed on the first interlayer insulating film 81 similarly to the first light shielding film 11a.
After depositing a metal film such as a metal such as i, Cr, W, Ta, Mo, and Pd, a metal alloy film such as a metal silicide, or a polysilicon film by sputtering or the like, the first intermediate conductive layer 80 is formed by photolithography and etching. . At the same time, a second intermediate conductive layer 180 is also formed. Note that an anti-reflection film such as a polysilicon film may be formed on the first intermediate conductive layer 80 and the second intermediate conductive layer 180 in order to reduce surface reflection. In order to reduce the connection resistance of the first intermediate conductive layer 80, the layer structure of the first intermediate conductive layer 80 and the second intermediate conductive layer 180 is formed of a polysilicon film as a lower layer and a refractory metal as an upper layer. You may.

Next, as shown in step (11) of FIG. 6, the upper surface of the stacked body including the scanning lines 3a, the capacitor lines 3b, the first interlayer insulating film 81 and the base insulating film 12 is covered so as to cover the steps. For example, the second interlayer insulating film 4 made of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed by using a normal pressure or reduced pressure CVD method, a TEOS gas, or the like. After forming the second interlayer insulating film 4, a heat treatment at about 1000 ° C. may be performed to activate the semiconductor layer 1a.

Next, the third contact hole 5 for the data line 6a is etched to form the second interlayer insulating film 4, the first
A hole is formed in the interlayer insulating film 81 and the insulating thin film 2, and a data line 6 a is formed thereon by a sputtering method or the like for about 100 to 500 hours.
A low-resistance metal film such as Al or a metal silicide film having a thickness of nm is formed, and a third interlayer insulating film 7 is formed thereon by a CVD method or the like.

Subsequently, a second contact hole 8b is formed in the third interlayer insulating film 7 and the second interlayer insulating film 4 by etching, and a pixel electrode 9a made of an ITO film is finally formed through the second contact hole 8b. The first intermediate conductive layer 80 is formed so as to be electrically connected. In particular, this step (1)
In 1), when the third contact hole 5 is opened,
A contact hole for connecting the scanning line 3a and the capacitor line 3b to a wiring (not shown) in the peripheral region of the substrate may be formed in the first interlayer insulating film 81 and the second interlayer insulating film 4 at the same time. The data line 6a is deposited to a thickness of about 100 to 500 nm, preferably about 300 nm.
Should be deposited to a thickness of about 500 to 1500 nm. Further, the second contact hole 8a may be formed by dry etching such as reactive ion etching or reactive ion beam etching, but wet etching may be used to form a tapered shape. Further, the pixel electrode 9
a may be deposited to a thickness of about 50 to 200 nm. When the electro-optical device is used for a reflection type liquid crystal device, the pixel electrode 9a may be formed from a material having high reflectivity and light shielding properties such as Al.

As described above, according to the manufacturing process of the present embodiment, the above-described electro-optical device of the present embodiment can be manufactured relatively easily. In addition, T for pixel switching
Since the semiconductor layer 1a of the FT 30 is formed of polysilicon, a peripheral circuit can be formed in substantially the same process when the pixel switching TFT 30 is formed.

In the above-described manufacturing process, the surface of the second interlayer insulating film 4 or the third interlayer insulating film 7 is formed at the stage when the pixel electrode 9a is formed so that the film surface is flattened.
Flattening may be performed by an MP method or the like. Alternatively, a predetermined area of the TFT array substrate 10 is etched in advance to form a concave depression, and the subsequent steps are performed in the same manner so that the surface of the third interlayer insulating film 7 is flattened. Alternatively, the second interlayer insulating film 4 and the base insulating film 12 may be formed in a concave shape. As described above, when the underlying film surface is flattened at the stage when the pixel electrode 9a is formed,
The occurrence of disclination of the liquid crystal due to the step can be suppressed as much as possible, and display defects such as a decrease in contrast ratio do not occur.

(Second Embodiment) The configuration of a liquid crystal device which is a second embodiment of the electro-optical device according to the present invention will be described with reference to FIG.
This will be described with reference to FIG. FIG. 7 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed. FIG.
It is A 'sectional drawing. In FIG. 8, the scale of each layer and each member is made different so that each layer and each member have a size recognizable in the drawing.

As shown in FIGS. 7 and 8, the second embodiment is different from the first embodiment in that the first intermediate conductive layer 80 and the second
Since the intermediate conductive layer 180 is not separated, L
A point provided as one of the intermediate conductive layers 80 ′ and a contact hole 18 a for connecting the second intermediate conductive layer 180 and the capacitor line 3 b in the first embodiment are opened. The remaining configuration is the same as that of the first embodiment. still,
7 and 8, the same reference numerals are given to the same components as those in FIGS. 2 and 3 according to the first embodiment,
The description thereof is omitted.

As described above, in the second embodiment, the intermediate conductive layer 80 ′ overlaps with the portion of the capacitor line 3 b along the data line 6 a via the second interlayer insulating film 4 to form the storage capacitor 70. Accordingly, in the light-shielding region along the data line 6a, the first capacitance electrode 1f extending from the high-concentration drain region 1e of the semiconductor layer 1a and the capacitance line 3b are arranged to face each other,
In addition, the capacitance line 3b and the intermediate conductive layer 80 'can be arranged to face each other. As a result, according to the second embodiment, the three-dimensional storage capacitor 70 is also provided in the light-shielded area along the data line 6a.
Therefore, a large storage capacitor can be efficiently formed in a small area, which is a very advantageous structure when the aperture ratio of the pixel is increased and the pixel pitch is miniaturized.

(Third Embodiment) FIG. 9 shows a configuration of a liquid crystal device which is a third embodiment of the electro-optical device according to the present invention.
This will be described with reference to FIG. 9 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed, and FIG. 10 is a cross-sectional view taken along the line AA ′ of FIG. In FIG. 10, in order to make each layer and each member large enough to be recognized on the drawing,
The scale is different for each layer and each member.

In FIGS. 9 and 10, the same components as those in FIGS. 2 and 3 according to the first embodiment or FIGS. 7 and 8 according to the second embodiment are denoted by the same reference numerals. , And description thereof will be omitted.

As described above, in the third embodiment, the intermediate conductive layer 80 ′ is overlapped with the portion of the capacitor line 3 b ″ along the data line 6 a along the data line 6 a via the second interlayer insulating film 4. Therefore, the storage capacitor 70 is also formed in this region.
Therefore, in the light-shielding region along the data line 6a, the high-concentration drain region 1e of the semiconductor layer 1a is extended, and the first capacitance electrode 1f forming the capacitance electrode and the capacitance line 3b ″ can be arranged to face each other, and Capacitance line 3b ″ and intermediate conductive layer 8
0 ′ can be disposed to face. In addition to this, unlike the case of the second embodiment, the first contact hole 8
Since a ″ is provided so that the intermediate conductive layer 80 ′ and the semiconductor layer 1a can be electrically connected to each other at a point further ahead of the tip of the portion of the capacitor line 3b ″ along the data line 6a when viewed in a plan view,
It is not necessary to provide a constriction for b ″, and the aperture ratio of the pixel can be further increased, and the storage capacitance 70 can be increased.

In each of the embodiments described above, the planar shape of each contact hole may be a circle, a square, or any other polygonal shape, but the circle is particularly useful for preventing cracks in the interlayer insulating film around the contact hole.

(Fourth Embodiment) The structure of a liquid crystal device according to a fourth embodiment of the present invention will be described with reference to FIG.
1 and FIG. FIG. 11 is a plan view of a plurality of adjacent pixel groups on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed.
FIG. 12 is a cross-sectional view along AA ′ of FIG. 11. In FIG. 12, the scale of each layer and each member is made different so that each layer and each member have a size recognizable in the drawing. The same members as those in the first embodiment are denoted by the same reference numerals, and detailed description is omitted.

In the fourth embodiment, as shown in FIG. 11, a scanning line 3a and a data line 6a are provided substantially at the center of the non-opening area. The semiconductor layer 1a is arranged below the data line 6a so as to intersect with the scanning line 3a. As shown in FIG. 12, the data line 6a and the high concentration source region 1d of the semiconductor layer 1a
Are electrically connected via the third contact holes 5 below the data lines 6a. In addition, the semiconductor layer 1
a high-concentration drain region 1e and the intermediate conductive layer 80a are connected to the first contact hole 8 under the data line 6a.
It is electrically connected via a ′ ″. By arranging the semiconductor layer 1a below the light-shielding data line 6a in this manner, there is an effect of preventing light incident from the counter substrate 20 side from being directly applied to the semiconductor layer 1a. Furthermore,
By forming the semiconductor layer 1a, the third contact hole 5, and the first contact hole 8a '''in line symmetry with respect to the center line of the non-opening area in the scanning line 3a direction and the non-opening area in the data line 6a direction. The shape of the step can be made symmetrical with respect to the data line 6a, which is advantageous because there is no difference in light leakage due to the rotation direction of the liquid crystal.

Under the semiconductor layer 1a, the underlying insulating film 12
A first light-shielding film 11a is formed via the first light-shielding film. The first light shielding film 11a is formed in a matrix along the direction of the data line 6a and the direction of the scanning line 3a. The semiconductor layer 1a is disposed inside the first light-shielding film 11a, and has an effect of preventing the return light from the TFT array substrate 10 from being directly irradiated on the semiconductor layer 1a.

The intermediate conductive layer 80a is made of a conductive film containing a polysilicon film or a high melting point metal, and extends in a substantially T-shape between the semiconductor layer 1a and the pixel electrode 9a along the scanning line 3a and the data line 6a. And the semiconductor layer 1a and the pixel electrode 9
It functions as a buffer for electrically connecting a. More specifically, the high-concentration drain region 1e of the semiconductor layer 1a is electrically connected to the conductive intermediate conductive layer 80a in the first contact hole 8a '''.
a and the pixel electrode 9a are electrically connected in the second contact hole 8b. By adopting such a configuration, even when a deep contact hole is formed in the interlayer insulating film, the intermediate conductive layer 80 having a large etching selectivity can be obtained.
By providing a, it is possible to avoid the danger of piercing through the semiconductor layer 1a when the contact hole is opened.
The data line 6a and the high-concentration source region 1 of the semiconductor layer 1a
a third contact hole 5 for electrically connecting d
Similarly, the relay may be performed with the same film as the intermediate conductive layer 80a.

Further, in the fourth embodiment, the intermediate conductive layer 80
a, an interlayer insulating film 91 is laminated thereon, and a light-shielding conductive film 90a is formed thereon. The light-shielding conductive film 90a extends to the outside of the image display area in the direction of the scanning line 3a so as to cover the intermediate conductive layer 80a except for the second contact hole 8b, and is provided in a scanning line driving circuit, a data line driving circuit, and the like. The potential is fixed by being electrically connected to any one of a constant potential source such as a supplied negative power source and a positive power source, a ground power source, and a constant potential source supplied to the counter electrode. Therefore,
The intermediate conductive layer 80a is used as one capacitor electrode, and the light-shielding conductive film 90a is used as the other capacitor electrode.
0 can be formed. At this time, needless to say, the interlayer insulating film 91 functions as a dielectric film of the storage capacitor 70. Here, since the interlayer insulating film 91 is laminated only to form the storage capacitor 70, the thickness of the interlayer insulating film 91 must be reduced to a thickness that does not leak between the intermediate conductive layer 80a and the light-shielding conductive film 90a. Thereby, the storage capacity 70 can be increased. Further, in the present embodiment, by forming the interlayer insulating film 81 thick, the intermediate conductive layer 80a can be extended to above the TFT 30 and the scanning line 3a, so that the storage capacitance 70 can be efficiently increased. Furthermore, the fourth
In the embodiment, the capacitor electrode is not formed by extending the semiconductor layer 1a. Accordingly, since it is not necessary to form a capacitor electrode and a capacitor line for forming a storage capacitor with the same film as the scanning line 3a, as shown in FIG. It can be arranged substantially at the center of the non-opening area defined by the light shielding film 11a. Further, since it is not necessary to lower the resistance of the semiconductor layer 1a made of a polysilicon film, it is not necessary to implant impurities into the capacitor electrode formation portion, and the number of steps can be reduced.

In the fourth embodiment, the channel region 1a 'of the TFT 30 is formed at the intersection of the scanning line 3a and the data line 6a, so that it is substantially at the center of the non-opening region in the direction of the data line 6a and the direction of the scanning line 3a. Can be provided. Thereby, the incident light from the counter substrate 20 side and the TFT array substrate 1
Since the light is hardly irradiated with the return light from the 0 side, the leakage current of the TFT 30 due to the light can be significantly reduced.

Further, in the fourth embodiment, as shown in FIG. 11, the pattern width is reduced in the order of the light-shielding conductive film 90a, the intermediate conductive layer 80a, and the first light-shielding film 11a in the vicinity of the channel region 1a '. Thus, the first light-shielding film 11a is not directly irradiated with incident light. Also,
By interposing an intermediate conductive layer 80a made of a polysilicon film between the light-shielding conductive film 90a and the semiconductor layer 1a,
Light reflected on the surface of the first light shielding film 11a or the TFT array substrate 1
An effect of absorbing return light from the 0 side can be provided, which is advantageous in light resistance.

Further, in the fourth embodiment, the data lines 6a,
The light-shielding conductive film 90a, the first light-shielding film 11a, etc.
Since a non-opening region can be formed on the T-array substrate 10, the opposing substrate 20 does not need to be provided with a light-shielding film. This allows
When mechanically bonding the TFT array substrate 10 and the opposing substrate 20, even if the alignment is shifted,
Since there is no light-shielding film on 0, the light transmitting area (opening area) does not change. As a result, a stable pixel aperture ratio can always be obtained, so that device defects can be significantly reduced.

(Overall Configuration of Electro-Optical Device) The overall configuration of the electro-optical device in each embodiment configured as described above will be described with reference to FIGS. Note that FIG.
FIG. 14 is a plan view of the TFT array substrate 10 together with the components formed thereon viewed from the counter substrate 20 side, and FIG. 14 is a cross-sectional view taken along the line HH ′ of FIG.

In FIG. 13, a sealing material 52 is provided on the TFT array substrate 10 along the edge thereof, and is made of, for example, the same or different material as the second light shielding film 23 in parallel with the inside thereof. A third light-shielding film 53 is provided as a frame that defines the periphery of the image display area. A data line driving circuit 101 for driving the data line 6a by supplying an image signal to the data line 6a at a predetermined timing and an external circuit connection terminal 1 are provided in a region outside the sealing material 52.
02 is provided along one side of the TFT array substrate 10, and supplies a scanning signal to the scanning line 3a at a predetermined timing to drive the scanning line 3a.
4 are provided along two sides adjacent to this one side. If the delay of the scanning signal supplied to the scanning line 3a does not matter, it goes without saying that the scanning line driving circuit 104 may be provided on only one side. Also, the data line driving circuit 1
01 may be arranged on both sides along the side of the image display area. Further, on the remaining one side of the TFT array substrate 10, a plurality of wirings 105 for connecting between the scanning line driving circuits 104 provided on both sides of the image display area are provided. Also,
At least one corner portion of the counter substrate 20 is provided with a vertical conductive member 106 for establishing electrical continuity between the TFT array substrate 10 and the counter substrate 20. Then, as shown in FIG. 14, the opposite substrate 20 having substantially the same contour as the sealing material 52 shown in FIG. 13 is fixed to the TFT array substrate 10 by the sealing material 52. Incidentally, in addition to the data line driving circuit 101, the scanning line driving circuit 104, etc., on the TFT array substrate 10,
A sampling circuit for applying an image signal to the plurality of data lines 6a at a predetermined timing; a precharge circuit for supplying a precharge signal of a predetermined voltage level to the plurality of data lines 6a prior to the image signal; An inspection circuit or the like for inspecting the quality, defects, etc. of the electro-optical device may be formed.

In each of the embodiments described above with reference to FIGS. 1 to 14, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, TAB (Tape Automated Bonding) The driving LSI mounted on the substrate may be electrically and mechanically connected via an anisotropic conductive film provided on the periphery of the TFT array substrate 10. For example, TN (Twisted) is provided on each of the side of the opposite substrate 20 where the projection light is incident and the side where the emission light of the TFT array substrate 10 is emitted.
Nematic) mode, VA (Vertically Aligned) mode,
A polarizing film, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction according to an operation mode such as a PDLC (Polymer Dispersed Liquid Crystal) mode or a normally white mode / a normally black mode.

Since the electro-optical device according to each of the embodiments described above is applied to a color display projector,
Three electro-optical devices are used as light valves for R (red), G (green), and B (blue), respectively. Each light valve has light of each color separated through a dichroic mirror for RGB color separation. Are respectively incident as projection light. Therefore, in each embodiment, the opposing substrate 20 is not provided with a color filter. However, an RGB color filter may be formed on the opposing substrate 20 in a predetermined area facing the pixel electrode 9a where the second light-shielding film 23 is not formed, together with the protective film. Alternatively, it is also possible to form a color filter layer with a color resist or the like under the pixel electrode 9a facing the RGB on the TFT array substrate 10. In this way, the electro-optical device according to each embodiment can be applied to a direct-view or reflective color electro-optical device other than the projector. Further, a micro lens may be formed on the counter substrate 20 so as to correspond to one pixel. In this way, a bright electro-optical device can be realized by improving the efficiency of collecting incident light. Furthermore, a dichroic filter that produces RGB colors using light interference may be formed by depositing a number of interference layers having different refractive indexes on the counter substrate 20. According to the counter substrate with a dichroic filter, a brighter electro-optical device for color display can be realized.

In the electro-optical devices according to the above-described embodiments, incident light is incident from the side of the counter substrate 20 as in the related art. However, since the first light-shielding film 11a is provided, the TFT array is provided. The incident light may be made incident from the substrate 10 side and emitted from the counter substrate 20 side.
That is, even if the electro-optical device is attached to the projector in this manner, it is possible to effectively prevent light from being incident on the channel region 1a 'of the semiconductor layer 1a or an adjacent region thereof, and to display a high-quality image. Is possible. At this time, TF
There is no need to separately arrange a polarizing plate coated with an anti-reflection (AR) coating for preventing reflection on the back surface side of the T-array substrate 10 or attach an AR film,
The material cost can be reduced by that much, and the yield is not greatly reduced due to dust, scratches and the like when attaching the polarizing plate, which is very advantageous. In addition, since light resistance is excellent, even if a bright light source is used or polarization conversion is performed by a polarization beam splitter to improve light use efficiency, image quality deterioration such as crosstalk due to light does not occur.

The switching element provided in each pixel has been described as a normal stagger type or coplanar type polysilicon TFT. However, an inverse stagger type TFT is described.
Embodiments are also effective for other types of TFTs such as TFTs and amorphous silicon TFTs.

The electro-optical device of the present invention is not limited to the above-described embodiments, but can be appropriately modified without departing from the spirit and spirit of the invention which can be read from the claims and the entire specification. An electro-optical device with various changes is also included in the technical scope of the present invention.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit such as various elements and wires provided in a plurality of pixels in a matrix forming an image display area in an electro-optical device according to a first embodiment of the present invention.

FIG. 2 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed in the liquid crystal device according to the first embodiment.

FIG. 3 is a sectional view taken along line A-A 'of FIG.

FIG. 4 shows a plane pattern of a capacitance line and a scanning line in the present embodiment in comparison with a plane pattern in a comparative example.
FIG. 4 is an enlarged plan view showing a part of a capacitance line and a scanning line.

FIG. 5 is a process diagram (part 1) illustrating each step of an image display area in the embodiment of the manufacturing process of the liquid crystal device in the first embodiment in order.

FIG. 6 is a process diagram (part 2) illustrating each step of the image display area in the embodiment of the manufacturing process of the liquid crystal device in the first embodiment in order.

FIG. 7 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed in a liquid crystal device according to a second embodiment of the present invention.

8 is a sectional view taken along line A-A 'of FIG.

FIG. 9 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed in a liquid crystal device according to a third embodiment of the present invention.

FIG. 10 is a sectional view taken along line A-A ′ of FIG. 9;

FIG. 11 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed in a liquid crystal device according to a fourth embodiment of the present invention.

12 is a sectional view taken along line A-A 'of FIG.

FIG. 13 is a plan view of a TFT array substrate in the liquid crystal device according to each embodiment together with components formed thereon as viewed from a counter substrate side.

FIG. 14 is a sectional view taken along line H-H ′ of FIG.

[Explanation of symbols]

 1a Semiconductor layer 1a 'Channel region 1b Low-concentration source region 1c Low-concentration drain region 1d High-concentration source region 1e High-concentration drain region 1f First capacitance electrode 2 Insulating thin film 3a Scanning line 3b, 3b "... capacitance line 4 ... second interlayer insulating film 5 ... third contact hole 6a ... data line 7 ... third interlayer insulating film 8a, 8a", 8a '"... first contact hole 8b ... second contact hole 18 ... Contact hole 9a: Pixel electrode 10: TFT array substrate 11a: First light-shielding film 12: Base insulating film 16: Alignment film 20: Counter substrate 21: Counter electrode 22: Alignment film 23: Second light-shielding film 30: TFT 50: Liquid crystal Layer 52 Sealing material 53 Third light-shielding film 70 Storage capacitor 80 First intermediate conductive layer 80 ′ Intermediate conductive layer 81 First interlayer insulating film 101 Data line driving circuit 104 ... scan line driver circuit 180 ... second intermediate conductive layer

Continued on front page F-term (reference) 2H092 GA28 GA29 GA30 JA45 JA46 JB54 JB56 JB64 JB65 NA04 NA07 PA02 PA06 PA09 5C094 AA05 AA10 BA03 BA43 CA19 EA04 EA07 5F033 GG04 HH04 HH18 HH19 HH20 JJ18 NN01 JJ01 JJ01 JJ01 JJ01 JJ01 JJ01 JJ01 JJ01 QQ09 QQ11 QQ19 QQ37 RR09 RR13 RR14 RR15 VV15 XX03 XX19 5F110 BB01 BB04 CC02 DD02 DD03 DD05 DD12 DD13 DD14 DD25 FF02 FF03 FF23 FF32 GG02 NN13 NN25 NN04 NN04 NN04 NN04 NN04 NN04 NN04 NN04 NN04 NN73 PP02 PP03 PP10 PP13 PP33 QQ11

Claims (22)

[Claims] A thin film transistor provided on a substrate; a pixel electrode electrically connected to a drain region of a semiconductor layer of the thin film transistor; and an insulating film interposed between the semiconductor layer of the thin film transistor and the pixel electrode. A plurality of wirings provided, an intermediate conductive layer electrically connecting the drain region of the semiconductor layer of the thin film transistor and the pixel electrode, and the thin film transistor under a region of at least one of the plurality of wirings An electro-optical device comprising: a first contact hole for electrically connecting a drain region of the semiconductor layer to the intermediate conductive layer. 2. The electro-optical device according to claim 1, wherein a diameter of the first contact hole is smaller than a diameter of a second contact hole that electrically connects the intermediate conductive layer and the pixel electrode. apparatus. 3. At least one of the plurality of wirings is a data line electrically connected to a source region of a semiconductor layer of the thin film transistor, and the first contact hole is formed below a region of the data line. The electro-optical device according to claim 1, wherein the electro-optical device is located. 4. The electro-optical device according to claim 3, wherein the first contact hole is disposed in a vicinity where the data line and the scanning line intersect. 5. At least one of the plurality of wirings forms a scanning line intersecting the data line, and the intermediate conductive layer extends from the data line region along the scanning line. The electro-optical device according to claim 3, wherein the electro-optical device extends. 6. A second contact hole for electrically connecting the intermediate conductive layer and the pixel electrode is provided in an extending portion of the intermediate conductive layer arranged along the scanning line. The electro-optical device according to claim 4, wherein 7. The electro-optical device according to claim 6, wherein the second contact hole is located substantially at the center between adjacent data lines. 8. The electro-optical device according to claim 3, wherein the intermediate conductive layer extends along the data line. 9. At least one of the plurality of wirings is a capacitance line extending below the intermediate conductive layer, and the capacitance line extends avoiding a region of the first contact hole. The electro-optical device according to claim 1, wherein: 10. The depth of the first contact hole is:
The electro-optical device according to claim 1, wherein the depth is smaller than the depth of a second contact hole between the intermediate conductive layer and the pixel electrode. 11. The electro-optical device according to claim 4, wherein the intermediate conductive layer is at least partially opposed to a capacitor electrode made of the same film as the scanning line via an interlayer insulating film. apparatus. 12. The electro-optical device according to claim 11, wherein the second contact hole is opened at a position overlapping the capacitor electrode when viewed in plan. 13. The capacitor electrode has a portion extending along a scanning line when viewed in a plan view and a portion extending along the data line from a portion intersecting with the data line. 13. The electro-optical device according to claim 11, wherein at least a part of the capacitor electrode is overlapped with an interlayer insulating film interposed therebetween. 14. The electro-optical device according to claim 1, wherein the intermediate conductive layer is made of a light-shielding conductive film. 15. The electro-optical device according to claim 14, wherein the intermediate conductive layer defines a part of the light shielding area. 16. The intermediate conductive layer includes a portion extending along the data line when viewed in a plan view, wherein a part of the light shielding region in a direction along the data line is defined. The electro-optical device according to claim 15, wherein 17. The capacitance electrode has a portion extending along the data line when viewed in a plan view, and at a location along the data line, a width Wd of the data line and a width of the capacitance electrode, respectively. Wd is between Wc and the width Wm of the intermediate conductive layer portion extending along the data line.
17. The electro-optical device according to claim 16, wherein a relationship of <Wc <Wm is satisfied. 18. The electro-optical device according to claim 17, wherein an edge portion of the pixel electrode along the data line is overlapped with an edge portion of the intermediate conductive layer when viewed two-dimensionally. apparatus. 19. The electro-optical device according to claim 3, wherein the semiconductor layer is formed below a region of the data line. 20. The semiconductor device according to claim 20, wherein the first contact hole is formed at a position symmetrical to a third contact hole connecting the source region of the semiconductor layer and the data line with respect to a channel region of the semiconductor layer. 20. The electro-optical device according to claim 19, wherein: 21. A semiconductor device, comprising: a lower light-shielding film extending below the scanning line as viewed in a plan view below the semiconductor layer; and a second contact hole for electrically connecting the intermediate conductive layer and the pixel electrode is provided. 20. The electro-optical device according to claim 19, wherein the lower light-shielding film is located in a region protruding from the scanning line when viewed in plan. 22. A thin film transistor provided on a substrate; a data line electrically connected to a source region of a semiconductor layer of the thin film transistor; and a pixel electrode electrically connected to a drain region of the semiconductor layer of the thin film transistor. A light-blocking intermediate conductive layer electrically connecting the drain region of the semiconductor layer of the thin film transistor to the pixel electrode; and a capacitor provided along the data line and located in the drain region of the semiconductor layer of the thin film transistor A light-shielding film formed of the same film as the intermediate conductive layer; and a contact hole for electrically connecting the capacitance line and the light-shielding film below the data line. Electro-optical device.