JP2000098407A - Manufacture of electro-optical device and electro- optical device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method for an electro-optical device capable of certainly connecting light shielding film and constant potential wiring. SOLUTION: This prepn. method consists of a step forming first insulation film 12 placed between light shielding film 11a and a layer composing of constant potential wiring 80, a step forming second insulation film 4 placed between the first insulation film 12 and the constant potential wiring 80, a step annealing the first and the second insulation films 12, 4, and a step forming a contact hole 81 passing through the annealed first and second insulation films 12, 4. Where an annealing temp. in the annealing step of the first and the second insulation films 12, 4 is specified at temp. higher than or equal to a film forming temp. of the second insulation film 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an electro-optical device in which a light-shielding film for shielding a semiconductor layer of a thin film transistor (hereinafter, referred to as TFT) from light and a constant potential wiring are connected to each other via a contact hole. About the method.

[0002]

2. Description of the Related Art When an electro-optical device is used as a light valve in a projector or the like, generally, projection light is incident from the side of a counter substrate which is disposed opposite to a TFT array substrate with an electro-optical material layer such as liquid crystal interposed therebetween. You. Here, the projected light is a-Si (amorphous silicon) of the TFT in the pixel portion.
When the light enters a channel region of a semiconductor layer made of a film, a p-Si (polysilicon) film, or the like, a photocurrent is generated in this channel region due to a photoelectric conversion effect, and the transistor characteristics of the TFT deteriorate. For this reason, a light-shielding film called a black matrix or a black mask is generally formed from a metal material such as Cr (chromium) or resin black on the opposite substrate at a position facing each TFT. The light-shielding film has a function of improving contrast and preventing color mixture of coloring materials, in addition to shading the semiconductor layer of the TFT, by defining each pixel opening region.

Further, in this type of electro-optical device,
In particular, a positive stagger type or coplanar type a-Si or p-S having a top gate structure (that is, a structure in which a gate electrode is provided above a channel on a TFT array substrate).
In the case of using the iTFT, it is necessary to prevent a part of the projection light from entering the TFT channel region from the TFT array substrate side as return light by the projection optical system in the projector. Similarly, when the projection light is reflected from the surface of the TFT array substrate when passing therethrough, or when emitted from another electro-optical device when a plurality of electro-optical devices are used in combination for color, the projection optical system is Part of the projected light that penetrates is returned as TF from the TFT array substrate side.
It is also necessary to prevent incidence on the T channel region. For this purpose, Japanese Patent Application Laid-Open No. Hei 9-127497,
In Japanese Unexamined Patent Publication No. 2611, Japanese Unexamined Patent Application Publication No. 3-125123, Japanese Unexamined Patent Application Publication No. HEI 8-171101, etc., a TFT array substrate made of a quartz substrate or the like also has a opaque position, for example, at a position facing the TFT (ie, below the TFT). An electro-optical device in which a light-shielding film is formed from a high-melting-point metal is proposed.

The latter light-shielding film is disposed between the substrate and the semiconductor layer of the TFT provided for each pixel on the substrate, and is connected to a constant potential wiring outside the image display area, for example. Since the portion connecting the light-shielding film to the constant potential wiring is formed simultaneously with the TFT, a configuration in which the light-shielding film and the constant potential wiring are connected via a contact hole penetrating a plurality of insulating films may be adopted. .

[0005]

However, when forming a contact hole penetrating through a plurality of insulating layers, the etching rate is greatly different due to the material of the insulating layer and the like, thereby causing an abnormal shape of the contact hole. There is a risk. Therefore, the light-shielding film and the constant potential wiring may not be reliably connected.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing an electro-optical device capable of reliably connecting a light shielding film and a constant potential wiring.

[0007]

According to a method of manufacturing an electro-optical device of the present invention, in order to solve the above-mentioned problems, a plurality of pixel electrodes are provided on one of a pair of substrates enclosing an electro-optical material. And a plurality of thin film transistors respectively driving the plurality of pixel electrodes, a plurality of data lines and a plurality of scanning lines connected to the plurality of thin film transistors and intersecting with each other, and a semiconductor layer forming the plurality of thin film transistors. A method for manufacturing an electro-optical device, comprising: a light-shielding film provided at a position covering each of at least a channel region when viewed from the one substrate side; and a constant potential wiring connected to the light-shielding film through a contact hole. Forming a first insulating film located between the light-shielding film and a layer forming the constant potential wiring; and forming a first insulating film between the first insulating film and the constant potential wiring. Forming a second insulating film to be formed, annealing the first and second insulating films, and forming the contact hole penetrating the annealed first and second insulating films. Wherein the annealing temperature in the step of annealing the first and second insulating films is equal to or higher than the film forming temperature of the second insulating film.

According to the method of manufacturing an electro-optical device of the present invention, the annealing temperature in the step of annealing the first and second insulating films is set equal to or higher than the film forming temperature of the second insulating film. And the difference between the etching rates of the second insulating film becomes small. Therefore, when forming the contact hole penetrating the first and second insulating films, there is no possibility that the shape of the contact hole is abnormal, and therefore, the light shielding film and the constant potential wiring can be reliably connected.

In one aspect of the method of manufacturing an electro-optical device according to the present invention, in the annealing step, the annealing time is set to １ ／ or more of the film forming time of the second insulating film.

According to this aspect, since the difference between the etching rates of the first and second insulating films is further reduced, the shape of the contact hole is further improved.
Therefore, the light shielding film and the constant potential wiring can be reliably connected.

According to another aspect of the present invention, there is provided a method of manufacturing an electro-optical device, the method comprising: forming a plurality of pixel electrodes on one of a pair of substrates enclosing an electro-optical material; A plurality of thin film transistors each driving an electrode, a plurality of data lines and a plurality of scanning lines respectively connected to the plurality of thin film transistors and intersecting with each other, and at least a channel region of a semiconductor layer constituting the plurality of thin film transistors, A method of manufacturing an electro-optical device, comprising: a light-shielding film provided at a position to cover each of the light-shielding films when viewed from the side of the substrate; and a constant potential wiring connected to the light-shielding film through a contact hole. A step of forming a first insulating film located between a layer forming a potential wiring and a second insulating film located between the first insulating film and the constant potential wiring Forming a contact hole through the annealed first and second insulating films; forming the contact hole through the annealed first and second insulating films; In addition, the annealing temperature in the step of annealing the second insulating film is equal to or higher than the film forming temperature of the second insulating film, and the annealing time is equal to or longer than 10 minutes.

According to the method of manufacturing an electro-optical device of the present invention, the first and second insulating films are etched by setting the annealing time in the step of annealing the first and second insulating films to 10 minutes or more. The difference in speed is small. Therefore, when forming the contact hole penetrating the first and second insulating films, there is no possibility that the shape of the contact hole is abnormal, and therefore, the light shielding film and the constant potential wiring can be reliably connected.

In one aspect of the method of manufacturing an electro-optical device according to the present invention, the first insulating film is an insulating film disposed between a semiconductor layer of a switching element provided for each pixel and the light-shielding film. It is.

In one aspect of the method of manufacturing an electro-optical device according to the present invention, the second insulating film is provided between a layer constituting a switching element provided for each pixel and a wiring drawn from the switching element. This is an insulating film to be arranged.

In one embodiment of the method for manufacturing an electro-optical device according to the present invention, the contact hole is arranged outside the image display area.

To facilitate understanding of the present invention, reference numerals in the accompanying drawings are appended in parentheses, but the present invention is not limited to the illustrated embodiment.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

The configuration and operation of the first embodiment of the electro-optical device according to the present invention will be described with reference to FIGS. FIG. 1 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels formed in a matrix forming a screen display area of the electro-optical device.

In FIG. 1, a plurality of pixels, which are formed in a matrix and form a screen display area of the electro-optical device according to the present embodiment, have a TF for controlling a pixel electrode 9a.
A plurality of T30s are formed in a matrix, and a data line 6a to which an image signal is supplied is electrically connected to a source of the TFT 30. The image signals S1, S2,..., Sn to be written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied to a plurality of adjacent data lines 6a for each group. good. Also, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,..., Gm are applied to the scanning line 3a in a pulsed manner in this order at a predetermined timing. It is configured. The pixel electrode 9a has a TF
Image signals S1, S2,..., And Sn supplied from the data line 6a are written at a predetermined timing by closing the switch of the TFT 30, which is a switching element, for a predetermined period, which is electrically connected to the drain of the T30. . The image signals S1, S2,..., Sn of a predetermined level written to the electro-optical material via the pixel electrodes 9a are held for a certain period of time between the counter electrodes (described later) formed on the counter substrate (described later). Is done. The electro-optic material modulates light by changing the orientation and order of a molecular assembly according to the applied voltage level, thereby enabling gray scale display. In the normally white mode, the incident light cannot pass through the electro-optical material portion according to the applied voltage. In the normally black mode, the incident light does not pass through the electro-optical material according to the applied voltage. Light having a contrast according to an image signal is emitted from the electro-optical device as a whole, which can pass through the optical material portion. Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with the electro-optical material capacitor formed between the pixel electrode 9a and the counter electrode. For example, the voltage of the pixel electrode 9a is held by the storage capacitor 70 for a time that is three orders of magnitude longer than the time during which the source voltage is applied. Thereby, the holding characteristics are further improved, and an electro-optical device having a high contrast ratio can be realized.

Next, the configuration of the pixel portion in the image display area of the electro-optical device will be described with reference to FIGS. FIG. 2 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which a data line, a scanning line, a pixel electrode, a light-shielding film, and the like are formed, and FIG. It is. In FIG. 3, the scale of each layer and each member is different so that each layer and each member have a size that can be recognized in the drawing.

In FIG. 2, a plurality of transparent pixel electrodes 9 are arranged in a matrix on a TFT array substrate of the electro-optical device.
a (the outline is indicated by a dotted line portion 9a '), and the data line 6a, the scanning line 3a, and the capacitance line 3b are provided along the vertical and horizontal boundaries of the pixel electrode 9a. The data line 6a is electrically connected to a later-described source region of the semiconductor layer 1a such as a polysilicon film via the contact hole 5, and the pixel electrode 9a is connected to a later-described source region of the semiconductor layer 1a via the contact hole 8. Is electrically connected to the drain region. In addition, the scanning lines 3a are arranged so as to face a channel region (a hatched region falling rightward in the figure) of the semiconductor layer 1a to be described later. The first light-shielding film 11a in the pixel portion is provided in a region indicated by oblique lines rising to the right in the drawing. That is, in the pixel portion, the first light-shielding film 11a includes the TF including the channel region of the semiconductor layer 1a.
T is provided at a position where each T covers the TFT array substrate when viewed from the side thereof. If the first light-shielding film 11a covers the channel region of the semiconductor layer 1a, the function of preventing light leakage in the pixel TFT is exhibited, but the first light-shielding film 11a has a wiring function for keeping the first light-shielding film 11a at a constant potential. In the present embodiment, in particular, the first light-shielding film 11a is provided in a striped shape along the scanning line 3a for reasons such as defining the opening area of the pixel portion (that is, the area through which light is transmitted). ing.

As shown in FIG. 3, the electro-optical device is a TFT array substrate 10 which constitutes an example of one transparent substrate.
And an opposing substrate 20 which is an example of the other transparent substrate disposed to oppose the opposing substrate. The TFT array substrate 10 is made of, for example, a quartz substrate, and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate. The pixel electrode 9a is provided on the TFT array substrate 10, and an alignment film 16 on which a predetermined alignment process such as a rubbing process is performed is provided above the pixel electrode 9a. The pixel electrode 9a is made of, for example, ITO
It is composed of a transparent conductive thin film such as a film (indium tin oxide film). The alignment film 16 is made of, for example, an organic thin film such as a polyimide thin film.

As shown in FIG. 3, each pixel electrode 9a is provided on the TFT array substrate 10 at a position adjacent to each pixel electrode 9a.
Pixel switching TFT3 for switching control of a
0 is provided.

On the other hand, a counter electrode (common electrode) 21 is provided on the entire surface of the counter substrate 20, and an alignment film 22 on which a predetermined alignment process such as a rubbing process is performed is provided below the counter electrode. Is provided. The counter electrode 21 is, for example, I
It is made of a transparent conductive thin film such as a TO film. Also, the alignment film 22
Consists of an organic thin film such as a polyimide thin film.

As shown in FIG. 3, the opposing substrate 20 is further provided with a second light-shielding film 23 in a region other than the opening region of each pixel. For this reason, the incident light does not enter the channel region 1a 'and the LDD (Lightly Doped Drain) regions 1b and 1c of the semiconductor layer 1a of the pixel switching TFT 30 from the side of the counter substrate 20. Further, the second light-shielding film 23 has functions such as improvement of contrast and prevention of color mixture of color materials.

A sealing material 52 to be described later is provided between the TFT array substrate 10 and the opposing substrate 20, which are configured as described above and are arranged so that the pixel electrode 9a and the opposing electrode 21 face each other.
An electro-optical material such as liquid crystal is sealed in a space surrounded by (FIGS. 11 and 12), and an electro-optical material layer 50 is formed. The electro-optical material layer 50 assumes a predetermined alignment state by the alignment films 16 and 22 (see FIG. 3) in a state where no electric field is applied from the pixel electrode 9a. Electro-optic material layer 50
Is composed of, for example, an electro-optical material in which one or several kinds of nematic electro-optical materials are mixed. The sealing material 52 is an adhesive made of, for example, a photo-curing resin or a thermosetting resin for bonding the two substrates 10 and 20 around the periphery thereof, and is used for setting a distance between the two substrates to a predetermined value. Spacers such as glass fibers or glass beads are mixed.

As shown in FIG. 3, the pixel switching T
First light-shielding films 11a are provided between the TFT array substrate 10 and the pixel switching TFTs 30 at positions facing the FTs 30, respectively. First light shielding film 11
a is preferably an opaque refractory metal Ti, C
It is composed of a single metal, an alloy, a metal silicide or the like containing at least one of r, W, Ta, Mo, Pd and Si. With such a material, the first light-shielding film 11a is not broken or melted by high-temperature processing in the step of forming the pixel switching TFT 30 performed after the step of forming the first light-shielding film 11a on the TFT array substrate 10. I can do it. Since the first light-shielding film 11a is formed, return light or the like from the side of the TFT array substrate 10 is transmitted to the channel region 1a 'or L of the pixel switching TFT 30.
It is possible to prevent the incident light from entering the DD regions 1b and 1c beforehand, and the pixel switching TFT 3
The characteristic of 0 does not deteriorate.

Further, a first interlayer insulating film 12 is provided between the first light shielding film 11a and the plurality of pixel switching TFTs 30.
Is provided. The first interlayer insulating film 12 is provided for electrically insulating the semiconductor layer 1a constituting the pixel switching TFT 30 from the first light-shielding film 11a. Further, the first interlayer insulating film 12 is formed on the TFT array substrate 1.
By being formed on the entire surface of 0, it also has a function as a base film for the pixel switching TFT 30. That is, the pixel switching TFT 3 may be roughened during polishing of the surface of the TFT array substrate 10 or stains remaining after cleaning.
0 has the function of preventing the deterioration of the characteristic. The first interlayer insulating film 12 is made of, for example, a highly insulating glass such as NSG (non-doped silicate glass), PSG (phosphosilicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), or a silicon oxide film. , A silicon nitride film or the like. Due to the first interlayer insulating film 12, the first light-shielding film 11a is formed by the pixel switching TFT 3
It is also possible to prevent a situation where 0 or the like is contaminated.

In this embodiment, the gate insulating film 2 provided between the gate electrode 3a and the semiconductor layer 1a is used as a dielectric film extending from a position facing the gate electrode 3a.
The storage capacitor 70 is formed by extending the semiconductor film 1a to form a first storage capacitor electrode 1f, and further forming a part of the capacitor line 3b opposed thereto as a second storage capacitor electrode.
More specifically, the high concentration drain region 1e of the semiconductor layer 1a
Is provided below the data line 6a and the scanning line 3a, and is disposed opposite the capacitor line 3b extending along the data line 6a and the scanning line 3a with the insulating film 2 interposed therebetween. 1f. In particular, since the insulating film 2 as a dielectric of the storage capacitor 70 is nothing but the gate insulating film 2 of the TFT 30 formed on the polysilicon film by high-temperature oxidation, it can be a thin and high withstand voltage insulating film. The capacitor 70 can be configured as a large-capacity storage capacitor with a relatively small area.

In FIG. 3, the pixel switching TFT
Numeral 30 has an LDD (Lightly Doped Drain) structure, and includes a scanning line 3a (gate electrode), a channel region 1a 'of a semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a, a scanning line 3a and a semiconductor. A gate insulating film 2 for insulating the layer 1a, a data line 6a (source electrode), a low-concentration source region (source-side LDD region) 1b and a low-concentration drain region (drain-side LDD region) 1c of the semiconductor layer 1a,
The semiconductor layer 1a includes a high-concentration source region 1d and a high-concentration drain region 1e. A corresponding one of the plurality of pixel electrodes 9a is connected to the high-concentration drain region 1e. As will be described later, the source regions 1b and 1d and the drain regions 1c and 1e
It is formed by doping a predetermined concentration of n-type or p-type dopant depending on whether a type or p-type channel is formed. An n-type channel TFT has the advantage of a high operating speed, and is often used as a pixel switching TFT 30 that is a pixel switching element. In this embodiment, in particular, the data line 6a is formed of a light-shielding thin film such as a metal film of Al or the like or an alloy film of metal silicide or the like. On the scanning line 3a, the gate insulating film 2, and the first interlayer insulating film 12, a contact hole 5 leading to the high-concentration source region 1d and a contact hole 8 leading to the high-concentration drain region 1e are respectively formed. An interlayer insulating film 4 is formed. This source region 1b
The data line 6a is electrically connected to the high-concentration source region 1d through the contact hole 5. Further, a third interlayer insulating film 7 having a contact hole 8 to the high-concentration drain region 1e is formed on the data line 6a and the second interlayer insulating film 4. The pixel electrode 9a is electrically connected to the high-concentration drain region 1e via the contact hole 8 to the high-concentration drain region 1e. The above-described pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 7 configured as described above.

The pixel switching TFT 30 preferably has an LDD structure as described above, but may have an offset structure in which impurity ions are not implanted into the low-concentration source region 1b and the low-concentration drain region 1c. A self-aligned TFT in which impurity ions are implanted at a high concentration using 3a as a mask to form high-concentration source and drain regions in a self-aligned manner may be used.

In the present embodiment, the gate electrode (data line 3a) of the pixel switching TFT 30 is connected to the source
Although only one single gate structure is arranged between the drain regions 1b and 1e, two or more gate electrodes may be arranged between them. At this time, the same signal is applied to each gate electrode. When a TFT is formed with a dual gate (double gate) or triple gate or more as described above, a leak current at a junction between a channel and a source-drain region can be prevented, and a current in an off state can be reduced. If at least one of these gate electrodes has an LDD structure or an offset structure, the off-state current can be further reduced, and a stable switching element can be obtained.

Here, in general, the polysilicon layers such as the channel region 1a 'of the semiconductor layer 1a, the low-concentration source region 1b, and the low-concentration drain region 1c have a photocurrent due to the photoelectric conversion effect of the polysilicon when light enters. Occurs, and the transistor characteristics of the pixel switching TFT 30 deteriorate. However, in the present embodiment, the data line 6a is formed of a light-shielding metal thin film such as Al so that the scanning line 3a overlaps from above. , At least the semiconductor layer 1a
Can be effectively prevented from being incident on the channel region 1a 'and the LDD regions 1b and 1c. Further, as described above, since the first light-shielding film 11a is provided below the pixel switching TFT 30, at least the channel region 1a 'and the LDD region 1b of the semiconductor layer 1a are formed.
It is possible to effectively prevent the return light from entering c.

In this embodiment, particularly, the light shielding film 11a
Is electrically connected to a constant potential source via a constant potential wiring 80, and the first light shielding film 11a is set to a constant potential. Therefore,
The fluctuation in the potential of the first light-shielding film 11a does not adversely affect the pixel switching TFT 30 that is disposed to face the first light-shielding film 11a. In this case, the constant potential source is a constant potential such as a negative power supply or a positive power supply supplied to a peripheral circuit (eg, a scanning line driving circuit, a data line driving circuit, a sampling circuit, etc.) for driving the electro-optical device. Power source, a ground power source, a constant potential source supplied to the counter electrode 21, and the like. By using a power supply such as a peripheral circuit, the first light-shielding film 11a can be set at a constant potential without providing a dedicated potential wiring or an external input terminal.

FIG. 4 is a plan view of a connection portion between the first light shielding film 11a located outside the display area of the TFT array substrate 10 and the constant potential wiring 80, FIG. 5 is a sectional view taken along the line BB 'of FIG. FIG.
FIG. 5 is a layout diagram showing a layout relationship between a first light shielding film 11a and a constant potential wiring 80.

As shown in FIG. 6, the first light-shielding film 11a is drawn out to the outside of the display area 61 along the scanning line 3a.
It extends to the lower layer of the light-shielding film 60 for the frame (peripheral parting) that separates the display area from the non-display area. In addition, a constant potential wiring 80 for supplying a low potential side constant voltage power supply VSSY to the scanning line driving circuit 104 extends under the light shielding film 60 along the outer periphery of the display area 61, as shown in FIGS. As shown, the first light-shielding film 11a and the constant potential wiring 80 are electrically connected via the contact hole 81 penetrating the first interlayer insulating film 12 and the second interlayer insulating film 4. Since the first light-shielding film 11a is thus connected to the constant potential wiring 80 for supplying the constant voltage power supply VSSY, the first light-shielding film 11a
Is a constant voltage power supply VSS without floating
It is fixed to the potential of Y.

Next, a method for manufacturing the TFT array substrate 10 will be described.

First, as shown in step (A) of FIG. 7, tungsten, titanium, chromium, tantalum, or the like is formed on the entire surface of a glass substrate, for example, a transparent insulating substrate 10 made of alkali-free glass or quartz by sputtering or the like. The opaque and electrically conductive light-shielding film 11 made of a metal film such as molybdenum or a metal alloy film such as a metal silicide containing these metals is formed in a thickness of about 500 angstroms to about 3000 angstroms, preferably about 1000 angstroms.
It is formed to a thickness of about 2000 angstroms. Thereafter, patterning is performed using a photolithography technique as shown in step (B) to form a first light-shielding film 11a. The first light-shielding film 11a is formed at least in the channel region 1 of the pixel switching TFT 30 formed later.
a, low-concentration source / drain regions 1b and 1c, and low-concentration source / drain regions 1b and 1c
It is formed so as to cover the junction with the drain regions 1d and 1e as viewed from the back side of the insulating substrate 10. The pixel switching TFT 30 of the first light-shielding film 11a thus formed
A portion formed corresponding to the channel region 1a is a channel light shielding portion, and a portion formed so as to be connected to the constant potential wiring 80 is a wiring portion.

Next, as shown in step (C) of FIG. 7, the surface of the first light-shielding film 11a is
About 15,000 angstroms, preferably about 8000
An angstrom first interlayer insulating film 12 is formed. The first interlayer insulating film 12 insulates the first light-shielding film 11a from the semiconductor film 1 to be formed later. For example, a silicon oxide film or a normal pressure CVD method, a low pressure CVD method, or a TEOS gas is used. It is formed as an insulating film such as a silicon nitride film. By forming the first interlayer insulating film 12 on the entire surface of the insulating substrate 10, an effect as a base film can be obtained. That is, it is possible to prevent the characteristics of the pixel switching TFT 30 from deteriorating due to roughness at the time of polishing the surface of the insulating substrate 10 or contamination due to insufficient cleaning.

Next, as shown in step (D) of FIG. 7, a polysilicon film 1A having a thickness of about 500 Å to about 2000 Å, preferably about 550 Å, is formed on the entire surface of the first interlayer insulating film 12. To form The method is as follows.
While heating to about 500 ° C., preferably about 500 ° C., a monosilane gas or a disilane gas is supplied at about 400 cc / min.
Supply at a flow rate of about 600 cc / min, pressure about 20 Pa
At about 40 Pa, an amorphous silicon film is formed. Thereafter, in a nitrogen atmosphere, about 600 ° C. to about 700 ° C.
Annealing is performed at a temperature of about 1 hour to about 72 hours, preferably about 4 hours to about 6 hours, and solid phase growth is performed to form a polysilicon film 1A. The thickness of the polysilicon film is 400
Angstroms to 2000 angstroms, preferably 400 to 600 angstroms. Also,
The polysilicon film 1A may be directly formed by a low-pressure CVD method or the like, or may be made amorphous by implanting silicon ions into a polysilicon film deposited by a low-pressure CVD method or the like, and recrystallized by annealing or the like. A silicon film 1A may be formed.

Next, using photolithography technology,
As shown in FIG. 7E, the polysilicon film 1A is patterned to form an island-shaped semiconductor layer 1 (active layer) on the pixel switching TFT 30. On the other hand, the polysilicon layer 1A is completely removed at the connection portion with the constant potential wiring 80.

Next, as shown in step (F) of FIG. 7, the semiconductor layer 1 is thermally oxidized at a temperature of about 900 ° C. to about 1300 ° C., so that the surface of the semiconductor layer 1 has a thickness of about 200 Å. A gate insulating film 2 made of a silicon oxide film of about 1500 Å is formed. By this step, the thickness of the semiconductor layer 1 finally becomes about 300 Å to about 1500 Å, preferably about 3 Å.
The thickness of the gate insulating film 2 is about 50 Å to about 450 Å, and the thickness of the gate insulating film 2 is about 200 Å to about 1500 Å. In addition, 8
When using a large substrate of about inch,
In order to prevent zero warpage, the thermal oxidation time is shortened to make the thermal oxide film thin, and a high-temperature silicon oxide film (HTO film) or a silicon nitride film is deposited on the thermal oxide film by a CVD method or the like. A multilayer gate insulating film structure of two or more layers may be formed.

Next, as shown in FIG. 8A, a polysilicon film 3 for forming a scanning line 3a (gate electrode) is formed on the entire surface of the substrate 10, and phosphorus is thermally diffused to form a polysilicon film. The silicon film 3 is made conductive. Alternatively, a doped silicon film in which phosphorus is introduced simultaneously with the formation of the polysilicon film 3 may be used.

Next, the polysilicon film 3 is patterned by photolithography as shown in FIG. 8B, and a gate electrode (a part of the scanning line 3a) is provided on the pixel switching TFT 30 side. Form. On the other hand, the polysilicon film 3
Is completely removed. The material of the scanning line 3a (gate electrode) may be a metal film, a metal silicide film, or the like, or may be a multilayered combination of a metal film, a metal silicide film, and a polysilicon film. In particular,
Since a metal film or a metal silicide film has a light-shielding property, a black matrix can be omitted by wiring the scanning line 3a as a light-shielding film. Accordingly, it is possible to prevent a decrease in the pixel aperture ratio due to misalignment between the opposing substrate and the electro-optical device substrate.

Next, as shown in the step (C) of FIG. 8, the pixel switching TFT 30 and the N of the peripheral driving circuit are changed.
On the side of the channel TFT portion, using the gate electrode as a mask, about 0.1 × 10 ¹³ / cm ² to about 10 × 10 ¹³ / cm ²
Low-concentration impurity ions (such as phosphorus) 1 with a dose of cm ²
9, and a low-concentration source is self-aligned with the gate electrode on the pixel switching TFT side.
The drain regions 1b and 1c are formed. Here, since it is located below the gate electrode, the portion where the impurity ions are not introduced becomes the channel region 1a as it is in the semiconductor layer. When the ion implantation is performed in this manner, impurity ions are also introduced into the polysilicon layer formed as the gate electrode, so that the polysilicon layer becomes more conductive.

Next, as shown in step (D) of FIG. 8, the pixel switching TFT 30 and the N of the peripheral driving circuit
On the channel TFT portion side, a resist mask 21 wider than the gate electrode is formed, and high-concentration impurity ions (phosphorus or the like) 20 are deposited at about 0.1 × 10 ¹⁵ / cm ² to about 10 × 1
The implantation is performed at a dose of 0 ¹⁵ / cm ² to form a high-concentration source region 1d and a high-concentration drain region 1e.

Instead of these impurity introducing steps, high-concentration impurity ions (such as phosphorus) are implanted without forming low-concentration impurity ions and forming a resist mask wider than the gate electrode. Alternatively, a source region and a drain region having an offset structure may be formed. Further, needless to say, the source and drain regions having a self-aligned structure may be formed by implanting high-concentration impurity ions (such as phosphorus) using the gate electrode as a mask.

Although not shown, in order to form a P-channel TFT portion of the peripheral drive circuit, the pixel switching TFT portion and the N-channel TFT portion are covered with a resist and protected, and the gate electrode is used as a mask. 0.1 × 1
By implanting impurity ions such as boron at a dose of 0 ¹⁵ / cm ² to about 10 × 10 ¹⁵ / cm ² , a P-channel source / drain region is formed in a self-aligned manner. Note that, similarly to the formation of the pixel TFT portion and the N-channel TFT portion of the peripheral driver circuit, the gate electrode is used as a mask and about 0.1 × 10 ¹³ / cm ² to about 10 × 10 ¹³ /
Low concentration impurity ions (boron, etc.) at a dose of cm ²
To form a low-concentration source / drain region in the polysilicon film, and then form a mask wider than the gate electrode to reduce the concentration of high-concentration impurity ions (boron, etc.) by about 0.1 ×.
The source region and the drain region having the LDD structure may be formed by implantation at a dose of 10 ¹⁵ / cm ² to about 10 × 10 ¹⁵ / cm ² . Further, without implanting low-concentration impurity ions, high-concentration impurity ions (such as boron) are implanted in a state where a mask wider than the gate electrode is formed, thereby forming a source region and a drain region having an offset structure. Is also good. By these ion implantation steps, a complementary TFT can be formed, and a peripheral driver circuit can be built in the same substrate.

Next, as shown in step (E) of FIG. 8, the thickness of the gate electrode is reduced to about 500 mm at a temperature of about 820 ° C. by a normal pressure CVD method, a low pressure CVD method, or the like.
A second interlayer insulating film 4 made of an NSG film (silicate glass film containing neither boron nor phosphorus) or a silicon nitride film having a thickness of 0 Å to about 15000 Å is formed. Then, the impurity ions introduced into the source / drain regions are activated and the contact holes 81 are formed.
Annealing is performed to suppress the shape abnormality in the step (A) in FIG. 9. The annealing temperature at this time is set to a temperature equal to or higher than the film forming temperature of the second interlayer insulating film 4. For example, when the film forming temperature of the second interlayer insulating film 4 is 820 ° C., the annealing is performed at the temperature or higher. In addition, the annealing time is set to a time equal to or longer than 1/2 of the film forming time of the second interlayer insulating film 4, or 10 minutes or more.

By performing the annealing under such conditions, the first insulating film 12 is sufficiently contracted during the annealing, and the abnormal shape during etching is less likely to occur. Therefore, the constant potential wiring 80 is less likely to be disconnected in the contact hole 81. Particularly, when the first interlayer insulating film 12 is formed using a TEOS gas or the like, the first interlayer insulating film 12 is formed.
Since the content of carbon (C) and water (H ₂ O) therein is increased, the shrinkage by heating is increased. Therefore, in this case, the effect of annealing is particularly great.

Next, at the connection portion with the constant potential wiring 80,
A contact hole 4a is formed in a region corresponding to the wiring portion of the first light shielding film 11a. In this case, forming the anisotropic contact hole 4a by dry etching such as reactive ion etching or reactive ion beam etching is advantageous for high definition because the opening diameter can be formed substantially as the size of the mask. is there. When the dry etching and the wet etching are combined and the contact hole 4a is formed in a tapered shape, there is an effect of preventing disconnection at the time of wiring connection.

Next, as shown in the step (A) of FIG. 9, the pixel switching T
On the side of the FT 30 portion, a contact hole 5 is formed in a portion of the second interlayer insulating film 4 corresponding to the source region. Further, at the connection portion with the constant potential wiring 80, a contact hole 12a connected to the contact hole 4a is formed in the first interlayer insulating film 12. Thereby, a contact hole 81 penetrating through the first interlayer insulating film 12 and the second interlayer insulating film 4 is formed.

Next, as shown in FIG. 9B, an aluminum film 6 for forming the data line 6a (source electrode) is formed on the surface of the interlayer insulating film 4 by a sputtering method or the like. In addition to a metal film such as aluminum, a metal silicide film or a metal alloy film may be used. The formed aluminum film 6 is connected to the first light shielding film 11a via the contact hole 81.

Next, as shown in a step (C) of FIG. 9, the aluminum film 6 is patterned by using a photolithography technique, and in the pixel switching TFT 30 part,
A source electrode is formed as a part of the data line 6a. On the other hand, at the connection portion with the constant potential wiring 80, the aluminum film 6 is patterned to form the constant potential wiring 80. Thus, the first light-shielding film 11a and the constant potential wiring 80 are connected via the contact hole 81.

Next, as shown in the step (D) of FIG. 9, the source electrode and the surface of the constant potential wiring 80 are subjected to a normal pressure CVD method, a normal pressure ozone-TEOS method, or the like, for example, at a temperature of about 400 ° C. Below, a third interlayer insulating film 7 including at least two layers of a BPSG film (a silicate glass film containing boron or phosphorus) having a thickness of about 500 Å to about 15,000 Å and an NSG film having a thickness of about 100 Å to about 3,000 Å. Form. Also,
An organic film or the like may be applied by spin coating to form a flattened film without a stepped shape.

Next, as shown in FIG. 9E, the second interlayer insulating film 4 and the third interlayer insulating film are formed on the pixel switching TFT 30 side by using a photolithography technique and a dry etching method. 7, a contact hole 8 is formed in a portion corresponding to the high-concentration drain region 1e. Also in this case, it is advantageous to form the anisotropic contact hole 8 by dry etching such as reactive ion etching and reactive ion beam etching for higher definition. When the dry etching and the wet etching are combined to form the contact hole 8 in a tapered shape, there is an effect of preventing disconnection at the time of wiring connection.

Next, as shown in step (A) of FIG.
After forming an ITO film 9 having a thickness of about 400 Å to about 2,000 Å for forming a drain electrode on the front surface side of the third interlayer insulating film 7 by a sputtering method or the like, a process shown in FIG. As described above, the ITO film 9 is patterned using the photolithography technique, and the pixel electrode 9a is formed in the pixel switching TFT 30 portion. In the connection portion with the constant potential wiring 80, the ITO film 9
Is completely removed. Note that an alignment film 16 of polyimide or the like is formed on the surface of the pixel electrode 9a, and is subjected to a rubbing process. The pixel electrode 9a is not limited to the ITO film, but may be a SnO film.
It is also possible to use a transparent electrode material made of a metal oxide film having a high melting point such as an x film or a ZnOx film. With these materials, the step coverage in the contact hole 8 can be practically used. . When a reflection type electro-optical device is formed, a film having high reflectance such as aluminum is formed as the pixel electrode 9a.

In the step (E) of FIG. 8 and the step (A) of FIG. 9, when forming the contact hole 5,
The contact hole 4a at the connection portion with the constant potential wiring 80 may be formed at the same time.

(Overall Configuration of Electro-Optical Device) The overall configuration of each embodiment of the electro-optical device configured as described above will be described with reference to FIG. 11 and FIG. Note that FIG.
FIG. 12 is a plan view of the FT array substrate 10 together with the components formed thereon viewed from the counter substrate 20 side.
FIG. 14 is a sectional view taken along line HH ′ of FIG. 13 including the counter substrate 20.

In FIG. 11, a sealing material 52 is provided on the TFT array substrate 10 along the edge thereof, and is made of, for example, the same or different material as the second light shielding film 23 in parallel with the inside thereof. A second light-shielding film 53 is provided as a peripheral parting. The data line drive circuit 101 and the mounting terminal 102
The scanning line drive circuit 104 is provided along one side of the T array substrate 10 and is provided along two sides adjacent to the one side. If the delay of the scanning signal supplied to the scanning line 3a does not matter, it goes without saying that the scanning line driving circuit 104 may be provided on only one side. Further, the data line driving circuits 101 may be arranged on both sides along the side of the screen display area. For example, the odd-numbered data lines 6a supply an image signal from a data line driving circuit arranged along one side of the screen display area, and the even-numbered data lines extend along the opposite side of the screen display area. The image signal may be supplied from a data line driving circuit disposed in the same manner. If the data lines 6a are driven in a comb-tooth shape in this manner, the area occupied by the data line driving circuit can be expanded, so that a complicated circuit can be formed. Further, on one remaining side of the TFT array substrate 10, a plurality of wirings 1 for connecting the scanning line driving circuits 104 provided on both sides of the screen display area are provided.
05 as well as a second
A precharge circuit 201 under the light shielding film 53 (see FIG. 4)
Is provided. In at least one of the corners of the opposing substrate 20, silver points 106 made of a conductive material for establishing electric conduction between the TFT array substrate 10 and the opposing substrate 20 are provided. Then, as shown in FIG. 12, the counter substrate 20 having substantially the same contour as the sealing material 52 shown in FIG.
It is fixed to the array substrate 10.

The TFT array substrate 1 of the electro-optical device according to each embodiment described above with reference to FIGS.
Further, an inspection circuit or the like for inspecting the quality, defects, and the like of the electro-optical device during manufacturing or shipping may be formed on zero. Instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, a driving LSI mounted on a TAB (tape automated bonding substrate) is provided around the TFT array substrate 10. The connection may be made electrically and mechanically via an anisotropic conductive film provided in the portion. Further, on the side of the opposite substrate 20 where the projected light is incident and on the side where the emitted light of the TFT array substrate 10 is emitted, for example, T
Depending on the operation mode such as N (twisted nematic) mode, STN (super TN) mode, D-STN (double-STN) mode, and normally white mode / normally black mode, a polarizing film, a retardation film, A polarizing plate and the like are arranged in a predetermined direction.

The electro-optical device according to each of the embodiments described above is applied to a color liquid crystal projector.
Three electro-optical devices are used as RGB light valves, respectively, and light of each color separated through a dichroic mirror for RGB color separation is incident on each electro-optical device as projection light. Become. Therefore, in each embodiment, the counter substrate 20 is not provided with a color filter. However, an RGB color filter may be formed on the opposing substrate 20 in a predetermined area facing the pixel electrode 9a where the second light-shielding film 23 is not formed, together with the protective film. In this way, the electro-optical device according to each embodiment can be applied to a color electro-optical device such as a direct-view or reflection-type color liquid crystal television other than the liquid crystal projector. Further, a micro lens may be formed on the counter substrate 20 so as to correspond to one pixel. In this way, a bright electro-optical device can be realized by improving the efficiency of collecting incident light. Furthermore, a dichroic filter that produces RGB colors using light interference may be formed by depositing a number of interference layers having different refractive indexes on the counter substrate 20. According to the counter substrate with the dichroic filter, a brighter color electro-optical device can be realized.

In the electro-optical device according to each of the embodiments described above, incident light is incident from the side of the counter substrate 20 as in the related art. However, since the first light shielding film 11a is provided, the TFT array substrate The incident light may be incident from the side of the counter substrate 10 and emitted from the counter substrate 20 side.
That is, even if the electro-optical device is attached to the electro-optical material projector, the channel region 1 of the semiconductor layer 1a
Light can be prevented from entering the a ′ and the LDD regions 1b and 1c, and a high-quality image can be displayed. Here, conventionally, in order to prevent reflection on the back surface side of the TFT array substrate 10, it has been necessary to separately arrange a polarizing plate coated with an AR coating for antireflection or attach an AR film. However, in each embodiment, the first light-shielding film 11a is formed between the surface of the TFT array substrate 10 and at least the channel region 1a 'and the LDD regions 1b and 1c of the semiconductor layer 1a. It is not necessary to use a coated polarizing plate or AR film, or use a substrate obtained by subjecting the TFT array substrate 10 itself to an AR process. Therefore, according to each embodiment, material cost can be reduced, and at the time of attaching a polarizing plate,
It is very advantageous without lowering the yield. In addition, since light resistance is excellent, even if a bright light source is used or polarization conversion is performed by a polarizing beam splitter to improve light use efficiency, image quality deterioration such as crosstalk due to light does not occur.

The switching element provided in each pixel has been described as a normal stagger type or coplanar type polysilicon TFT.
The embodiments are also effective for other types of TFTs such as TFTs and amorphous silicon TFTs.

In this embodiment, the gate insulating film 2 has a single-layer structure. However, the gate insulating film may have a two-layer structure, and the upper insulating film may be left at a portion connected to the constant potential wiring 80. . In this case, the contact hole corresponding to the contact hole 81 penetrates the three layers of the first interlayer insulating film 12, the upper insulating film, and the second interlayer insulating film.

[0066]

According to the method of manufacturing the electro-optical device of the present invention, the annealing temperature in the step of annealing the first and second insulating films is set to be equal to or higher than the film forming temperature of the second insulating film. The difference between the etching rates of the first and second insulating films becomes small. Therefore, when forming the contact hole penetrating the first and second insulating films, there is no possibility that the shape of the contact hole is abnormal, and therefore, the light shielding film and the constant potential wiring can be reliably connected. According to the method of manufacturing an electro-optical device of the present invention, the annealing time in the step of annealing the first and second insulating films is set to 10 minutes or more, so that the etching rates of the first and second insulating films are increased. Is small. Therefore, when forming the contact hole penetrating the first and second insulating films, there is no possibility that the shape of the contact hole is abnormal, and therefore, the light shielding film and the constant potential wiring can be reliably connected.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a display area of an electro-optical device.

FIG. 2 is a diagram illustrating a pixel of the electro-optical device.

FIG. 3 is a sectional view taken along line AA ′ of FIG. 2;

FIG. 4 is a diagram showing a connection portion between a first light shielding film and a constant potential wiring.

FIG. 5 is a sectional view taken along line BB ′ of FIG. 4;

FIG. 6 is a diagram showing an arrangement of a connection portion between a first light shielding film and a constant potential wiring.

FIG. 7 is a diagram showing a manufacturing process of the electro-optical device according to the manufacturing method of the present invention.

FIG. 8 is a view showing a step following the step shown in FIG. 7;

FIG. 9 is a view showing a step following the step shown in FIG. 8;

FIG. 10 is a view showing a step following the step shown in FIG. 9;

FIG. 11 is a layout diagram of elements constituting the electro-optical device.

FIG. 12 is a sectional view taken along line HH ′ of FIG. 6;

[Explanation of symbols]

 Reference Signs List 4 second interlayer insulating film 12 first interlayer insulating film 11a first light shielding film 80 constant potential wiring 81 contact hole

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H092 JA26 JA29 JA33 JA38 JA42 JA44 JB13 JB23 JB32 JB33 JB38 JB52 JB57 JB63 JB69 KA04 KA07 KB12 KB13 MA05 MA08 MA14 MA15 MA16 MA18 MA19 MA20 MA25 MA27 MA30 MA35 MA37 NA41 NA13 NA22 NA29 PA06 PA09 QA07 5C094 AA04 AA42 AA43 AA55 BA03 BA43 CA19 DA15 DB10 EA04 EA05 EA10 EB02 ED15 FA02 FB02 FB15 GB10 JA20

Claims (6)

[Claims] 1. A plurality of pixel electrodes, a plurality of thin film transistors for driving the plurality of pixel electrodes, and a plurality of thin film transistors, respectively, on one of a pair of substrates enclosing an electro-optical material. A plurality of connected data lines and a plurality of scanning lines, and a light-shielding film provided at a position covering at least a channel region of a semiconductor layer forming the plurality of thin film transistors as viewed from the one substrate side. And a method for manufacturing an electro-optical device, comprising: a light-shielding film and a constant potential wiring connected via a contact hole; wherein a first insulating layer located between the light-shielding film and a layer forming the constant potential wiring is provided. Forming a film, forming a second insulating film located between the first insulating film and the constant potential wiring, annealing the first and second insulating films. And forming the contact hole penetrating the annealed first and second insulating films. The annealing temperature of the step of annealing the first and second insulating films is set to the second temperature. A manufacturing temperature of the electro-optical device, which is equal to or higher than the film forming temperature of the insulating film. 2. The method of manufacturing an electro-optical device according to claim 1, wherein, in the annealing step, an annealing time is set to a half or more of a film forming time of the second insulating film. 3. A plurality of pixel electrodes, a plurality of thin film transistors respectively driving the plurality of pixel electrodes, and a plurality of thin film transistors on one of a pair of substrates enclosing the electro-optical material. A plurality of connected data lines and a plurality of scanning lines, and a light-shielding film provided at a position covering at least a channel region of a semiconductor layer forming the plurality of thin film transistors as viewed from the one substrate side. And a method of manufacturing an electro-optical device, comprising: a light-shielding film and a constant potential wiring connected via a contact hole; a first insulating film located between the light-shielding film and a layer forming the constant potential wiring Forming a first insulating film, forming a second insulating film located between the first insulating film and the constant potential wiring, and annealing the first and second insulating films. And forming the contact hole penetrating the annealed first and second insulating films. The annealing temperature of the step of annealing the first and second insulating films is set to the second temperature. The method of manufacturing an electro-optical device, wherein the temperature is equal to or higher than the film forming temperature of the insulating film and the annealing time is equal to or longer than 10 minutes. 4. The device according to claim 1, wherein the first insulating film is an insulating film disposed between a semiconductor layer of a switching element provided for each pixel and the light-shielding film.
A method for manufacturing an electro-optical device according to claim 3. 5. The semiconductor device according to claim 1, wherein the second insulating film is an insulating film disposed between a layer constituting a switching element provided for each pixel and a wiring drawn from the switching element. A method for manufacturing an electro-optical device according to claim 1. 6. The electro-optical device according to claim 1, wherein the contact hole is disposed outside the image display area.