JPH05203994A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To eliminate the brightness irregularity and crosstalk of a display image and make an excellent image display by decreasing the parasitic capacity between a picture element electrode, and a scanning line and a signal line which are close to it. CONSTITUTION:The liquid crystal display device has an array substrate which has a TFT 107 connected to the scanning line 103 and signal line and the picture element electrode 109 connected thereto, a counter substrate which has a counter electrode facing them, and a liquid crystal layer sandwiched between the array substrate and counter substrate; and an electrostatic shielding electrode 113 which overlaps with at least part of the peripheral edge part of the picture element electrode 109 and also overlaps with at least one of the scanning line 103 and signal line 105 is provided on the array substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to an active matrix type liquid crystal display device using thin film transistors.

[0002]

2. Description of the Related Art Recently, electronic devices have been made smaller, lighter, and have lower power consumption. In the field of display devices, a small, lightweight, low power consumption display that replaces a CRT (Cathode Ray Tube). As a device, flat panel displays have been actively researched and developed.

Among them, the liquid crystal display device is particularly advantageous in that it can display a large area, can display in full color, and can be a display device operating at low current and low voltage. ing. As such a liquid crystal display device, various types of operation systems are used depending on the purpose. Among them, the active matrix liquid crystal display device is capable of displaying full-color moving images with high resolution. It has a lot of attention.

In the active matrix type liquid crystal display device, one pixel is arranged at each intersection of electrodes arranged in a matrix form, a switching element is arranged for each pixel, and pixels connected by this switching element are arranged. Although they are individually driven and controlled, it has been noticed that a thin film transistor (hereinafter, abbreviated as TFT) is used in such an active matrix type liquid crystal display device, and research and development have been actively carried out and already put into practical use. Some have been done.

At present, as a liquid crystal display device for a laptop computer, for example, a diagonal size of 10 inches and a pixel number of about 480 vertical by 640 horizontal are mainstream, but a higher image quality, higher definition direct-view liquid crystal display. Also, research and development aiming at a fine pitch and high definition projection type (projection type) display device is being carried out.

The structure of an active matrix type liquid crystal display device using such a TFT is shown in FIG. 28 by extracting one pixel portion of the TFT array substrate. Also in FIG.
FIG. 4 is an equivalent circuit diagram showing the electrical configuration of the entire one pixel portion.

Scan lines 2 arranged in a row on a glass insulating substrate
801 and a signal line 2803 that is arranged in a row crossing the line 801
A TFT 2805 connected to the scanning line 2801 and the signal line 2803, and a pixel electrode 2 connected to the TFT 2805.
A TFT array substrate 2811 is formed by forming an auxiliary capacitance electrode 2809 facing the pixel electrode 2807 via an insulating film and forming an auxiliary capacitance Cs.
Then, the counter electrode 2813 facing the TFT array substrate 2811, the pixel electrode 2807, and the counter electrode 281.
The main part of the liquid crystal display device is composed of the liquid crystal layer 2815 sandwiched between the liquid crystal layer 283 and the liquid crystal layer 2815.

The apparatus having such a structure is configured so that the scanning line 2801
Is selected, that is, in the scanning selection period, the TFT 28
05 is turned on (conduction state), and the pixel electrode 2807 and the counter electrode 2 are turned on by the voltage applied via the signal line 2803.
The liquid crystal capacitance CLC formed by 813 and the liquid crystal layer 2815 sandwiched therebetween and the auxiliary capacitance CS built in the TFT array substrate 2811 are charged. And scan line 2
During a period in which 801 is not selected, that is, a scanning non-selection period, the TFT 2805 is turned off (high resistance state), and the pixel electrode 2807 is electrically disconnected from the signal line 2803. Then, a voltage equal to or higher than the lighting threshold value is applied to the liquid crystal layer 2815 due to the charges accumulated during the scan selection period.
Is applied to the pixel, the lighting state of the pixel is maintained.

In the active matrix type liquid crystal display device using the TFT as described above, the parasitic capacitance Cgs is provided between the pixel electrode 2807 and the scanning line 2801 and between the pixel electrode 2807 and the signal line 2803, respectively. , Cds are formed. Due to these parasitic capacitances Cgs and Cds, the pixel electrode 2807 causes the scanning line 28
01 and the signal line 2803, the scan line 2
801 and the potential of the signal line 2803 change the pixel electrode 2807.
Influences the voltage of and changes the voltage like noise.

The potential variation of the scanning line 2801 becomes a problem especially when the scan pulse falls, and a potential variation ΔVp called a punch-through voltage occurs according to the voltage change of the scan pulse trailing edge. Here, such potential fluctuation ΔVp takes a value represented by the following equation. ΔVp = {Cgs / (CLC + Cs + Cgs + Cds)} × ΔVg Since there is such a potential variation ΔVp called a punch-through voltage, the potential of the pixel electrode 2807 is the signal line 280.
3 is different from the predetermined signal voltage applied to
Accurate signal voltage writing is hindered. Therefore, in the conventional technique, the potential of the counter electrode 2813 is shifted correspondingly by the potential variation ΔVp, and the potential variation ΔVp called the punch-through voltage is compensated.

However, the CLC is not constant and varies depending on the voltage applied to the liquid crystal and the attitude of the liquid crystal, and it is impossible to keep all Cgs, Cs, and CLC in the screen constant without variation due to manufacturing problems. .. Therefore, ΔVp is not constant even within the same screen and varies from position to position, and it cannot always be sufficiently compensated by adjusting the potential of the counter electrode 2813. As a result, flicker and burn-in occur on the screen.

On the other hand, since the electric potential of the signal line 2803 is not always uniform and fluctuates corresponding to the video signal voltage, the electric potential fluctuation of the pixel electrode 2807 caused by the signal line 2803 is larger than that of the scanning line 2801. Frequent and diverse potential fluctuations. As an example thereof, the state of fluctuation due to frame inversion will be described.

In frame inversion, all signal lines 2803
The potential is the same polarity and the signal line 2803 is set for each frame.
Since the polarity is reversed, the potential fluctuation of the signal line 2803 is greatest when the polarity is reversed. Regarding the potential fluctuation ΔVps of the pixel electrode 2807 at this time, the potential fluctuations of the signal lines 2803 on both the left and right sides forming a parasitic capacitance with the pixel electrode 2807 are ΔVsig1 and ΔVsig2, and the parasitic capacitances are Cds1 and Cds2, respectively. , ΔVps = (Cds1 × ΔVsig1 + Cds2 × ΔVsig2) / (CLC + Cs + Cgs + Cds1 + ds2). This potential fluctuation ΔVps occurs every frame, that is, every time the bottom pixel row of the screen is written. Therefore, when looking at each pixel, the time until writing and ΔVps occurs at the top and bottom of the screen is different, which appears as a positional variation in the brightness of the screen.
This is observed as what is called uneven brightness of the screen.

When Cds1 and Cds2 are further increased, the potential variation of the signal line 2803 causes the potential variation of the pixel electrode 2807, causing crosstalk.

These parasitic capacitances are generated by the TFT array substrate 2
At 811, the following locations are formed. First C
gs is mainly the channel portion of the TFT 2805 and the scanning line 28.
01 and the gate electrode and the pixel electrode 2807 (source electrode) overlap each other. Also Cds1, Cds2
Is mainly formed in a portion where the pixel electrode 2807 and the signal line 2803 are close to each other.

As described above, as liquid crystal display devices have become smaller and higher definition, and the size of one pixel has become smaller and finer, in order to improve the aperture ratio of the pixel and increase the brightness, the distance between the electrodes is further increased. It will be necessary to reduce the distance. When the distance between the electrodes is reduced in this way, the above-mentioned parasitic capacitances Cgs, Cds1, and Cds2 become larger and larger,
Due to this, uneven brightness and crosstalk are more and more prominent, and the quality of the displayed image deteriorates.

On the other hand, the scanning line 2801 and the signal line 280
3 and the pixel electrode 2807 to prevent the light from passing through the gap between the pixel electrode 2807 and the pixel portion and reduce the contrast of the pixel portion.
In order to prevent the T2805 from malfunctioning, a conventional liquid crystal display device uses a light-shielding film called a black matrix or a black mask. This black matrix is usually provided on the counter substrate side, and when the TFT array substrate 2811 and the counter substrate are opposed to each other, the black matrix is aligned so that the opening of the black matrix is located at the portion to be opened. It was

However, as the liquid crystal display device becomes smaller and higher definition as described above, and the size of one pixel is further miniaturized, further miniaturization is required to improve the aperture ratio of the pixel and increase the brightness. Pixel electrodes and a black matrix must be formed with a pattern size and precision, and the counter substrate (not shown) and the TFT array substrate 2811 must be finely and finely aligned, which makes the manufacturing more difficult.

[0019]

As described above, the conventional liquid crystal display device has a problem that uneven brightness and crosstalk occur due to the parasitic capacitance.

Further, as the pixels become finer and finer, the pattern accuracy and alignment tolerance of the pixel electrode and the black matrix become more and more strict and severe, and there is a problem that their manufacture becomes more and more difficult. ..

The present invention has been made to solve such a problem, and an object thereof is to reduce a parasitic capacitance between a pixel electrode and a scanning line or a signal line in the vicinity of the pixel electrode to display an image. An object of the present invention is to provide a liquid crystal display device that eliminates unevenness in image brightness and crosstalk and realizes excellent image display.

[0022]

A liquid crystal display device according to the present invention comprises a scanning line arranged in a row, a signal line arranged in a row intersecting with the scanning line, and a thin film transistor element connected to the scanning line and the signal line. An array substrate having a pixel electrode connected thereto, a counter substrate having a counter electrode facing the array substrate, and a liquid crystal layer sandwiched between the array substrate and the counter substrate, and a peripheral edge of the pixel electrode It is characterized in that a shield electrode having an electrostatic shielding property is provided on the array substrate so as to overlap at least a part of the portion and at least one of the scanning line and the signal line.

The shield electrode is made of a material having a high light-shielding property, and also serves as a light-shielding film that blocks light transmission in a gap between the scanning line or the signal line and the pixel electrode, that is, a so-called black mask. You may do it.

The shield electrode may also be used as one electrode of the auxiliary capacitance and the storage capacitance connected in parallel to the liquid crystal capacitance of the pixel.

The shield electrode may be in an electrically floating state, or a voltage may be applied.

[0026]

The parasitic capacitance formed between the pixel electrode and the scanning line or between the pixel electrode and the signal line is determined by the shape of the two electrodes and the dielectric constant of the surrounding material. Is greatly affected by.

Therefore, for example, when a shield electrode set to a constant potential is provided between the two electrodes of the pixel electrode and the signal line, the line of electric force which is going to be connected between the pixel electrode and the signal line is the shield electrode. Is blocked by the electrostatic shielding effect of
Or it decreases.

Such an electrostatic shielding effect is not limited to the case where the shield electrode is arranged so as to shield between the pixel electrode and the two electrodes of the signal line, and the insulating layer is formed above or below each of the two electrodes. It also occurs sufficiently effectively when they are arranged so as to overlap each other. By blocking or reducing such lines of electric force, for example, the parasitic capacitance between the pixel electrode and the two electrodes of the signal line is eliminated.

In the liquid crystal display device of the present invention, parasitic capacitance is provided by a shield electrode which is arranged so as to overlap at least a part of the peripheral portion of such a pixel electrode and at least one of the scanning line and the signal line. Therefore, it is possible to realize high-quality image display while avoiding uneven brightness and crosstalk.

If the shield electrode is made of a material having a high light blocking property, the shield electrode is arranged so as to overlap the pixel electrode and the scanning line or the signal line as described above, so that it is so-called black. It can also be used as a light-shielding film such as a matrix.

Further, since the shield electrode is arranged so as to partially overlap with the pixel electrode as described above, an auxiliary capacitance using an insulating film or the like as a dielectric is formed at a portion partially overlapping with the pixel electrode. It can also be used as an auxiliary capacitance electrode.

[0032]

Embodiments of the liquid crystal display device of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a diagram showing the structure of one pixel portion of the liquid crystal display device of the first embodiment, FIG. 2 (a) is a sectional view taken along the line AA 'showing its layer structure, and FIG. ) It is a BB 'sectional view.

In the liquid crystal display device of the first embodiment, scanning lines 103 arranged in a row on a glass insulating substrate 101, signal lines 105 arranged in a row intersecting with the scanning lines 103, and these scanning lines 1 are arranged.
03 and the TFT 107 connected to the signal line 105,
The pixel electrode 109 connected to this and the gate insulating layer 11
1, the shield electrode 11 overlaps all four sides of the peripheral edge of the pixel electrode 109 and overlaps part of the signal line 105.
3 is formed, and the TFT array substrate 115 is formed. Although not shown, the TFT array substrate 11
The main part is composed of a counter substrate having a counter electrode facing 5 and a liquid crystal layer sandwiched between the counter substrate and the TFT array substrate 115.

The liquid crystal display device according to the first embodiment is characterized in that the shield electrode 113 overlaps all four sides of the peripheral edge of the pixel electrode 109 and part of the signal line 105.
In addition, the auxiliary capacitance 117 is formed at the portion where the pixel electrode 109 and the shield electrode 113 overlap with each other through the gate insulating layer 111.

Next, a method of manufacturing the liquid crystal display device of the first embodiment having such a structure will be described. A Mo-Ta alloy is deposited to a thickness of 250 nm on the glass substrate 101 and patterned to form the scanning line 103 and the shield electrode 113 at the same time. Subsequently, SiO _x and SiN _x are respectively formed on the above as a gate insulating layer 111 to have a film thickness of 300 nm and 50 nm, respectively.
-Si and SiN _x as a channel protective film are 50
nm and 200 nm are formed. And Si of the channel protective film
After N _x is etched and formed into an island shape, an n ⁺ a-Si layer as an ohmic contact layer is deposited to a thickness of 50 nm. After that, n ⁺ a-Si and a-Si are etched in an island shape, ITO is then deposited to a thickness of 100 nm, and this is patterned to form a pixel electrode 109. Then, gate insulation on the extraction portion of the scanning line 103 is performed. The layer 111 is removed by etching, Cr and Al are deposited at 50 nm and 300 nm, respectively, and patterned to form the signal line 105, the drain electrode, and the source electrode.

Then, by using the signal line 105 as a mask, n ⁺ between the source electrode and the drain electrode of the TFT 107 is increased.
The TFT array substrate is formed by selectively removing the a-Si layer from the channel protective layer by etching.

Then, the TFT array substrate 115 and the counter substrate are combined, the periphery thereof is sealed with a sealant, and the liquid crystal composition is injected between the both substrates to complete the liquid crystal display device.

As described above, the liquid crystal display device of this embodiment is
A shield electrode 113 is provided in the same layer as the scanning line 103 on the glass substrate 101, a gate insulating layer 111 is provided so as to cover them, and a pixel electrode 109 and a signal line 105 are provided thereon. Has been done. And shield electrode 1
The reference numeral 13 is connected to a power source, a predetermined voltage is applied thereto, and is arranged so as to have a constant potential over all the pixels.

In the liquid crystal display device of the present embodiment having such a configuration, the lines of electric force from the pixel electrode 109 to the signal line 105 are greatly reduced by the electrostatic shielding effect of the shield electrode 113, so that the pixel electrode 109 and the signal line Parasitic capacitance that tends to be formed between the line 105 and the line 105 is eliminated, and it is possible to prevent uneven brightness and crosstalk that are caused by this parasitic capacitance.

In addition, the shield electrode 113 and the scanning line 103
Means that a film made of a material such as Mo-Ta alloy deposited in the same layer as described above can be simultaneously formed by patterning by etching. Therefore, it is necessary to add a new step for forming the shield electrode 113. Therefore, the manufacturing process can be simplified.

Further, the pixel electrode 109 and the shield electrode 11
An auxiliary capacitance 117 is formed at a portion overlapping with 3 through the gate insulating layer 111. That is, the shield electrode 113
Since it also serves as the auxiliary capacitance electrode of the auxiliary capacitance 117, the structure and manufacturing process can be simplified as compared with the case where the auxiliary capacitance electrode is provided separately.

According to the experiments conducted by the present inventors, the punch-through voltage and the pixel potential fluctuation due to the frame inversion are detected, and compared with the conventional device, the shield electrode 113 is formed so that the pixel electrode 109 and the signal line 105 are connected to each other. Parasitic capacitance Cds1, C
It was confirmed that ds1 2 was significantly reduced.

(Embodiment 2) FIG. 3 is a diagram showing the structure of one pixel portion of the liquid crystal display device of the second embodiment, FIG. 4 (a) is a sectional view taken along the line AA 'showing its layer structure, and FIG. ) Is the BB 'sectional view. The same components as those in the first embodiment are designated by the same reference numerals as those in FIGS.

In the liquid crystal display device according to the second embodiment, the shield electrode 213 includes the scanning line 103 and the signal line 1.
05, and the shield electrode 213
Is used as a light-shielding film, so-called black matrix, and the shield capacitor 213 is used as an electrode to form the auxiliary capacitor 217.

The shield electrode 213 overlaps all four sides around the pixel electrode 109 with the gate insulating layer 111, the second gate insulating layer 215, and the third insulating layer 219 interposed therebetween, and a part of the signal line 105 is gate insulated. The layer 111 and the second gate insulating layer 215 are provided so as to overlap with each other, and part of the scan line 103 is provided so as to overlap with the second gate insulating layer 215. In addition, the pixel electrode 109 and the signal line 105 are separated by an insulating layer 219, so that a short circuit can be reliably prevented.

Similar to the operation described in the first embodiment, the electrostatic shielding effect of the shield electrode 213 causes the space between the scanning line 103 and the pixel electrode 109 and the space between the signal line 105 and the pixel electrode 109. Parasitic capacitance is eliminated.

The material of the shield electrode 213 is Mo-
Ta alloy and S for the second gate insulating layer 215
iO _x was used, and SiN _x was used as the third insulating layer 219. Since a material having a high light blocking property such as Mo-Ta alloy is used as the shield electrode 213, the portion covered with the shield electrode 213, that is, the gap between the pixel electrode 109 and the scanning line 103, and the pixel electrode 109 and the signal. Line 1
Light does not pass through the gap 05 and only the pixel electrode 109 that is not covered with the shield electrode 213 transmits light, so the shield electrode 213 also has a function as a black matrix. This allows
The conventional black matrix on the counter substrate side can be omitted. However, at this time, a black matrix is provided on the counter substrate in the portion corresponding to the vicinity of the TFT 107 to make the light-shielding property against the light from the counter substrate and the reflected light on the inner surface of the main surface side of the glass substrate more reliable. Preferably.

If the black matrix near the signal line 105 and the scanning line 103 is left and color separation is performed for each pixel of the color filter in this black matrix, the color filter is inspected as compared with the case where the black matrix is omitted. However, the black matrix on the counter substrate side is not always required to be omitted, because it can be easily performed and the manufacturing yield can be improved.

However, a black matrix in which the opening of the counter electrode is wider than the opening of the shield electrode is supplementarily used so that one of them defines the opening even if the positions of the two are deviated in the manufacturing process. Is desirable. Although illustration is omitted, in this embodiment, a black matrix having an opening wider than the opening of the shield electrode 213 by a distance of 8 μm is additionally used. Thereby, even if a pattern shift occurs, it is possible to reliably shield light.

(Embodiment 3) FIG. 5 is a diagram showing the structure of one pixel portion of the liquid crystal display device of the third embodiment, and FIG. 6 is a sectional view taken along the line AA 'showing its layer structure.

The same components as those in the first and second embodiments are designated by the same reference numerals as in FIGS.

The liquid crystal display device of the third embodiment has the second
The liquid crystal display device according to the embodiment of
09, a shield electrode 313 is formed so as to overlap the periphery of 09 and part of the scanning line 103 and the signal line 105, and this is also used as a light-shielding film, a so-called black matrix, and the auxiliary capacitor 317 provided in the central portion of the pixel The structure is also used as the auxiliary capacitance electrode, and the manufacturing method thereof is characterized in that the pixel electrode 109 is formed by self-alignment using the shield electrode 313.

A second gate insulating layer 215 and a gate insulating layer 111 are formed so as to cover the shield electrode 313, a scanning line 103 is formed between the layers, and a pixel electrode 109 is formed on the uppermost layer.

When forming the pixel electrode 109, ITO is used.
After the film is deposited, the back surface is first exposed using a negative resist or an image reverse resist, and then, a portion overlapping the source electrode from the front surface (main surface) and a portion where the auxiliary capacitance 317 is formed are exposed by using a photomask, and the pixel electrode is exposed. Form 109. In this case, the signal line 105 and the scanning line 103
Pixel electrode 109 as compared with the case of self-aligning only by itself
Since a large distance can be set between the signal line 105 and the scanning line 103, the parasitic capacitance therebetween can be further reduced.

Further, since the shield electrode 313 is formed so as to overlap the periphery of the pixel electrode 109 and part of the scanning line 103 and the signal line 105 as described above, this is also used as a black matrix. The black matrix on the counter substrate side can be omitted as in the above embodiment.

This shield electrode can be formed in any layer through an insulating layer such as the gate insulating layer 111, as long as it is lower than the layer of the pixel electrode 109.

(Embodiment 4) FIG. 7 is a diagram showing the structure of one pixel portion of the liquid crystal display device of the fourth embodiment, FIG. 8A is a sectional view taken along the line AA 'showing the layer structure thereof, and FIG. ) Is the BB 'sectional view. The same components as those in the first embodiment are designated by the same reference numerals as those in FIGS.

The liquid crystal display device of the fourth embodiment has the second
The liquid crystal display device of this embodiment is further improved, and its layer structure is almost the same as that of the second embodiment, but the shield electrode 413 is formed of a transparent conductive film such as ITO, and the entire surface of the pixel electrode 109 is formed. Placed so as to face the gate insulating layer 1
The storage capacitor 417 is characterized in that the area of the storage capacitor 417 can be increased by forming the storage capacitor 417 via the gate electrode 11 and the second gate insulating layer 215. ITO (indium oxide / tin) was used as the material of the shield electrode 413.

Since the value of the formed auxiliary capacitance 417 depends on the area of the pixel electrode 109 which overlaps with the shield electrode 413, in the present embodiment, as shown in FIG. 7, the shield electrode 413 is formed from the entire surface of the pixel electrode 109. Also formed in a large area. However, the area of the shield electrode 413 is preferably set to an appropriate value because it cannot be increased because of problems in TFT performance such as drive current characteristics. For example, the capacitor may be formed in a shape that overlaps with the upper half of the pixel electrode to set the capacitance to about half of that of the present embodiment.

(Embodiment 5) FIG. 9 is a diagram showing the structure of one pixel portion of the liquid crystal display device of the fifth embodiment, and FIG. 10 is a sectional view taken along the line AA 'showing the layer structure thereof. The same components as those in the first embodiment are designated by the same reference numerals as those in FIGS.

The liquid crystal display device according to the fifth embodiment has the first
In the liquid crystal display device of the above embodiment, an auxiliary capacitance 517 is formed at a portion where the shield electrode 513 and the pixel electrode 109 overlap with each other with the gate insulating layer 111 interposed therebetween, and the shield electrode 513 forms one of the signal lines 105. The feature is that they are arranged so as to overlap over the entire portion corresponding to the pixel. By arranging the shield electrode 513 in this way, electrostatic shielding in the vicinity of the signal line 105 can be performed more effectively than in the first embodiment, and as a result,
The parasitic capacitances Cds1 and Cds2 can be reduced more effectively.

Further, by disposing the shield electrode 513 so as to overlap the entire portion corresponding to one pixel of the signal line 105 in this manner, even if the width of the signal line 105 becomes finer, the shield electrode 513. There is also a margin in width, and there is also no concern about a pattern shift or the like, so that there is also an advantage that manufacturing is simple.

(Embodiment 6) FIG. 11 is a plan view showing the structure of one pixel portion of a liquid crystal display device according to a sixth embodiment, and FIG.
(A) is an AA 'sectional view showing the layer structure, and (b) is a BB' sectional view. The same components as those in the first and fifth embodiments are designated by the same reference numerals as those in FIGS.

The liquid crystal display device of the sixth embodiment is the fifth embodiment.
In a further improvement of the liquid crystal display device of the embodiment, the pixel electrode 109 is formed in the layer of the gate insulating layer 111, and the signal line 105 is arranged on the gate insulating layer 111, and the pixel electrode 109 and the pixel electrode 109 are formed. The feature is that the structure is configured to reliably prevent a short circuit with the signal line 105. The shield electrode 613 is arranged below the pixel electrode 109 via the gate insulating layer 111.

Accordingly, in addition to the electrostatic shielding effect and the light shielding effect of the shield electrode 613, the pixel electrode 109 and the signal line 105 can be brought close to each other without causing a short circuit, and the aperture ratio of the pixel electrode 109 is further improved. The effect of being able to do is also realized.

Next, a method of manufacturing the liquid crystal display device of the sixth embodiment will be described.

Mo-Ta alloy is deposited on the glass substrate 101.
Deposit 50 nm, pattern this and scan line 103
And the shield electrode 613 are formed at the same time. 200nm and SiO _x to be a gate insulating layer 111 on top thereof followed
accumulate. It is desirable that the SiO _x film is deposited in 100 nm portions twice in order to prevent a short circuit between the pixel electrode 109 and the shield electrode 613 due to a pinhole defect or the like.

Subsequently, an ITO film was deposited to a thickness of 100 nm and patterned to form a pixel electrode 109, and then SiO _x and SiN which will become a gate insulating layer 111 to cover the pixel electrode 109.
_x is deposited to 100 nm and 50 nm, respectively. 200n of the above
The gate insulating layer 111 is formed by the SiO _{x of} m and the SiO _x and SiN _x, and the pixel electrode 109 is provided in the layer.

An active layer a is formed on the gate insulating layer 111.
-Si and SiN _x as a channel protective layer are 50
nm, 200 nm is deposited. And Si of the channel protection layer
After N _x is etched and formed into an island shape, an n ⁺ a-Si layer as an ohmic contact layer is deposited to a thickness of 50 nm. Here, when SiN _x is deposited on the ITO by plasma CVD,
It is known that defects such as film peeling and surface turbidity occur. SiN _x can be deposited by avoiding such defects by appropriately selecting the deposition conditions, but it has been found that when such SiN _x is used as the gate insulating layer, the characteristics of the TFT are deteriorated. Therefore, in this embodiment, SiO _x is used as the film deposited on ITO, because it is desirable.

After that, n ⁺ a-Si and a-Si are etched in an island shape to form the gate insulating layer 1 in the portion where the scanning line 103 is taken out and where the pixel electrode 109 is electrically connected.
A contact hole is drilled in 11 by BFH.

Then, Cr and Al are 50 nm and 3 respectively.
The signal line 105 is formed by depositing 00 nm and patterning it.
And a drain electrode and a source electrode are formed.

Then, by using the signal line 105 as a mask, n ⁺ between the source electrode and the drain electrode of the TFT 107 is increased.
The a-Si layer is selectively etched away from the channel protection layer to form a TFT array.

Although not shown in the figure, Si is formed on the TFT.
Since it is known that the reliability of the TFT is improved by covering with N _x , SiN _x on the TFT 107 is 200 nm.
After deposition, each electrode extraction portion and pixel electrode 109
The upper SiN _x was removed by etching. At that time, if the SiO _x on the pixel electrode 109 is also removed by etching, the image quality is further improved. However, if the SiO _x on the pixel electrode 109 is left, the pixel electrode 1 due to, for example, a conductive foreign substance mixed in during the manufacturing process is used.
The short circuit between 09 and the counter electrode can be prevented.

Then, the TFT array substrate 115 and the counter substrate are combined, the periphery thereof is sealed with a sealant, and the liquid crystal composition is injected between both substrates to complete the liquid crystal display device.

Although SiO _x is deposited by plasma CVD in this embodiment, thermal CVD is more preferable.

Further, in this embodiment, the film thickness of the SiO _x film used as the dielectric of the auxiliary capacitor 517 is 200 nm, which is thinner than the film thickness of 300 nm of the fifth embodiment, but the shield electrode 613. The occurrence of a short circuit between the pixel electrode 105 and the pixel electrode 105 was reduced to about 1/2. As a result of comparing and examining the fifth and sixth embodiments, it was found that this was due to the following facts.

Since the channel protective layer is selectively etched with the a-Si layer when the island-shaped etching is performed, the etching stops at the a-Si layer in principle.
In reality, if there is a pinhole defect, the etchant may penetrate into the gate insulating layer 111 through the pinhole and a hole may be opened in the gate insulating layer 111.
When O is deposited, ITO is also deposited in this hole, causing a short circuit failure. However, in the liquid crystal display device of the present embodiment, the pixel electrode 109 made of ITO is formed in a step prior to the step of etching the channel protective layer, and
The ITO film annealed at a temperature of 00 ° C. or higher has extremely high resistance to the etchant used for etching the channel protective layer, and the above-mentioned short circuit failure is caused by pinhole defects in the ITO film and pinholes in the a-Si layer. It rarely occurs except when the defect overlaps with the same position. Therefore, in this embodiment, the shield electrode 613 is
It is considered that the occurrence of a short circuit between the pixel electrode 105 and the pixel electrode 105 is reduced to about 1/2.

(Embodiment 7) FIG. 13 is a plan view showing the structure of one pixel portion of a liquid crystal display device according to a seventh embodiment, and FIG.
(A) is an AA 'sectional view showing the layer structure, and (b) is a BB' sectional view. The same components as those in the first and sixth embodiments are designated by the same reference numerals as those in FIGS. 1, 2, 11, 12 and the like.

The liquid crystal display device of the seventh embodiment is the sixth embodiment.
In the liquid crystal display device of the above embodiment, the shield electrode 713, the scanning line 103, the pixel electrode 109, and the signal line 105 are connected to the gate insulating layer 111, the second gate insulating layer 215, and the third insulating layer, respectively. The layers are separated by inserting the layer 219 so that these short-circuit defects can be more surely prevented and the pattern of the shield electrode 713 can be freely set. As a result, the aperture ratio of the pixel electrode can be made wider, the screen brightness is improved, and the shield electrode 713 overlaps almost the entire surface corresponding to one pixel of the signal line 105, so that the electrostatic shielding effect is also high. Has become.

The shield electrode 713 can be arranged so as to overlap the scanning line 103 as long as there is no problem of scanning pulse delay or potential fluctuation of the shield electrode. In this case, the shield electrode 713 is black. It can also be used as a matrix.

(Embodiment 8) FIG. 15 is a plan view showing the structure of one pixel portion of the liquid crystal display device of the eighth embodiment. The liquid crystal display device according to the eighth embodiment has an improved manufacturing method in the liquid crystal display device according to the seventh embodiment, and a shield electrode 813 is provided.
The pixel electrode 109 is formed by self-alignment using.

For the pixel electrode 109, after forming an ITO film, an unnecessary portion of the portion not overlapping the shield electrode 813 is exposed and developed by mask exposure using an image reverse resist.

Subsequently, after backside exposure and mask exposure, image reverse baking is performed and the entire surface is exposed to form a pattern. Such a manufacturing method is suitable for manufacturing a liquid crystal display device having a structure in which the shield electrode 813 and the scanning line 103 are not overlapped, and when the pixel electrode 109 made of an ITO film is formed before the signal line 105. Can also be used. Most of the auxiliary capacitance 517 can be formed by the final mask exposure. (Embodiment 9) FIG. 16 is a sectional view showing the layer structure of a pixel portion of a liquid crystal display device according to a ninth embodiment. The same components as those of the first and sixth embodiments are shown in FIGS.
The same numbers as 1, 12 and the like are shown.

In the liquid crystal display device of the sixth embodiment, as described above, the patterning of the passivation layer is included.
It required a patterning process. However, in the liquid crystal display device having such a configuration, the present inventors have revealed as a result of research that the step of leaving the a-Si layer in an island shape can be omitted. A method of manufacturing such a 6-step patterning step will be described with reference to FIG.

Mo—Ta alloy is deposited on the glass substrate 101.
Deposit 50 nm, pattern this and scan line 103
And the shield electrode 613 are formed at the same time.

Subsequently, SiO _x to be the gate insulating layer 111 is deposited on each of them twice in 130 nm increments.

Next, an ITO film is deposited and patterned to form a pixel electrode 109, and then SiO _x and SiN _x to be the gate insulating layer 111 are deposited so as to cover the pixel electrode 109 at 90 nm and 50 nm, respectively.

The above 200 nm SiO _{x and} this Si
The gate insulating layer 111 is formed of O _x and SiN _x, and the pixel electrode 109 is provided in the layer.

Successively, a-Si of the active layer 1601 and SiN _x as the channel protective layer 1603 are deposited on the gate insulating layer 111 by 50 nm and 200 nm, respectively.

The channel protective layer 1603 is made of SiN _x.
Is etched into an island shape, and then an n ⁺ a-Si layer as the ohmic contact layer 1605 is deposited to a thickness of 50 nm.

After that, the pixel electrode 109 and the scanning line 10
A through hole 1607 is formed at the extraction portion of 3.
At this time, the through hole 1607 is the uppermost n ⁺ a-Si.
From the layer to the SiO _x film of the gate insulating layer 111 are continuously etched and punched.

Then, Mo / Al / Mo is deposited and patterned to form the signal line 105, the drain electrode 1609, and the source electrode 1611.

Then, using the signal line 105 and the like as a mask, the n ⁺ a-Si layer between the source electrode 1611 and the drain electrode 1609 of the TFT 107 is used as the channel protection layer 1.
603 is selectively removed by etching, and the pixel electrode 1
The a-Si layer on 09 is etched away to form a TFT array.

Further, 200 n of SiN _x is deposited on the TFT 107.
m after deposition, each electrode extraction portion and pixel electrode 10
The SiN _x on 9 was removed by etching. that time,
At the same time, the SiO _x on the pixel electrode 109 is also removed by etching.

As described above, the patterning process can be performed six times. This is preferable because productivity is improved. Further, conventionally, there is a case where the island-shaped semiconductor layer pattern does not exist at a place where it should exist in the design due to the pattern disorder during the patterning of the semiconductor layer. However, it was confirmed that in the liquid crystal display device of the present embodiment, the production yield can be improved while avoiding such defects.

The process of forming the through hole 1607 will be described with reference to FIG.

First, the ohmic contact layer 1605 made of n ⁺ a-Si and the active layer 160 made of a-Si.
1. A part of the gate insulating layer made of SiN _{x is} removed by etching using a resist 1613 by CDE (chemical dry etching) using a gas containing CF ₄ as a main component, and patterned. (A) Then, the SiO _x film of the gate insulating layer 111 is etched with BHF to form through holes 1607 and the like, and the Mo-Ta layer surface such as the scanning line 103 extraction portion underneath is exposed. (B) At this time, the ohmic contact layer 1605 as an upper layer
⁺ Active layer, n ⁺ a-Si film, a-Si film, SiN _x
The film projects like eaves on the wall surface of the through hole 1607.
(C) Then, a CDE process is further performed using a gas containing CF ₄ as a main component to remove the eave-shaped protrusions of the n ⁺ a-Si film, the a-Si film, and the SiN _x film by etching. SiO _x
It is processed so that it will be sufficiently retracted from the wall surface of. At this time
It is desirable to set back about 0.1 to 3 μm. At this time, the oxide and the like on the exposed Mo-Ta surface are also lightly removed by etching, so that Mo / Al deposited thereafter is removed.
The electrical connection with the / Mo film is further improved.
(D) Although the through-hole 1607 has the eave-shaped protrusion removed, there is a stepped portion and the coverage of the material placed on it is poor, and a mouse hole is formed when the stepped portion is exposed to an etching solution during etching. Since there are many cases of so-called disconnection, it is preferable to set a wiring pattern made of a Mo / Al / Mo film deposited above the through hole 1607 larger than the pattern of the through hole 1607 as in this embodiment.

The formation of the through hole is not limited to the above process, and reactive ion etching (R) is performed to prevent undercut of SiO _x , for example.
IE) may be used, but when SIO _x is etched by RIE, it is necessary to selectively etch the underlying Mo-Ta, and under that condition, the etching rate of SIO _x is only about 500 angstrom / min. Productivity is low because it cannot be obtained. Since the characteristics of TFT107 surface dirt when resist is applied on n ⁺ a-Si may deteriorate, the Mo is deposited to about 500 Å on the n ⁺ a-Si, an etching removal of Mo after the through hole forming Preferably. Further, the omission of the patterning step of the a-Si film can be applied to the liquid crystal display device of the other embodiments, and is not necessarily limited to the combination with the shield electrode. For example, the layer structure can be applied to various configurations as shown in FIGS.

In the case of the structure shown in FIGS. 21 and 22, it is not necessary to form a through hole on the pixel electrode 109, but it is preferable to use the above-mentioned process at the extraction portion of the scanning line 103. .. Further, in the case of FIG. 22, the passivation layer 161 on the shield electrode 613.
5 may be removed by etching in order to increase the auxiliary capacity.

Further, if the structure shown in FIG. 22 is used,
Since the through hole on the side connecting the source electrode 1611 and the pixel electrode 109 and the extraction portion of the scanning line 103 are formed in the same step, and the TFT array can be formed by five patterning steps, the productivity is further improved. At this time, etching is performed by RIE using S of the passivation layer 1615.
After performing the process from the iN _x film to the SiN _x film of the gate insulating layer 111, subsequently etching the SiO _x film with BHF, and performing the same CDE treatment as described above, an eave-like shape without protrusion was obtained.

In particular, in the example shown in FIG. 22, the pixel electrode 109 is formed on the passivation layer 1615, and the total thickness of the insulating film used as the dielectric of the auxiliary capacitance can be increased. Electrode 613
This is particularly effective when it is necessary to largely overlap the pixel electrode 109 with the pixel electrode 109 and to suppress the value of the auxiliary capacitance.

(Embodiment 10) FIG. 23 is a sectional view showing a layer structure of a pixel portion of a liquid crystal display device according to a tenth embodiment. It should be noted that the same components as those in the above-described embodiment are denoted by the same reference numerals.

For example, in the liquid crystal display device of the above-described embodiment as shown in FIG. 11, an insulating layer such as a gate insulating layer is used to prevent short circuit of the pixel electrode, the shield electrode, the signal line, the scanning line and the like. However, if the number of such insulating layers is increased, the number of film forming steps is increased, resulting in an increase in manufacturing cost. This is because the cost of film formation is increased by using an expensive device such as a plasma CVD device, a used gas, and a film material.

Therefore, it is desired to form an insulating layer at low cost, and in order to realize this, a method of anodizing the surface of the shield electrode is preferable. Further, according to anodic oxidation, pinholes are not generated, so that it is possible to avoid the occurrence of interlayer short circuit.

The shield electrode 1013 and the scanning line 103 are set to A
A thin film is formed on the glass substrate 101, and its surface is subjected to constant current oxidation in boric acid up to 100 V, and then constant current oxidation for 30 minutes to form Al ₂ O ₃ 2301.

After that, an ITO film is formed by sputtering and patterned to form the pixel electrode 109.

Next, the gate insulating film 111 is formed of a SiO _x film,
Alternatively, it is formed of a laminated film of a SiO _x film and a SiN _x film. An a-Si film is formed thereon, and the SiN _x film is patterned to form a channel protective layer 1603. Then, after depositing the n ⁺ a-Si film, the a-Si film is patterned into an island shape to form an active layer 1601.

Then, Al / Mo is laminated by sputtering to form a source electrode 1611 and a drain electrode 1609. Forming a Pajji coacervation layer made of the SiN _x film so as to cover the top of this, the SiN _x of the pixel electrode 109 portion and the wiring lead-out portion removed by etching.

The shield electrode 1013 and the scanning line 10 described above.
3 etc. is not limited to Al, but Ta, TaN _x , Ti, Nb, T
It may be formed of a material such as a laminated film of iN _x and TaN _x / Ta / TaN _y .

In particular, when a Ta or TaN _x anodic oxide film is laminated with an ITO film and then an a-Si film is formed by plasma CVD, In and Sn diffuse in the anodic oxide film and leak. The current increases. Therefore, as shown in FIG. 24, SiO _x , SiN _x or TiO _x , AlO
1000 angstrom, preferably using a material such as _x , which has an ion radius smaller than In and Sn,
A thin film 2401 with a film thickness of 200 to 500 angstrom
By forming it between the a-type anodic oxide film and the ITO film, it is possible to prevent In and Sn from diffusing into the anodic oxide film and avoid an increase in leak current.

Further, an alloy in which Ta or TaN _x is mixed with Si may be used. Or TaSiN _x / Ta /
Wiring may be formed by a laminated structure of TaN _x and the surface thereof may be anodized.

Forming the gate insulating film 111 by sputtering is also effective in suppressing the leak current.

By adopting such a structure and its manufacturing method, an expensive plasma CV is manufactured in the manufacturing process.
The number of D film forming steps can be reduced, and the manufacturing cost can be reduced.

In addition, Al ₂ O ₃ , TaO _x , TaN _x O
_y , TiO _x , Ta-Si-O, and Ta-Si-N-O each have a relative dielectric constant of 7, 30, 20, 85, 20, and 15;
Shield electrode 101 because it is larger than SiO _x 4
There is an advantage that the value of the auxiliary capacitance using 3 for one electrode can be increased in a small area.

Further, if a film formed by plasma CVD has dust in the working atmosphere, pinhole defects are likely to occur, and short-circuit defects due to the pinhole defects are likely to occur. Therefore, the film thickness may be increased to some extent. is necessary. On the other hand, TF
The thickness of the gate insulating layer used for T107 is the sum of the insulating layer above the ITO pixel electrode 109 and the insulating layer below, but if the film thickness is too large and the capacitance is small, the on-current will be sufficient. Since the film cannot be removed, it is not preferable that the film thickness is too thick. Therefore, it is effective to form the thin film 2401 and the like, which are insulating layers, from a material having a high relative dielectric constant.

On the other hand, when the signal line 105 and the pixel electrode 109 overlap each other due to pattern disturbance, the pixel may be defective in display due to the coupling capacitance formed between them. In order to suppress it, it is effective to reduce the capacitance value. Therefore, it is effective to interpose an insulating film such as SiO _x having a relative dielectric constant smaller than that of the liquid crystal in a layer as thick as possible between the signal line 105 and the pixel electrode 109. It is effective to use an anodic oxide film for the insulating layer.

(Embodiment 11) Penetration voltage; When ΔVp is different for each position in the screen, it is impossible to set an appropriate counter electrode voltage offset for all pixels in the screen, and flicker In addition, image display defects such as interference fringes and image sticking occur, which is a factor that significantly deteriorates the display quality.

Therefore, it is necessary to take measures to suppress such punch-through voltage. This will be described below with reference to FIG.

When the shield electrode and the pixel electrode are overlapped with each other to form an auxiliary capacitance, if the overlapping width forming the auxiliary capacitance 2501 is set to the optimum width; WCS, the punch-through voltage; ΔV
The inventors have confirmed that the distribution width of p in the screen is reduced.

Required TF for certain Cs0 and Clc-max
T size; W is determined. Here, the auxiliary capacity 2501
Width that forms a line; the capacitance value C when Wcs is changed
Since s changes, it is necessary to change the W correspondingly. However, penetration voltage; Wcs of ΔVp,
Considering the change due to the variation of W, there is an optimum width; Wcs determined by it. That is, the variations in line width between the scanning line and the shield electrode serving as the electrode of the auxiliary capacitance are canceled out. By setting such WCS, the punch-through voltage ΔVp can be minimized.

Then, several kinds of TFT-LCDs in which Wcs and W were changed were actually manufactured, and the penetration voltage in the screen; ΔVp was measured. At this time, the gate electrode width; Lg =
The thickness of the TFT 107 was 13 μm, and the TFT 107 used was a self-alignment type in which the channel protective layer was formed by self-alignment with the gate electrode. However, in the process of forming the gate and shield electrodes, the line width distribution (positional variation) was intentionally set to about 1 μm. The state of the distribution is shown in FIG.

The method of obtaining WCS described above will be described in more detail below using mathematical expressions.

Here, Lg; gate electrode width Wis; channel protective layer length Lcs; overlapping length of pixel electrode and shield electrode forming auxiliary capacitance Wcs; auxiliary capacitance width (= area of auxiliary capacitance / Lcs) Cgi; capacitance value of gate insulating layer per unit area Csi; capacitance value of auxiliary capacitance per unit area Cso; capacitance value of design auxiliary capacitance (design value) Cs; capacitance value of auxiliary capacitance (actual value) ) Clc-max; maximum value of liquid crystal capacity of one pixel Clc-min; minimum value of liquid crystal capacity of one pixel Cgs; parasitic capacitance Wo between gate (scan line) and source (pixel electrode); width of designed TFT (Design value) W: TFT width (actual value varying with Cs) Vg: Scan line applied voltage β: Constant (where β = (Clc-max + Clc-min) /
2Clc-max). In this embodiment, Wis = W + 5 μm. Penetration voltage; ΔVp is ΔVp = (Vg · Cgs) / (Cs + βClc-max) Cgs = Lg · Wis · Cgi / 2 Cs = Lcs · Wcs · Csi where α = (Cso + Clc-max) / WoW = ( Wcs · Lcs · Csi + Clc-max) / α In the formation of the gate electrode and the shield electrode that also serves as the scanning line or the electrode of the auxiliary capacitance, if the pattern width completed is X with respect to the pattern width of X0 by design, dCgs / dX = (dCgs / dLg) × (dLg / dX) = (Wis · Cgi / 2) × 1 dCs / dX = (dCs / dWcs) × (dWcs / dX) = Lcs · Csi / 2 From the above, (1 // Vg) × (dΔVp / dX) = (Wis · Cgi / 4) × {2 (Cs + β · Clc-max) -Lg · Lcs · Csi} / (Cs + β · Clc-max) ² where X changes Therefore, to minimize the change in ΔVp, set Wcs so that dΔVp / dX = 0 It may be Re. Therefore, such an optimal Wcs is
Wcs = (Lg-Lcs-Csi-2β-Clc-max) / (2
Lcs / Csi) is recommended.

In the case of this embodiment, the liquid crystal display device of the seventh embodiment has the same structure as that of the seventh embodiment, but the main parameters are as follows: Lg = 13 μm, Lcs = 550 μm, Clc-max /
Clc-min = 0.35pF / 0.14pF, Csi = 1.8 × 10 -4 pF
/ Μm ² and substituting into the above equation, the optimum value is Wcs
= 4 μm. Actually, in this embodiment, Wcs is 4 μ
It was set to m, and as a result of visual inspection of the display image, it was confirmed that good display quality could be realized.

The width of the auxiliary capacitance; Wcs is not limited to the above optimum value. As can be seen from FIG. 26, if the optimum value is Wcs ^opt , 0.7 Wcs ^opt ≤ Wcs ≤ 2Wcs
If set to ^opt , a sufficient practical effect can be obtained.

As can be seen from FIG. 26, in the region where Wcs is small, the fluctuation ratio of Cs is relatively large and the fluctuation of ΔVp is large. However, considering the aperture ratio, it is preferable that Wcs is small. .. Therefore, in this case ΔVp
It is desirable to reduce Lg in order to suppress the above.

Further, according to the detailed trials and evaluations conducted by the present inventors, Δ was obtained even when the scanning line, the gate electrode and the shield electrode were formed in different steps as in the seventh embodiment.
It was confirmed that the variation in Vp within the screen was reduced. This is because there is a correlation between the line widths of the scanning lines and the gate electrodes and the line widths of the electrodes of the auxiliary capacitors, even though they are formed in separate steps. This is because, in the case of this example, since each step was performed in the same apparatus, the patterning conditions peculiar to the apparatus are the same in each step of different steps, and the width of the variation in the line width is It is considered that the values fluctuated with each other so as to reduce the variation of ΔVp within the screen.

In FIG. 27, in order to more positively reduce the variation in the penetration voltage ΔVp within the screen,
It is a figure which shows the Example of the liquid crystal display device which provided the correction | amendment part 2701. The correction unit 2701 forms Cgs for correction by overlapping the pixel electrode 109 and the scanning line 103. In the liquid crystal display device of this embodiment, not only the variations in the line widths of the scanning lines and the shield electrode serving as the electrode of the auxiliary capacitance are offset, but also the punch-through voltage ΔVp due to the variations in the line width of the pixel electrode 109 is offset. We have confirmed that we can.

However, since the correction section 2701 functions as Cgs, it is desirable to set the capacitance value to the extent that the display characteristics are not deteriorated. That is, it is desirable to make the size as small as possible in the process so that the above-mentioned correction effect can be realized.

When the shield electrode is used as the black matrix on the signal line side, it is necessary to prevent the display defect due to the disclination of the liquid crystal from being visually recognized on the screen. It is said that this disclination is generally caused by an electric field in the lateral direction with respect to the liquid crystal layer, and occurs in a line shape at the end of the pixel electrode. The occurrence of this disclination also depends on the orientation direction such as rubbing. Therefore, for example, in the case of the liquid crystal display device of the fifth embodiment, since the rubbing alignment treatment is performed in an oblique direction for use for OA or the like,
The occurrence of disclination is different between the left end and the right end of the pixel electrode. As a result, when actually displayed, it seems that disclination is conspicuous at the left end of the pixel electrode, while it hardly appears at the right end. Therefore, in such a case, if the overlap between the shield electrode and the pixel electrode is set so that the left end portion of the pixel electrode overlaps the right end portion more than the right end portion, the shield electrode conceals a display defect due to disclination. be able to. In this way, it is desirable to conceal a display defect due to disclination.

Further, since the disclination may be generated in such a manner that it is caught in a step portion such as an alignment film or a passivation film which is in contact with the liquid crystal layer, in order to avoid this, a protective film is formed on the pixel electrode. It is preferable that a step such as a (passivation film) is not formed so that a sufficient distance is provided outside the pixel electrode, and the step is preferably separated by about 10 μm. Further, it is desirable that the end portion of such a protective film is processed into a gentle taper shape so that the step is not steep.

Further, in the above embodiments, a metal material such as Mo-Ta or Al is used as the material of the shield electrode, but the material is not limited to this. When this shield electrode also serves as an electrode of the auxiliary capacitance, the potential fluctuation based on the time constant becomes large when the resistance value is high, so if the material with high process conductivity among the materials with high conductivity and high resistance is used, Other materials can also be used.

Besides, the pattern, layer structure, material, etc. of the TFT array are not limited to those in the above-mentioned embodiments, and may be appropriately changed according to the specifications of each liquid crystal display device without departing from the scope of the present invention. It goes without saying that it is possible.

[0135]

As described in detail above, according to the present invention,
It is possible to provide a liquid crystal display device that reduces a parasitic capacitance between a pixel electrode and a scanning line or a signal line adjacent to the pixel electrode to eliminate unevenness in brightness and crosstalk of a display image and realize a good image display. .

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a liquid crystal display device according to a first embodiment.

FIG. 2 is a sectional view of the liquid crystal display device of the first embodiment.

FIG. 3 is a diagram showing a configuration of a liquid crystal display device according to a second embodiment.

FIG. 4 is a sectional view of a liquid crystal display device according to a second embodiment.

FIG. 5 is a diagram showing a configuration of a liquid crystal display device of a third embodiment.

FIG. 6 is a sectional view of a liquid crystal display device according to a third embodiment.

FIG. 7 is a diagram showing a configuration of a liquid crystal display device of a fourth embodiment.

FIG. 8 is a sectional view of a liquid crystal display device according to a fourth embodiment.

FIG. 9 is a diagram showing a configuration of a liquid crystal display device of a fifth embodiment.

FIG. 10 is a sectional view of a liquid crystal display device according to a fifth embodiment.

FIG. 11 is a diagram showing a configuration of a liquid crystal display device of a sixth embodiment.

FIG. 12 is a sectional view of a liquid crystal display device according to a sixth embodiment.

FIG. 13 is a diagram showing a configuration of a liquid crystal display device of a seventh embodiment.

FIG. 14 is a sectional view of a liquid crystal display device according to a seventh embodiment.

FIG. 15 is a diagram showing a configuration of a liquid crystal display device of a seventh embodiment.

FIG. 16 is a sectional view showing a layer structure of a liquid crystal display device of a ninth embodiment.

FIG. 17 is a diagram showing a process of forming a through hole of the liquid crystal display device of the ninth embodiment.

FIG. 18 is a diagram showing a first modification of the liquid crystal display device of the ninth embodiment.

FIG. 19 is a diagram showing a second modification of the liquid crystal display device of the ninth embodiment.

FIG. 20 is a diagram showing a third modification of the liquid crystal display device of the ninth embodiment.

FIG. 21 is a diagram showing a fourth modification of the liquid crystal display device of the ninth embodiment.

FIG. 22 is a diagram showing a fifth modification of the liquid crystal display device of the ninth embodiment.

FIG. 23 is a cross-sectional view showing the layer structure of the liquid crystal display device of the tenth embodiment.

FIG. 24 is a sectional view showing a modification of the liquid crystal display device of the tenth embodiment.

FIG. 25 is a diagram for explaining the punch-through voltage using mathematical expressions.

FIG. 26 is a diagram showing the correlation between the punch-through voltage ΔVp and the width Wcs of the auxiliary capacitance.

FIG. 27 is a diagram showing an embodiment of a liquid crystal display device provided with a correction unit 2701.

FIG. 28 is a diagram showing a configuration of a conventional liquid crystal display device.

FIG. 29 is a diagram showing an electrically equivalent circuit of a conventional liquid crystal display device.

[Explanation of symbols]

101 ... Glass insulating substrate, 103 ... Scan line, 105 ... Signal line, 107 ... TFT, pixel electrode 109, gate insulating layer 111, shield electrode 113, TFT array substrate 11
5, auxiliary capacity 117

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Reference number within the agency FI Technical indication location H01L 29/784 (72) Inventor Makoto Shibusawa 8 Shinsita-cho, Isogo-ku, Yokohama-shi, Kanagawa Stock company Toshiba Corporation Inside the Yokohama office (72) Inventor Mitsushi Ikeda 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Stock company Toshiba Research Laboratories (72) Inventor Yoshiko Komukai Toshiba-cho, Ko-ku, Kawasaki-shi, Kanagawa Inside Toshiba Research Institute, Inc. (72) Inventor Hisaro Toeda, No. 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki City, Kanagawa Stock Company Toshiba Research Institute

Claims (1)

[Claims] 1. An array substrate having scan lines arranged in a row, signal lines arranged in a line intersecting with the scan lines, thin film transistor elements connected to the scan lines and the signal lines, and pixel electrodes connected to the thin film transistor elements. A counter substrate having a counter electrode facing it, and a liquid crystal layer sandwiched between the array substrate and the counter substrate, overlapping at least a part of a peripheral portion of the pixel electrode, and the scanning line. And a shield electrode having an electrostatic shielding property, which is disposed so as to overlap at least one of the signal lines, on the array substrate.