JP2001326322A - Intermediate structure to be mounted with semiconductor, and method of manufacturing semiconductor device - Google Patents

Intermediate structure to be mounted with semiconductor, and method of manufacturing semiconductor device

Info

Publication number
JP2001326322A
JP2001326322A JP2000145603A JP2000145603A JP2001326322A JP 2001326322 A JP2001326322 A JP 2001326322A JP 2000145603 A JP2000145603 A JP 2000145603A JP 2000145603 A JP2000145603 A JP 2000145603A JP 2001326322 A JP2001326322 A JP 2001326322A
Authority
JP
Japan
Prior art keywords
circuit board
semiconductor
semiconductor element
plate
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000145603A
Other languages
Japanese (ja)
Other versions
JP3300698B2 (en
Inventor
Yoshitaka Sunakawa
義隆 砂川
Yoshitake Hayashi
林  祥剛
Hideo Kanzawa
英雄 神澤
Tsukasa Shiraishi
司 白石
Sei Yuhaku
祐伯  聖
Kazuyoshi Amami
和由 天見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2000145603A priority Critical patent/JP3300698B2/en
Publication of JP2001326322A publication Critical patent/JP2001326322A/en
Application granted granted Critical
Publication of JP3300698B2 publication Critical patent/JP3300698B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To reform the warp of a circuit board and materialize stable connection reliability, by interposing a circuit board between plates A and B having openings corresponding to the positions where semiconductor elements A and B are to be mounted on both sides of the faces A and B of the circuit board, in a semiconductor mounting method which is used in the case of flip-chip- mounting semiconductor elements on both the face A and the face B of the circuit board. SOLUTION: Since the warp of a circuit board where semiconductor elements A and B are mounted is suppressed by providing an integrated structure of plate where a circuit board is interposed between the plates A1 and B2 having openings in the positions where the semiconductor elements A and B are to be mounted at the face A and the face B of the circuit board 3.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、回路基板の両面上
に複数個の半導体素子をフリップチップ実装する際の半
導体実装対象中間構造体と半導体装置の製造方法に関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an intermediate structure to be mounted on a semiconductor and a method of manufacturing a semiconductor device when a plurality of semiconductor elements are flip-chip mounted on both sides of a circuit board.

【0002】[0002]

【従来の技術】半導体プロセスの微細化技術の進化に伴
いメモリー素子の高容量化が進んでいる。このような背
景のもと記憶媒体として従来から使われている磁気記録
や光記録に替わり、一部フラッシュメモリーのような個
体メモリーが使われている。
2. Description of the Related Art With the advance of the miniaturization technology of semiconductor processes, the capacity of memory devices has been increased. Against this background, solid-state memories such as flash memories have been used in place of magnetic recording and optical recording conventionally used as storage media.

【0003】これらの応用例としてICカードやデジタ
ルカメラなどのメモリーカードが有り、さらにはセキュ
リティ機能を持ったSD(Secure Digita
l)カードなどが広まろうとしている。このようなメモ
リーカードは、音楽情報などを記録するため今後、より
一層大容量化が要望されている。
[0003] Examples of these applications include memory cards such as IC cards and digital cameras, and SD (Secure Digital) having a security function.
l) Cards are spreading. Such memory cards are required to have even larger capacities in order to record music information and the like.

【0004】メモリーカードは小型で薄いため、この中
に高容量メモリーを収容するためには、半導体の実装も
3次元実装や両面フリップチップ実装のような形態が必
要とされる。
Since a memory card is small and thin, in order to accommodate a high-capacity memory therein, a semiconductor must be mounted in a form such as three-dimensional mounting or double-sided flip-chip mounting.

【0005】以下、前記両面フリップチップ実装技術を
用いて実装を行った場合の一例(例えば、特願平10−
324213号出願に記載されたもの)について図面を
参照しその構成を説明する。
Hereinafter, an example of mounting using the double-sided flip-chip mounting technology (for example, Japanese Patent Application No.
324213) will be described with reference to the drawings.

【0006】図17は、従来の半導体実装治具を用い
て、半導体素子を回路基板の両面上にフリップチップ実
装した構造体の構成とその製造手順を示す断面図であ
り、図18は、従来の2段突起電極を用いて回路基板の
両面にフリップチップ実装を行う説明用の断面図であ
り、図19は、回路基板の片面上にフリップチップ実装
する場合に発生する基板変形を示した模式図である。
尚、図17〜図19において、同一部分には同一符号を
付している。
FIG. 17 is a sectional view showing a structure of a structure in which a semiconductor element is flip-chip mounted on both sides of a circuit board using a conventional semiconductor mounting jig and a manufacturing procedure thereof. FIG. FIG. 19 is a cross-sectional view for explaining flip-chip mounting on both sides of a circuit board using the two-step protruding electrodes of FIG. 19; and FIG. 19 is a schematic diagram showing substrate deformation that occurs when flip-chip mounting is performed on one side of the circuit board. FIG.
17 to 19, the same parts are denoted by the same reference numerals.

【0007】図17に示すように、回路基板A面4およ
び回路基板B面7の表面に予め実装された高さおよび大
きさが全て異なった形状からなる複数の面実装部品と相
対した位置に、溝加工部18を半導体素子A5の実装を
行う位置に開口部6を設けたプレートA1およびプレー
トB2とを2面構成されており、前記プレートA1とプ
レートB2の間に前記回路基板を配置した後、取り付け
ビス19によって固定することにより、回路基板全体の
反りを矯正することができる。尚、規制ピン20は、プ
レートA1およびB2あるいは回路基板とを規制するも
のである。
[0007] As shown in FIG. 17, at a position opposed to a plurality of surface mount components which are pre-mounted on the surfaces of the circuit board A surface 4 and the circuit board B surface 7 and have different heights and sizes. A plate A1 and a plate B2 having an opening 6 at a position where the grooved portion 18 is to be mounted with the semiconductor element A5 have two surfaces, and the circuit board is disposed between the plate A1 and the plate B2. Thereafter, by fixing with the mounting screws 19, the warpage of the entire circuit board can be corrected. The restriction pins 20 restrict the plates A1 and B2 or the circuit board.

【0008】次に、その製造手順を説明する。プレート
B2の上に回路基板B面7を下方向に配置して、続いて
回路基板A面4の上にプレートA1を配置して取り付け
ビス19で固定させ一体構造とした後、まず回路基板A
面4に半導体素子A5を実装し、一体構造としたプレー
トA1・B2を反転させた状態で今度は、回路基板B面
7の半導体素子B8をフリップチップ実装を行うことに
より、回路基板A面4およびB面7の両面に対して、フ
リップチップ実装が可能となる方法を用いている。
Next, the manufacturing procedure will be described. After the circuit board B surface 7 is arranged on the plate B2 in the downward direction, the plate A1 is arranged on the circuit board A surface 4 and fixed with the mounting screws 19 to form an integrated structure.
The semiconductor element A5 is mounted on the surface 4 and the semiconductor elements B8 on the circuit board B surface 7 are flip-chip mounted in a state where the plates A1 and B2 formed as an integral structure are inverted. And a method that enables flip-chip mounting on both sides of the B side 7.

【0009】[0009]

【発明が解決しようとする課題】しかしながら、図17
で示した従来の構成の様に、回路基板A面4およびB面
7への半導体素子の実装位置が重ならない場合や回路基
板自体の剛性が高く熱膨張係数が小さい(半導体素子に
近い)場合などは特に問題はないと思われるが、例え
ば、メモリーカード用のような形態で半導体素子を両面
実装する場合には、図18に示すように回路基板A面4
には、13×10×0.3mmの半導体素子A5が2
個、回路基板B面7には、6×6×0.3mmの半導体
素子B8が2個それぞれ重なるように両面にフリップチ
ップ実装を行う必要がある。
However, FIG.
When the mounting positions of the semiconductor elements on the circuit board A surface 4 and the B surface 7 do not overlap or when the rigidity of the circuit board itself is high and the thermal expansion coefficient is small (close to the semiconductor device) as in the conventional configuration shown in FIG. Although it is considered that there is no particular problem, for example, when a semiconductor element is mounted on both sides in a form like a memory card, as shown in FIG.
Has two semiconductor elements A5 of 13 × 10 × 0.3 mm.
It is necessary to perform flip-chip mounting on both sides of the circuit board B surface 7 such that two 6 × 6 × 0.3 mm semiconductor elements B8 overlap each other.

【0010】また、この時の回路基板は多層基板で厚み
が0.35mmであり、外装ケース(図示せず)に収め
られるカードの厚みは約2mmである。このように、実
装領域が極めて狭くかつ、薄いサイズで規定された実装
が必要となるため、従来の実装治具や製造方法では、前
記構造体を構成するには困難を要す。
At this time, the circuit board is a multi-layer board having a thickness of 0.35 mm, and a card housed in an outer case (not shown) has a thickness of about 2 mm. As described above, since the mounting area is extremely narrow and the mounting is required to be defined in a thin size, it is difficult to configure the structure with the conventional mounting jig and manufacturing method.

【0011】すなわち、従来の実装治具や半導体装置の
製造方法で、半導体素子を両面実装する場合、実装領域
が極めて狭くかつ薄いサイズで実装することが困難であ
るという課題がある。
That is, when a semiconductor element is mounted on both sides by a conventional method of manufacturing a mounting jig or a semiconductor device, there is a problem that it is difficult to mount the semiconductor element in a very narrow and thin size.

【0012】また、図19に示すように回路基板A面4
の片面側だけに半導体素子A5を実装し、アンダーフィ
ル樹脂13を熱硬化させた場合、半導体素子A5と回路
基板全体との熱膨張係数差により回路基板と半導体素子
に反りが発生する。
Further, as shown in FIG.
When the semiconductor element A5 is mounted on only one side of the substrate and the underfill resin 13 is thermally cured, the circuit board and the semiconductor element are warped due to a difference in thermal expansion coefficient between the semiconductor element A5 and the entire circuit board.

【0013】例えば、半導体素子が10×10×0.4
mmで回路基板が0.4mm厚の組み合わせで封止材を
150℃で硬化した場合には、約35μmの反りが発生
する。続いて回路基板B面7に半導体素子B8を実装す
る際、半導体素子A5の実装によって生じた回路基板の
反りによって実装品質および信頼性が著しく悪化する。
For example, if the semiconductor element is 10 × 10 × 0.4
When the encapsulant is cured at 150 ° C. in a combination of 0.4 mm and a circuit board thickness of 0.4 mm, warpage of about 35 μm occurs. Subsequently, when the semiconductor element B8 is mounted on the circuit board B surface 7, the mounting quality and the reliability are significantly deteriorated due to the warpage of the circuit board caused by the mounting of the semiconductor element A5.

【0014】すなわち、従来の実装治具や半導体装置の
製造方法で、半導体素子を実装すると、回路基板にそり
が発生し、実装品質および信頼性が著しく悪化するとう
いう課題がある。
That is, when a semiconductor element is mounted by a conventional method of manufacturing a mounting jig or a semiconductor device, there is a problem that a warpage occurs in a circuit board and mounting quality and reliability are significantly deteriorated.

【0015】本発明は、このような従来の半導体素子実
装方法が有する課題を考慮し、薄板で剛性が低い回路基
板上へ半導体素子を両面重なるように配して、両面ベア
ーチップ実装ができる半導体実装対象中間構造体と半導
体装置の製造方法を提供することを目的とするものであ
る。
In view of the above-mentioned problems of the conventional semiconductor element mounting method, the present invention provides a semiconductor which can be mounted on a thin, low-rigidity circuit board so that both sides of the semiconductor element are superimposed on each other, and can be mounted on a double-sided bare chip. It is an object of the present invention to provide a mounting target intermediate structure and a method of manufacturing a semiconductor device.

【0016】[0016]

【課題を解決するための手段】上述した課題を解決する
ために、第1の本発明(請求項1に対応)は、回路基板
と、前記回路基板の第1の面に第1の半導体素子を実装
する位置に開口部を有する第1のプレートと、前記回路
基板の第2の面に第2の半導体素子を実装する位置に開
口部を有する第2のプレートとを備え、前記回路基板の
前記第1の面に前記第1のプレートが、前記第2の面に
前記第2のプレートがそれぞれ当接された半導体実装対
象中間構造体であって、前記第1のプレートの各フレー
ムとそれらに対向する前記第2のプレートの各フレーム
とは少なくとも一部が重なっていることを特徴とする半
導体実装対象中間構造体である。
In order to solve the above-mentioned problems, a first invention (corresponding to claim 1) provides a circuit board and a first semiconductor element on a first surface of the circuit board. A first plate having an opening at a position where the second substrate is mounted, and a second plate having an opening at a position where a second semiconductor element is mounted on the second surface of the circuit board. A semiconductor mounting target intermediate structure in which the first plate is in contact with the first surface and the second plate is in contact with the second surface, and each frame of the first plate is The semiconductor mounting target intermediate structure is characterized in that at least a part of each of the frames of the second plate opposing to the above is overlapped.

【0017】また、第2の本発明(請求項2に対応)
は、前記回路基板の前記第2の面の開口部に対応する位
置に突起部を有し、前記突起部が前記回路基板の第2の
面に当接する第3のプレートを備え、前記第3のプレー
トは、前記第1の半導体を実装する際に用いられること
を特徴とする第1の本発明に記載の半導体実装対象中間
構造体である。
Further, the second invention (corresponding to claim 2)
Comprises a third plate having a projection at a position corresponding to the opening on the second surface of the circuit board, wherein the projection is in contact with the second surface of the circuit board; Is an intermediate structure to be mounted on a semiconductor according to the first aspect of the present invention, which is used when mounting the first semiconductor.

【0018】また、第3の本発明(請求項3に対応)
は、 前記回路基板の前記第1の面の開口部に対応する
位置に突起部を有し、前記突起部には、前記第1の半導
体が実装されている位置に座ぐり構造が設けられてお
り、前記突起部が前記回路基板の第1の面に当接する第
4のプレートを備え、前記第4のプレートは、前記第2
の半導体を実装する際に用いられることを特徴とする第
2の本発明に記載の半導体実装対象中間構造体である。
Further, the third invention (corresponding to claim 3)
Has a projection at a position corresponding to the opening on the first surface of the circuit board, and the projection has a spot facing structure at a position where the first semiconductor is mounted. And a fourth plate in which the protrusion contacts the first surface of the circuit board, wherein the fourth plate includes the second plate.
A semiconductor mounting target intermediate structure according to a second aspect of the present invention, which is used when mounting the semiconductor according to the first aspect of the invention.

【0019】また、第4の本発明(請求項4に対応)
は、前記座ぐり構造の深さは、前記回路基板表面から前
記第1の半導体素子の裏面までの高さ以上であることを
特徴とする第3の本発明に記載の半導体実装対象中間構
造体である。
The fourth invention (corresponding to claim 4)
Wherein the depth of the counterbore structure is equal to or greater than the height from the surface of the circuit board to the back surface of the first semiconductor element. It is.

【0020】また、第5の本発明(請求項5に対応)
は、回路基板の第1の面と第2の面にそれぞれ第1及び
第2の半導体素子をフリップチップ実装する半導体装置
の製造方法であって、前記回路基板の第1の面に前記第
1の半導体素子を実装する位置に開口部を有する第1の
プレートと、前記回路基板の第2の面に前記第2の半導
体素子を実装する位置に開口部を有する第2のプレート
とを、ぞれぞれ前記回路基板の前記第1の面と前記第2
の面に当接して半導体実装対象中間構造体を形成し、前
記半導体実装対象中間構造体の前記第1のプレートの各
フレームとそれらに対向する前記第2のプレートの各フ
レームとは少なくとも一部が重なっているものであり、
前記回路基板の第1の面に前記第1の半導体素子をフェ
ースダウンにて搭載して、アンダーフィル樹脂を硬化さ
せてフリップチップ実装し、前記半導体実装対象中間構
造体を反転させた後、前記回路基板の第2の面に前記第
2の半導体素子をフェースダウンにて搭載して、アンダ
ーフィル樹脂を硬化させてフリップ実装することを特徴
とする半導体装置の製造方法である。
Further, the fifth invention (corresponding to claim 5)
Is a method for manufacturing a semiconductor device in which first and second semiconductor elements are flip-chip mounted on a first surface and a second surface of a circuit board, respectively, wherein the first surface is mounted on the first surface of the circuit board. A first plate having an opening at a position where the semiconductor element is mounted, and a second plate having an opening at a position where the second semiconductor element is mounted on the second surface of the circuit board. The first surface of the circuit board and the second surface
To form a semiconductor mounting target intermediate structure, and each frame of the first plate of the semiconductor mounting target intermediate structure and at least a part of each frame of the second plate facing the semiconductor mounting target intermediate structure. Are overlapping,
After mounting the first semiconductor element face-down on the first surface of the circuit board, curing the underfill resin and performing flip-chip mounting, and inverting the semiconductor mounting target intermediate structure, A method of manufacturing a semiconductor device, comprising mounting the second semiconductor element face down on a second surface of a circuit board, curing the underfill resin, and performing flip mounting.

【0021】また、第6の本発明(請求項6に対応)
は、前記第1の半導体を搭載する際、前記回路基板の前
記第2の面の開口部に対応する位置に突起部を有する第
3のプレートを前記回路基板の第2の面に当接させるこ
とを特徴とする第5の本発明に記載の半導体装置の製造
方法である。
The sixth invention (corresponding to claim 6)
When mounting the first semiconductor, a third plate having a protrusion at a position corresponding to an opening of the second surface of the circuit board is brought into contact with the second surface of the circuit board A fifth aspect of the present invention is the method for manufacturing a semiconductor device according to the present invention.

【0022】また、第7の本発明(請求項7に対応)
は、前記第2の半導体素子を搭載する際、前記第1の半
導体素子が実装された位置に座ぐり構造を設けた突起を
前記回路基板の前記第1の面の開口部に対応する位置に
有する第4のプレートを前記回路基板の第1の面に当接
させることを特徴とする第5または6の本発明に記載の
半導体装置の製造方法である。
A seventh aspect of the present invention (corresponding to claim 7)
When mounting the second semiconductor element, a projection provided with a spot facing structure at a position where the first semiconductor element is mounted is positioned at a position corresponding to an opening of the first surface of the circuit board. The method according to the fifth or sixth aspect of the present invention, wherein the fourth plate has a contact with the first surface of the circuit board.

【0023】また、第8の本発明(請求項8に対応)
は、回路基板の第1の面と第2の面の両面にそれぞれ半
導体素子をフリップチップ実装する半導体装置の製造方
法であって、前記両面に搭載する半導体素子のサイズが
異なっており、前記両面に前記半導体素子を搭載する位
置が重なっている場合、前記回路基板の第1の面にサイ
ズの小さい方の前記半導体素子をフェースダウンにて搭
載して、アンダーフィル樹脂を硬化させてフリップチッ
プ実装し、前記回路基板を反転させた後、前記回路基板
の第2の面にサイズの大きい方の前記半導体素子をフェ
ースダウンにて搭載して、アンダーフィル樹脂を硬化さ
せてフリップチップ実装することを特徴とする半導体装
置の製造方法である。
The eighth invention (corresponding to claim 8)
Is a method of manufacturing a semiconductor device in which semiconductor elements are flip-chip mounted on both surfaces of a first surface and a second surface of a circuit board, respectively, wherein sizes of the semiconductor elements mounted on the two surfaces are different. When the positions where the semiconductor elements are mounted overlap each other, the semiconductor element having the smaller size is mounted face down on the first surface of the circuit board, and the underfill resin is cured and flip-chip mounted. Then, after flipping the circuit board, mounting the larger semiconductor element face down on the second surface of the circuit board, curing the underfill resin, and performing flip chip mounting. This is a method for manufacturing a semiconductor device.

【0024】また、第9の本発明(請求項9に対応)
は、回路基板の第1の面と第2の面にそれぞれ第1及び
第2の半導体素子をフリップチップ実装する半導体装置
の製造方法であって、前記回路基板の第1の面に前記第
1の半導体素子をフェースダウンにて搭載後、アンダー
フィル樹脂を硬化反応率98%以下で仮硬化させフリッ
プチップ実装し、前記回路基板の第2の面に前記第2の
半導体素子をフェースダウンにて搭載後、前記アンダー
フィル樹脂を完全硬化させてフリップチップ実装するこ
とを特徴とする半導体装置の製造方法である。
The ninth invention (corresponding to claim 9)
Is a method for manufacturing a semiconductor device in which first and second semiconductor elements are flip-chip mounted on a first surface and a second surface of a circuit board, respectively, wherein the first surface is mounted on the first surface of the circuit board. After mounting the semiconductor element face down, the underfill resin is temporarily cured at a curing reaction rate of 98% or less and flip-chip mounted, and the second semiconductor element is face down on the second surface of the circuit board. After the mounting, the underfill resin is completely cured and flip-chip mounted.

【0025】また、第10の本発明(請求項10に対
応)は、回路基板の第1の面と第2の面の両面にそれぞ
れ第1及び第2の半導体素子をフリップチップ実装する
半導体装置の製造方法であって、前記回路基板の第1の
面に前記第1の半導体素子をフェースダウンにて搭載
後、アンダーフィル樹脂を硬化反応率98%以下で仮硬
化させフリップチップ実装し、前記回路基板の第2の面
に前記第2の半導体素子をフェースダウンにて搭載後、
アンダーフィル樹脂を硬化反応率98%以下で仮硬化さ
せフリップチップ実装し、前記両面のアンダーフィル樹
脂を完全硬化させることを特徴とする半導体装置の製造
方法である。
According to a tenth aspect of the present invention, there is provided a semiconductor device in which first and second semiconductor elements are flip-chip mounted on both the first and second surfaces of a circuit board, respectively. The first semiconductor element is mounted face-down on the first surface of the circuit board, and the underfill resin is provisionally cured at a curing reaction rate of 98% or less and flip-chip mounted. After mounting the second semiconductor element face down on the second surface of the circuit board,
A method for manufacturing a semiconductor device, comprising temporarily curing an underfill resin at a curing reaction rate of 98% or less, mounting the flip-chip, and completely curing the underfill resin on both surfaces.

【0026】また、第11の本発明(請求項11に対
応)は、前記回路基板の第1の面と第2の面に用いられ
る前記アンダーフィル樹脂材料の熱膨張係数およびヤン
グ率が同等であることを特徴とする第9または10の本
発明に記載の半導体装置の製造方法である。
According to an eleventh aspect of the present invention (corresponding to claim 11), the underfill resin material used for the first surface and the second surface of the circuit board has the same thermal expansion coefficient and Young's modulus. A ninth or tenth aspect of the present invention is the method for manufacturing a semiconductor device according to the present invention.

【0027】また、第12の本発明(請求項12に対
応)は、回路基板の第1の面と第2の面にそれぞれ第1
及び第2の半導体素子をフリップチップ実装する半導体
装置の製造方法であって、前記回路基板の第1の面に前
記第1の半導体素子を実装する位置に開口部を有する第
1のプレートと、前記回路基板の第2の面に前記第2の
半導体素子を実装する位置に開口部を有する第2のプレ
ートとを、ぞれぞれ前記回路基板の前記第1の面と前記
第2の面に当接して半導体実装対象中間構造体を形成
し、前記半導体実装対象中間構造体の前記第1のプレー
トの各フレームとそれらに対向する前記第2のプレート
の各フレームとは少なくとも一部が重なっているもので
あり、前記回路基板の第1の面に前記第1の半導体素子
をフェースダウンにて搭載して電気的接続を施し、前記
半導体実装対象中間構造体を反転させた後、前記回路基
板の第2の面に前記第2の半導体素子をフェースダウン
にて搭載して電気的接続を施し、前記第1及び第2の半
導体素子と、前記回路基板との隙間にアンダーフィル樹
脂を充填後加熱硬化することを特徴とする半導体装置の
製造方法である。
According to a twelfth aspect of the present invention (corresponding to claim 12), the first surface and the second surface of the circuit board are respectively provided with the first and second surfaces.
And a method of manufacturing a semiconductor device in which a second semiconductor element is flip-chip mounted, comprising: a first plate having an opening at a position where the first semiconductor element is mounted on a first surface of the circuit board; A second plate having an opening at a position where the second semiconductor element is mounted on a second surface of the circuit board; and a first plate and a second surface of the circuit board, respectively. To form an intermediate structure to be mounted on a semiconductor, and each frame of the first plate of the intermediate structure to be mounted on the semiconductor and at least a part of each frame of the second plate opposed thereto are overlapped. The first semiconductor element is mounted face-down on the first surface of the circuit board to make electrical connection, and after the semiconductor mounting target intermediate structure is inverted, the circuit is mounted. The second surface of the substrate The second semiconductor element is mounted face-down to make electrical connection, and a gap between the first and second semiconductor elements and the circuit board is filled with an underfill resin and then heated and cured. 6 shows a method for manufacturing a semiconductor device.

【0028】また、第13の本発明(請求項13に対
応)は、前記第1の半導体に電気的接続を施す際、前記
回路基板の前記第2の面の開口部に対応する位置に突起
部を有する第3のプレートを前記回路基板の第2の面に
当接させることを特徴とする第12の本発明に記載の半
導体装置の製造方法である。
According to a thirteenth aspect of the present invention, when an electrical connection is made to the first semiconductor, a projection is provided at a position corresponding to the opening on the second surface of the circuit board. A twelfth method of manufacturing a semiconductor device according to the present invention, wherein a third plate having a portion is brought into contact with the second surface of the circuit board.

【0029】また、第14の本発明(請求項14に対
応)は、前記第2の半導体素子に電気的接続を施す際、
前記第1の半導体素子が実装された位置に座ぐり構造を
設けた突起を前記回路基板の前記第1の面の開口部に対
応する位置に有する第4のプレートを前記回路基板の第
1の面に当接させることを特徴とする第12または13
の本発明に記載の半導体装置の製造方法である。
According to a fourteenth aspect of the present invention (corresponding to claim 14), when an electrical connection is made to the second semiconductor element,
A fourth plate having a projection provided with a spot facing structure at a position where the first semiconductor element is mounted at a position corresponding to an opening of the first surface of the circuit board; The twelfth or thirteenth aspect, wherein the twelfth or thirteenth aspect is brought into contact with a surface
This is a method for manufacturing a semiconductor device according to the present invention.

【0030】また、第15の本発明(請求項15に対
応)は、第5〜14の本発明のいずれか記載の半導体装
置の製造方法において、前記半導体素子と前記回路基板
間の電気的な接続は、導電性接着剤を介して接続される
構造であり、前記半導体素子と前記回路基板間に絶縁樹
脂を介在させて、前記導電性接着剤と同時に加熱硬化し
たことを特徴とする半導体装置の製造方法である。
According to a fifteenth invention (corresponding to claim 15), in the method of manufacturing a semiconductor device according to any one of the fifth to fourteenth inventions, an electrical connection between the semiconductor element and the circuit board is provided. The semiconductor device is characterized in that the connection is a structure connected via a conductive adhesive, and an insulating resin is interposed between the semiconductor element and the circuit board to be heated and cured simultaneously with the conductive adhesive. It is a manufacturing method of.

【0031】[0031]

【発明の実施の形態】以下に、本発明の実施の形態を図
面を参照して説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0032】(第1の実施の形態)まず、本発明の第1
の実施の形態を図面を参照して説明する。
(First Embodiment) First, the first embodiment of the present invention will be described.
An embodiment will be described with reference to the drawings.

【0033】図1は、本発明の第1の実施の形態におけ
る半導体実装治具を用いて半導体素子を回路基板の両面
にフリップチップ実装した場合の構成を示す断面図であ
り、図2は、その斜視図である。
FIG. 1 is a cross-sectional view showing a configuration in which a semiconductor element is flip-chip mounted on both sides of a circuit board using a semiconductor mounting jig according to the first embodiment of the present invention, and FIG. It is the perspective view.

【0034】図1および図2において、プレートA1お
よびプレートB2は、本実施の形態における半導体実装
治具であり、回路基板3のA面4に半導体素子A5を実
装する位置には、前記半導体素子A5と当接しないよう
に開口部6を設けたプレートA1が構成されており、同
じく回路基板3のB面7に半導体素子B8を実装する位
置には、半導体素子B8と当接しない開口部6を設けた
プレートB2が構成されている。
1 and 2, a plate A1 and a plate B2 are semiconductor mounting jigs in the present embodiment, and the semiconductor element A5 is mounted on the A surface 4 of the circuit board 3 at the position where the semiconductor element A5 is mounted. A plate A1 provided with an opening 6 so as not to come into contact with A5 is formed. Similarly, at a position where the semiconductor element B8 is mounted on the B surface 7 of the circuit board 3, an opening 6 not coming into contact with the semiconductor element B8 is provided. Is provided on the plate B2.

【0035】プレートA1の各フレームとそれらに対向
するプレートB2の各フレームとは少なくとも一部が重
なっている。
Each frame of the plate A1 and each frame of the plate B2 opposed thereto at least partially overlap.

【0036】このように構成された、プレートA1とプ
レートB2との間に回路基板3を介在させることによ
り、両者のプレート荷重やビス締め等の固定手段にて、
回路基板3全体の反りと半導体素子A5および半導体素
子B8がフリップチップ実装される部分の局部的な反り
を抑制することができる。
By thus interposing the circuit board 3 between the plate A1 and the plate B2, the plate A1 and the plate B2 can be fixed by a fixing means such as plate load or screw fastening.
The warpage of the entire circuit board 3 and the local warpage of the portion where the semiconductor elements A5 and B8 are flip-chip mounted can be suppressed.

【0037】また、プレートA1およびプレートB2
は、複数の開口部を構成した一体構造とすることで、多
数個の半導体素子をフリップチップ実装することが可能
である。
Further, plate A1 and plate B2
By using an integrated structure having a plurality of openings, a large number of semiconductor elements can be flip-chip mounted.

【0038】図3は、本発明の第1の実施の形態におけ
る半導体実装治具の構成において、異なる開口部の形状
を有したプレートを用いて、半導体素子を回路基板の両
面にフリップチップ実装した場合の構成を示す断面図で
ある。
FIG. 3 shows a configuration of a semiconductor mounting jig according to the first embodiment of the present invention, in which semiconductor elements are flip-chip mounted on both sides of a circuit board using plates having different opening shapes. It is sectional drawing which shows a structure in the case.

【0039】図3に示すように、本実施の形態において
は、回路基板3のA面4およびB面7にサイズの異なる
半導体素子A5または半導体素子B8の実装を行う場
合、例えば回路基板A面4にサイズの小さい半導体素子
A5を実装し、回路基板B面7に大きいサイズの半導体
素子B8を実装する場合は、プレートA1の開口部6の
形状をプレートB2より狭くしかつ、半導体素子B8が
実装される接合部9の裏面aをプレートA1で支持す
る。この場合も、プレートA1の各フレームとそれらに
対向するプレートB2の各フレームとは少なくとも一部
が重なっている。
As shown in FIG. 3, in this embodiment, when the semiconductor elements A5 or B8 having different sizes are mounted on the A surface 4 and the B surface 7 of the circuit board 3, for example, In the case where the small-sized semiconductor element A5 is mounted on the circuit board 4 and the large-sized semiconductor element B8 is mounted on the circuit board B surface 7, the shape of the opening 6 of the plate A1 is made narrower than the plate B2 and the semiconductor element B8 is The back surface a of the joint 9 to be mounted is supported by the plate A1. Also in this case, at least a part of each frame of the plate A1 and each frame of the plate B2 facing them overlap.

【0040】従って、大きいサイズである半導体素子B
8の実装時の荷重をプレートA1で受けることができる
ため、回路基板3の変形を防止することが可能となり、
半導体素子B8の接続信頼性に対する影響を最小現に抑
制できる。
Therefore, the semiconductor element B having a large size
8, the load at the time of mounting can be received by the plate A1, so that the deformation of the circuit board 3 can be prevented,
The influence on the connection reliability of the semiconductor element B8 can be minimized.

【0041】図4は、本発明の第1の実施の形態におけ
る半導体実装治具の構成が突起構造を有するプレートを
用いて、半導体素子を回路基板の両面にフリップチップ
実装した場合の構成を示す断面図であり、図5はその斜
視図である。
FIG. 4 shows a configuration of the first embodiment of the present invention in which the semiconductor device is flip-chip mounted on both sides of a circuit board using a plate having a projection structure. FIG. 5 is a sectional view, and FIG. 5 is a perspective view thereof.

【0042】図4および図5に示すように、プレートA
1とプレートB2との間に回路基板3を介在させ一体構
造とし、前記プレートB2の開口部6に現れる回路基板
B面7を突起構造を有したプレートC10で支持するこ
とにより、回路基板A面4に実装される半導体素子A5
の実装領域の反りがより平坦化されるとともに、剛性の
弱い回路基板を保持することができるため、実装時の荷
重等による回路基板のたわみや変形が防止できる。
As shown in FIG. 4 and FIG.
The circuit board 3 is interposed between the plate 1 and the plate B2 to form an integral structure, and the circuit board B surface 7 that appears in the opening 6 of the plate B2 is supported by a plate C10 having a protruding structure. Semiconductor device A5 mounted on 4
Since the warpage of the mounting area is further flattened and the circuit board having low rigidity can be held, it is possible to prevent the circuit board from being bent or deformed due to a load at the time of mounting.

【0043】尚、プレートC10の突起高さは、プレー
トA1またはプレートB2の厚みと同じであることが好
ましい。
The height of the projection of the plate C10 is preferably the same as the thickness of the plate A1 or the plate B2.

【0044】図6は、本発明の第1の実施の形態におけ
る半導体実装治具の構成が突起部に座ぐり構造を有する
構成を用いて、半導体素子を回路基板の両面にフリップ
チップ実装した場合の構成を示す断面図である。
FIG. 6 shows a case where a semiconductor device is flip-chip mounted on both sides of a circuit board by using a configuration in which a semiconductor mounting jig according to the first embodiment of the present invention has a counterbore structure on a projection. It is sectional drawing which shows a structure of.

【0045】図6に示すように、プレートC10の突起
部の構造が回路基板3の裏面に半導体素子が実装される
位置に座ぐり部11を構成したプレートD12を設ける
ことにより、回路基板A面4と回路基板B面7に実装さ
れる配置が異なった場合や、部分的に重なるような配置
の実装に対しても簡単に実装することができかつ、回路
基板3全体の反りも合わせて矯正することができる。
As shown in FIG. 6, by providing a plate D12 having a counterbore portion 11 at a position where a semiconductor element is mounted on the back surface of the circuit board 3, the protrusion of the plate C10 is provided. 4 and the circuit board B surface 7 can be easily mounted even if they are differently arranged or partially overlapped, and the entire circuit board 3 is also corrected for warpage. can do.

【0046】また、プレートD12の座ぐり構造の深さ
は、回路基板3の面から半導体素子の裏面までの高さ以
上を有することにより、予め実装された半導体素子のダ
メージを最小現に抑えることが可能である。
Further, the depth of the counterbore structure of the plate D12 is equal to or greater than the height from the surface of the circuit board 3 to the back surface of the semiconductor element, so that damage to the semiconductor element mounted in advance can be minimized. It is possible.

【0047】また、予め実装された半導体素子が封止完
了後の状態で強度を有している場合は、座ぐり深さは同
等の高さであることが好ましく、この場合は実装される
半導体素子の荷重をプレートD12と半導体素子とで受
けるため、さらに回路基板3の変形を防止でき平坦化す
ることが可能となる。
In the case where the previously mounted semiconductor element has strength after the sealing is completed, it is preferable that the counterbore depth is the same height. Since the load of the element is received by the plate D12 and the semiconductor element, the circuit board 3 can be further prevented from being deformed and can be flattened.

【0048】(第2の実施の形態)次に、本発明の第2
の実施の形態を図面を参照して説明する。上述した第1
の実施の形態と基本的に同様のものについては、同一符
号を付与し説明を省略する。
(Second Embodiment) Next, a second embodiment of the present invention will be described.
An embodiment will be described with reference to the drawings. The first mentioned above
Components that are basically the same as those of the first embodiment are given the same reference numerals, and description thereof is omitted.

【0049】図7は、本発明の第2の実施の形態におけ
る半導体実装治具を用いて、半導体素子を回路基板の両
面にフリップチップ実装する場合の構成および手順を示
す断面図である。
FIG. 7 is a cross-sectional view showing a configuration and a procedure when a semiconductor element is flip-chip mounted on both sides of a circuit board using a semiconductor mounting jig according to the second embodiment of the present invention.

【0050】図7に示すように、回路基板A面4に半導
体素子A5を実装する位置には、前記半導体素子A5と
当接しないように開口部6を設けたプレートA1が構成
されており、同じく回路基板B面7に半導体素子B8を
実装する位置には、半導体素子B8と当接しない開口部
6を設けたプレートB2が構成されている。
As shown in FIG. 7, at a position where the semiconductor element A5 is mounted on the surface 4 of the circuit board A, a plate A1 provided with an opening 6 so as not to contact the semiconductor element A5 is formed. Similarly, at a position where the semiconductor element B8 is mounted on the surface 7 of the circuit board B, a plate B2 provided with an opening 6 not in contact with the semiconductor element B8 is formed.

【0051】このように構成された、プレートA1とプ
レートB2との間に回路基板3を介在させ一体構造とし
た後、まず、回路基板A面4に半導体素子A5をフェー
スダウンにて搭載し、回路基板3と半導体素子との密着
強度と信頼性を高めるために、アンダーフィル樹脂13
を充填加熱硬化させてフリップチップ実装する。
After the circuit board 3 is interposed between the plate A1 and the plate B2 to form an integral structure, the semiconductor element A5 is first mounted on the circuit board A surface 4 face down. In order to increase the adhesion strength and reliability between the circuit board 3 and the semiconductor element, the underfill resin 13 is used.
And heat-cured to mount a flip chip.

【0052】次に、前記一体構造とした回路基板3を反
転させた後、半導体素子B8を同様の手段にてにフリッ
プチップ実装する。前述の製造方法を用いれば、回路基
板3の反りを治具で抑制した状態のまま連続して回路基
板3の両面に半導体素子を実装することがが可能とな
る。
Next, after the circuit board 3 having the integrated structure is inverted, the semiconductor element B8 is flip-chip mounted by the same means. If the above-described manufacturing method is used, it is possible to continuously mount the semiconductor elements on both surfaces of the circuit board 3 while keeping the warp of the circuit board 3 with a jig.

【0053】本実施の形態においては、プレートA1と
プレートB2の開口形状を同じ大きさで同一場所に設け
ているが、回路基板3の両面に実装される半導体素子の
形状が異なった場合においては、プレートA1とプレー
トB2の開口率が異なっていても問題はなく、大きいサ
イズの半導体素子A5または半導体素子B8を実装する
際に実装部を裏面のプレートで受ける構造でも良い。
In the present embodiment, the opening shapes of the plate A1 and the plate B2 are provided at the same size and at the same place. However, when the shapes of the semiconductor elements mounted on both sides of the circuit board 3 are different, There is no problem even if the aperture ratios of the plate A1 and the plate B2 are different, and a structure in which the mounting portion is received by the plate on the back surface when the large-sized semiconductor element A5 or the semiconductor element B8 is mounted may be used.

【0054】図8は、本発明の第2の実施の形態におけ
る半導体実装治具の構成として、突起構造を有するプレ
ートを用いて、回路基板の両面に半導体素子をフリップ
チップ実装する場合の構成を示す断面図である。
FIG. 8 shows a configuration of a semiconductor mounting jig according to a second embodiment of the present invention, in which a semiconductor element is flip-chip mounted on both sides of a circuit board using a plate having a projection structure. FIG.

【0055】図8に示すように、プレートA1とプレー
トB2との間に回路基板3を介在し、一体構造とした、
プレートB2の開口部6に突起構造を有するプレートC
10にて回路基板B面7を支持した後、回路基板A面4
に半導体素子A5をフェースダウンにて搭載し、アンダ
ーフィル樹脂13を充填後熱硬化させてフリップチップ
実装する。
As shown in FIG. 8, a circuit board 3 is interposed between a plate A1 and a plate B2 to form an integrated structure.
Plate C having a projection structure in opening 6 of plate B2
After supporting the circuit board B surface 7 at 10, the circuit board A surface 4
The semiconductor element A5 is mounted face down, filled with the underfill resin 13 and then thermally cured to be flip-chip mounted.

【0056】次に、前記一体構造とした回路基板3を反
転させた後、回路基板B面7に半導体素子B8を同様に
フリップチップ実装する。
Next, after the circuit board 3 having the integrated structure is turned over, the semiconductor element B8 is similarly flip-chip mounted on the circuit board B surface 7.

【0057】上述の実装方法を用いることにより、半導
体素子A5を実装する際には、回路基板3の裏面がプレ
ートC10で受けられているため、半導体素子A5の実
装荷重による変形が防止でき安定した実装が可能とな
る。
By using the above mounting method, when mounting the semiconductor element A5, since the back surface of the circuit board 3 is received by the plate C10, the deformation due to the mounting load of the semiconductor element A5 can be prevented, and the semiconductor element A5 can be stably mounted. Implementation becomes possible.

【0058】また、回路基板B面7へ半導体素子B8を
実装する際は、先に実装した半導体素子A5によって回
路基板3の剛性が得られる。
When the semiconductor element B8 is mounted on the surface 7 of the circuit board B, the rigidity of the circuit board 3 is obtained by the previously mounted semiconductor element A5.

【0059】図9は、本発明の第2の実施の形態におけ
る半導体実装治具の構成が突起構造であるプレートに、
さらに座ぐり構造を有するプレートを用いて、半導体素
子を回路基板の両面にフリップチップ実装した場合の構
成と手順を示す断面図である。
FIG. 9 shows a semiconductor mounting jig according to a second embodiment of the present invention in which a plate having a projection structure is provided.
FIG. 4 is a cross-sectional view showing a configuration and a procedure when a semiconductor element is flip-chip mounted on both sides of a circuit board using a plate having a spot facing structure.

【0060】図9に示すように、プレートA1とプレー
トB2との間に回路基板3を介在し、一体構造とした
後、プレートB2の開口部6に突起を有するプレートC
10にて回路基板B面7を支持する。
As shown in FIG. 9, after the circuit board 3 is interposed between the plate A1 and the plate B2 to form an integral structure, a plate C having a projection in the opening 6 of the plate B2 is formed.
At 10, the circuit board B surface 7 is supported.

【0061】そして、回路基板A面4に半導体素子A5
をフェースダウンにて搭載し、アンダーフィル樹脂13
を充填後熱硬化させてフリップチップ実装する。
The semiconductor element A5 is placed on the circuit board A surface 4.
Is mounted face down, underfill resin 13
After filling, heat curing is performed and flip chip mounting is performed.

【0062】次に、一体構造とした回路基板3を反転さ
せた後、半導体素子A5が実装された位置に座ぐり構造
を設けた突起を有するプレートD12にて、回路基板A
面4あるいは半導体素子A5もしくは両方を支持する。
Next, after the integrated circuit board 3 is turned over, the circuit board A is mounted on a plate D12 having a projection provided with a spot facing structure at a position where the semiconductor element A5 is mounted.
The surface 4 or the semiconductor element A5 or both are supported.

【0063】そして、回路基板B面7に半導体素子B8
を同様にフリップチップ実装する。
Then, the semiconductor element B8 is placed on the circuit board B surface 7.
Is similarly flip-chip mounted.

【0064】上述の製造方法によれば、半導体素子A5
および半導体素子B8を実装する際に、回路基板3の裏
面を治具で支持することができるため、半導体素子の実
装荷重等による変形が抑制できるため安定した接続状態
が得ることができる。
According to the above-described manufacturing method, the semiconductor device A5
When the semiconductor element B8 is mounted, the back surface of the circuit board 3 can be supported by a jig, so that deformation of the semiconductor element due to a mounting load or the like can be suppressed, and a stable connection state can be obtained.

【0065】(第3の実施の形態)次に、本発明の第3
の実施の形態を図面を参照して説明する。上述した第2
の実施の形態と基本的に同様のものについては、同一符
号を付与し説明を省略する。 図10は、本発明の第
3の実施の形態における、サイズの異なる半導体素子を
回路基板の両面にフリップチップ実装する場合の構成お
よび手順を示す断面図であり、図11は、その模式図で
ある。
(Third Embodiment) Next, a third embodiment of the present invention will be described.
An embodiment will be described with reference to the drawings. The second mentioned above
Components that are basically the same as those of the first embodiment are given the same reference numerals, and description thereof is omitted. FIG. 10 is a cross-sectional view showing a configuration and a procedure when flip-chip mounting semiconductor elements having different sizes on both surfaces of a circuit board according to the third embodiment of the present invention, and FIG. 11 is a schematic view thereof. is there.

【0066】図10に示すように、プレートC10で支
持させた、回路基板A面4にサイズの小さい半導体素子
A5をフェースダウンにて搭載し、アンダーフィル樹脂
13を充填後熱硬化させてフリップチップ実装する。
As shown in FIG. 10, a semiconductor element A5 having a small size is mounted face-down on the circuit board A surface 4 supported by the plate C10, filled with the underfill resin 13, and then thermally cured to form a flip chip. Implement.

【0067】次に、前記回路基板3を反転させた後、サ
イズの大きい半導体素子B8を同様にフリップチップ実
装することにより、図11に示すようにアンダーフィル
樹脂13が熱硬化される際に発生する、半導体素子と回
路基板の反りの相関は、半導体素子の形状にともなっ
た、湾曲した反りを示す傾向がある反面、最初に小さい
サイズの半導体素子A5を実装したWの周辺以外は、比
較的平坦な箇所が存在する。この平坦部に大きいサイズ
の半導体素子B8を実装させることにより、安定した接
続状態を維持することが可能である。
Next, after the circuit board 3 is turned over, a large-sized semiconductor element B8 is similarly flip-chip mounted, so that when the underfill resin 13 is thermally cured as shown in FIG. The correlation between the warpage of the semiconductor element and the circuit board tends to show a curved warp according to the shape of the semiconductor element. On the other hand, except for the periphery of W where the small-sized semiconductor element A5 is first mounted, the correlation is relatively high. There are flat parts. By mounting a large-sized semiconductor element B8 on this flat portion, a stable connection state can be maintained.

【0068】(第4の実施の形態)次に、本発明の第4
の実施の形態を図面を参照して説明する。上述した第3
の実施の形態と基本的に同様のものについては、同一符
号を付与し説明を省略する。
(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described.
An embodiment will be described with reference to the drawings. The third mentioned above
Components that are basically the same as those of the first embodiment are given the same reference numerals, and description thereof is omitted.

【0069】図12は、本発明の第4の実施の形態にお
ける、アンダーフィル樹脂13の硬化条件と樹脂の硬化
反応率の関係を示したグラフであり、図13は、硬化反
応率と実装された半導体素子反り量の関係を示したグラ
フである。
FIG. 12 is a graph showing the relationship between the curing conditions of the underfill resin 13 and the curing reaction rate of the resin in the fourth embodiment of the present invention. FIG. 4 is a graph showing the relationship between the amounts of warpage of the semiconductor elements.

【0070】図12に示す硬化条件は、縦軸に硬化反応
率を横軸に硬化時間を示すと例えば、温度条件を70
℃、90℃、110℃、130℃、150℃条件下にお
けるアンダーフィル樹脂13の硬化反応率は、硬化時間
30分経過後を比較すると70℃で約55%、90℃で
は約80%、110℃では約90%、130℃では約9
8%であり、150℃では100%の値を示す。このよ
うに低温領域である70℃と90℃では、アンダーフィ
ル樹脂13が完全硬化するまでに時間を要す。
The curing conditions shown in FIG. 12 are as follows. When the ordinate indicates the curing reaction rate and the abscissa indicates the curing time, for example, the temperature condition is 70
The curing reaction rate of the underfill resin 13 under the conditions of 90 ° C., 90 ° C., 110 ° C., 130 ° C. and 150 ° C. is about 55% at 70 ° C., about 80% at 90 ° C. About 90% at 130 ° C, about 9% at 130 ° C
8%, and shows a value of 100% at 150 ° C. At 70 ° C. and 90 ° C. in the low temperature range, it takes time for the underfill resin 13 to be completely cured.

【0071】また、硬化反応率と半導体素子の反り量に
は相対関係があり、その一例を図13に示す。縦軸に半
導体チップの反り量を横軸に硬化反応率を示すと例え
ば、回路基板がアラミド材の4層基板(厚み0.4m
m)で半導体素子のサイズが10×10×0.4mmの
場合において、酸無水物エポキシ系の封止材を用いた場
合、硬化反応率40%で半導体素子の反り量は0μm、
80%で約7μm、98%で約25μm、100%で約
35μmの値を示す。
Further, there is a relative relationship between the curing reaction rate and the amount of warpage of the semiconductor element, and one example is shown in FIG. The vertical axis represents the amount of warpage of the semiconductor chip and the horizontal axis represents the curing reaction rate. For example, the circuit board is a four-layer board of aramid material (0.4 m thick).
m), when the size of the semiconductor element is 10 × 10 × 0.4 mm, when an acid anhydride epoxy-based encapsulant is used, the curing reaction rate is 40%, the warpage of the semiconductor element is 0 μm,
It shows a value of about 7 μm at 80%, about 25 μm at 98%, and about 35 μm at 100%.

【0072】従って、半導体素子の反り量の少ない硬化
反応率80%〜98%の範囲で回路基板A面4の実装を
行えば、回路基板B面7に半導体素子を実装する際に比
較的平坦な実装が行える。
Therefore, if the circuit board A surface 4 is mounted within a curing reaction rate of 80% to 98% with a small amount of warpage of the semiconductor element, the semiconductor element is relatively flat when mounted on the circuit board B surface 7. Implementation.

【0073】以上の硬化条件を用いてまず、回路基板A
面4に半導体素子A5をフェースダウンにて搭載後、ア
ンダーフィル樹脂13を充填後110℃・30分の熱処
理によって硬化反応率80%で仮硬化させフリップチッ
プ実装する。
Using the above curing conditions, first, the circuit board A
After the semiconductor element A5 is mounted face down on the surface 4, the underfill resin 13 is filled, and after being heat-treated at 110 ° C. for 30 minutes, it is temporarily cured at a curing reaction rate of 80%, and flip-chip mounted.

【0074】次に回路基板B面7に半導体素子B8を同
じくフェースダウンにて搭載後、回路基板両面に実装さ
れた半導体素子のアンダーフィル樹脂13を150℃・
30分の熱処理にて硬化反応率100%で完全硬化させ
る。これにより、最初にフリップチップ実装された半導
体素子A5は仮硬化状態から完全硬化状態になり、回路
基板A面4と半導体素子A5の接合部に対しては、十分
な密着強度が確保される。
Next, after the semiconductor element B8 is mounted face down on the circuit board B surface 7, the underfill resin 13 of the semiconductor element mounted on both sides of the circuit board is heated to 150 ° C.
It is completely cured at a curing reaction rate of 100% by heat treatment for 30 minutes. As a result, the semiconductor element A5 that is first flip-chip mounted is changed from the pre-cured state to the completely cured state, and a sufficient adhesion strength is secured to the joint between the circuit board A surface 4 and the semiconductor element A5.

【0075】このように、回路基板A面4に実装される
半導体素子A5のアンダーフィル樹脂13の硬化反応率
が80%〜98%の範囲であれば、半導体素子A5の反
り量が少ない範囲でフリップチップ実装が実現できるた
め、回路基板B面7へ実装される半導体素子B8の実装
が容易となる。
As described above, when the curing reaction rate of the underfill resin 13 of the semiconductor element A5 mounted on the circuit board A surface 4 is in the range of 80% to 98%, the warpage of the semiconductor element A5 is small. Since flip-chip mounting can be realized, mounting of the semiconductor element B8 mounted on the circuit board B surface 7 is facilitated.

【0076】さらに、半導体素子B8の実装後、アンダ
ーフィル樹脂13の封止材を硬化反応率100%で完全
硬化させることにより、接続信頼性を向上させることが
できる。
Further, after mounting the semiconductor element B8, the connection reliability can be improved by completely curing the sealing material of the underfill resin 13 at a curing reaction rate of 100%.

【0077】上述の半導体チップの熱膨張係数は2〜3
ppmでり、回路基板は樹脂基板で7〜15ppmと比
較的半導体チップの熱膨張係数に近いアラミド繊維の基
板を用いている。
The above-mentioned semiconductor chip has a thermal expansion coefficient of 2-3.
The circuit board is a resin substrate, and an aramid fiber substrate having a thermal expansion coefficient relatively close to that of a semiconductor chip of 7 to 15 ppm is used.

【0078】(第5の実施の形態)次に、本発明の第5
の実施の形態を説明する。上述した第4の実施の形態と
基本的に同様の硬化条件を用いているため図面は省略す
る。
(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described.
An embodiment will be described. Since the same curing conditions as in the fourth embodiment are used, the drawings are omitted.

【0079】回路基板A面4に半導体素子A5をフェー
スダウンにて搭載後、アンダーフィル樹脂13を硬化反
応率80〜98%の範囲で仮硬化させフリップチップ実
装し、次に回路基板B面7に半導体素子B8をフェース
ダウンにて搭載後、アンダーフィル樹脂13を同様に硬
化反応率80〜98%の範囲で仮硬化させ、フリップチ
ップ実装した後に、両面を完全硬化させる。
After the semiconductor element A5 is mounted face down on the circuit board A surface 4, the underfill resin 13 is temporarily cured within a curing reaction rate of 80 to 98% and flip-chip mounted. After the semiconductor element B8 is mounted face down, the underfill resin 13 is similarly temporarily cured within a curing reaction rate of 80 to 98%, and after flip chip mounting, both sides are completely cured.

【0080】このことにより、回路基板A面4と半導体
素子A5および回路基板B面7と半導体素子B8が同じ
物性を有するアンダーフィル樹脂13で硬化されている
ため、両面の回路基板3にフリップチップ実装された半
導体素子の封止材を一旦、同じ硬化反応率の状態にする
ことにより、応力バランスが取れ熱応力による影響が抑
制され、信頼性が向上する。
Since the circuit board A surface 4 and the semiconductor element A5 and the circuit board B surface 7 and the semiconductor element B8 are cured by the underfill resin 13 having the same physical properties, the flip-chip By once setting the sealing material of the mounted semiconductor element to the same curing reaction rate, the stress is balanced and the influence of the thermal stress is suppressed, and the reliability is improved.

【0081】また、回路基板A面4と回路基板B面7に
構成されるアンダーフィル樹脂13の材料の熱膨張係数
およびヤング率が同等であることが好ましい。
It is preferable that the materials of the underfill resin 13 formed on the circuit board A surface 4 and the circuit board B surface 7 have the same thermal expansion coefficient and Young's modulus.

【0082】(第6の実施の形態)次に、本発明の第6
の実施の形態を図面を参照して説明する。上述した第1
の実施の形態と基本的に同様のものについては、同一符
号を付与し説明を省略する。
(Sixth Embodiment) Next, a sixth embodiment of the present invention will be described.
An embodiment will be described with reference to the drawings. The first mentioned above
Components that are basically the same as those of the first embodiment are given the same reference numerals, and description thereof is omitted.

【0083】図14は、本発明の第6の実施の形態にお
ける、半導体実装治具を用いて、回路基板と半導体素子
を電気的に接続する両面フリップチップ実装の構成と手
順を示した断面図である。
FIG. 14 is a sectional view showing the structure and procedure of double-sided flip-chip mounting for electrically connecting a circuit board and a semiconductor element using a semiconductor mounting jig according to a sixth embodiment of the present invention. It is.

【0084】回路基板A面4に半導体素子A5を実装す
る位置に開口部6を有したプレートA1と回路基板B面
7に半導体素子B8を実装する位置に開口部6を有した
プレートB2との間に回路基板3を介在させて一体構造
とした後、まず、図14に示すように回路基板A面4に
接続用パターンが形成された基板ランド14と半導体素
子A5の接続端子に2段突起バンプ15を形成し、前記
2段突起バンプ15に導電性接着剤16が転写された半
導体素子A5をフェースダウンにて搭載後、前記導電性
接着剤16を硬化することにより、回路基板A面4と半
導体素子A5の電気的接続を得ることができる。
The plate A1 having the opening 6 at the position where the semiconductor element A5 is mounted on the circuit board A surface 4 and the plate B2 having the opening 6 at the position where the semiconductor element B8 is mounted on the circuit board B surface 7 After the circuit board 3 is interposed therebetween to form an integrated structure, first, as shown in FIG. 14, two-stage protrusions are formed on the board land 14 having the connection pattern formed on the circuit board A surface 4 and the connection terminal of the semiconductor element A5. After the bumps 15 are formed, and the semiconductor element A5 having the conductive adhesive 16 transferred to the two-step protruding bumps 15 is mounted face down, the conductive adhesive 16 is cured, so that the circuit board A surface 4 And the semiconductor element A5 can be electrically connected.

【0085】また、前述の導電性接着剤16は、従来の
エポキシ系接着剤と異なり、熱衝撃時の急激な温度変化
により発生する熱応力を緩和することができるととも
に、ハンダ耐熱試験においても良好な信頼性をもつ接着
剤で接合されているため、高信頼性を得ることができ
る。
The above-mentioned conductive adhesive 16 is different from the conventional epoxy adhesive in that it can alleviate the thermal stress generated by a rapid temperature change at the time of thermal shock, and has a good solder heat resistance test. High reliability can be obtained because they are joined with a highly reliable adhesive.

【0086】さらに導電性接着剤16の接着力は、1バ
ンプ当たり約3g程度を有しているため、半導体素子の
取り外しが容易である。従って、半導体素子A5の実装
後は、インサーキットテスター等による電気的検査によ
り、不良半導体素子および実装不良についてリペアーを
行うことができる。
Further, since the adhesive strength of the conductive adhesive 16 is about 3 g per bump, the semiconductor element can be easily removed. Therefore, after the semiconductor element A5 is mounted, the defective semiconductor element and the mounting failure can be repaired by an electrical inspection using an in-circuit tester or the like.

【0087】次に、前記一体構造とした回路基板3を反
転させた後、半導体素子B8を前述したプロセスと同様
に電気的接続を施す。
Next, after the circuit board 3 having the integrated structure is turned over, the semiconductor element B8 is electrically connected in the same manner as in the above-described process.

【0088】その後、半導体素子A5および半導体素子
B8と回路基板3の隙間にアンダーフィル樹脂13を充
填し加熱硬化することにより、安定した接続状態を維持
することができる。
Thereafter, the gap between the semiconductor element A5 and the semiconductor element B8 and the circuit board 3 is filled with the underfill resin 13 and cured by heating, so that a stable connection state can be maintained.

【0089】また、図15の斜視図および図16の断面
図に示すように半導体素子実装前に、回路基板3の半導
体素子実装面に絶縁樹脂17を部分的に塗布し、導電性
接着剤16と同時に硬化することにより、半導体素子と
回路基板が仮固定されるため、装着時およびなんらかの
外部的圧力に対して接続状態を維持することができる。
As shown in the perspective view of FIG. 15 and the cross-sectional view of FIG. 16, an insulating resin 17 is partially applied to the semiconductor element mounting surface of the circuit board 3 before mounting the semiconductor element. At the same time, by curing, the semiconductor element and the circuit board are temporarily fixed, so that the connection state can be maintained at the time of mounting and any external pressure.

【0090】さらに、プレートA1とプレートB2との
間に回路基板3を介在させた一体構造を有するプレート
B2の開口部6に現れる、回路基板B面7の実装面裏面
を突起構造を形成したプレートC10で支持した後、図
14に示した両面フリップチップ実装と同様のプロセス
を用いて、回路基板A面4に半導体素子A5をフェース
ダウンにて搭載し電気的接続を施し、次に、前記一体構
造とした回路基板3を反転させた後、半導体素子B8を
前述したプロセスと同様に電気的接続を施す。
Further, a plate on which the rear surface of the mounting surface of the circuit board B surface 7 appears at the opening 6 of the plate B2 having an integrated structure in which the circuit board 3 is interposed between the plate A1 and the plate B2 is formed with a projection structure. After supporting by C10, the semiconductor element A5 is mounted face down on the circuit board A surface 4 by using the same process as the double-sided flip chip mounting shown in FIG. After inverting the circuit board 3 having the structure, the semiconductor element B8 is electrically connected in the same manner as the above-described process.

【0091】その後、半導体素子A5および半導体素子
B8と回路基板3の隙間にアンダーフィル樹脂13を充
填し加熱硬化して半導体装置を製造する。
Thereafter, a gap between the semiconductor element A5 and the semiconductor element B8 and the circuit board 3 is filled with an underfill resin 13 and cured by heating to manufacture a semiconductor device.

【0092】上述の製造方法を用いた場合においては、
半導体素子を両面に実装した時点ではアンダーフィル樹
脂13が充填されていないため、基板の反りがなく実装
できる。その後、両面に実装された半導体素子と回路基
板3の隙間にアンダーフィル樹脂13を充填後同時に加
熱硬化することによって回路基板3の両面の応力バラン
スが取れ反りが発生しない。この様にして製造された半
導体装置は初期品質が良く信頼性も高いという特徴があ
る。
In the case where the above-described manufacturing method is used,
Since the underfill resin 13 is not filled when the semiconductor element is mounted on both sides, the mounting can be performed without warpage of the substrate. Thereafter, the gap between the semiconductor element mounted on both sides and the circuit board 3 is filled with the underfill resin 13 and then simultaneously heated and cured, so that the stress on both sides of the circuit board 3 is balanced and no warpage occurs. The semiconductor device manufactured in this manner is characterized by high initial quality and high reliability.

【0093】さらに、プレートA1とプレートB2との
間に回路基板3を介在させた一体構造を有するプレート
B2の開口部6に現れる、回路基板B面7の実装面裏面
を突起構造を形成したプレートC10にて回路基板を支
持した後、図14に示した両面フリップチップ実装と同
様のプロセスを用いて、回路基板A面4に半導体素子A
5をフェースダウンにて搭載し、電気的接続を施す。次
に、前記一体構造とした回路基板3を反転させた後、半
導体素子A5が実装された位置に座ぐり部11を設け突
起構造を構成したプレートD12にて、回路基板A面4
あるいは半導体素子A5もしくは両方を支持した後、半
導体素子B8を前述のプロセスと同様に電気的接続を施
す。
Further, a plate on which the back surface of the mounting surface of the circuit board B surface 7 is formed at the opening 6 of the plate B2 having an integrated structure in which the circuit board 3 is interposed between the plate A1 and the plate B2 is formed. After supporting the circuit board at C10, the semiconductor element A is mounted on the circuit board A surface 4 using the same process as the double-sided flip-chip mounting shown in FIG.
5 is mounted face down to make electrical connection. Next, after the circuit board 3 having the integrated structure is turned over, a counterbore portion 11 is provided at a position where the semiconductor element A5 is mounted, and the plate
Alternatively, after supporting the semiconductor element A5 or both, the semiconductor element B8 is electrically connected in the same manner as in the above-described process.

【0094】その後、半導体素子A5および半導体素子
B8と回路基板3の隙間にアンダーフィル樹脂13を充
填後、加熱硬化することにより、回路基板A面4と回路
基板B面7に実装される配置が異なった実装に対しても
簡単に実装することができる。
Thereafter, the gap between the semiconductor elements A5 and B8 and the circuit board 3 is filled with the underfill resin 13 and then cured by heating, so that the arrangement mounted on the circuit board A surface 4 and the circuit board B surface 7 is achieved. It can be easily implemented for different implementations.

【0095】さらに、本発明に実施の形態例2〜6のい
ずれか記載の製造方法は、半導体素子と回路基板間の電
気的な接続は導電性接着剤16を介する構造であり、か
つ、半導体素子と回路基板間に絶縁樹脂17を介在させ
て、導電性接着剤16と同時に加熱硬化するものであ
る。
Further, in the manufacturing method according to any one of the second to sixth embodiments of the present invention, the electrical connection between the semiconductor element and the circuit board has a structure via the conductive adhesive 16 and The insulating resin 17 is interposed between the element and the circuit board, and is heated and cured simultaneously with the conductive adhesive 16.

【0096】尚、本実施例の説明において、半導体素子
の実装方法として両面フリップチップ構成で説明した
が、片面はフェースアップによるベアーチップ実装方式
でも問題はない。また、ACFやC4のような実装形態
でも構わない。
In the description of the present embodiment, a double-sided flip-chip configuration has been described as a method for mounting a semiconductor element. However, there is no problem with a bare-chip mounting method in which one side is face-up. Further, a mounting form such as ACF or C4 may be used.

【0097】さらに、本実施の形態の回路基板A面は本
発明の回路基板の第1の面の例であり、本実施の形態の
回路基板B面は本発明の回路基板の第2の面の例であ
り、本実施の形態の半導体素子Aは本発明の第1の半導
体素子の例であり、本実施の形態の半導体素子Bは本発
明の第2の半導体素子の例であり、本実施の形態のプレ
ートA、B、C、Dはそれぞれ本発明の第1、第2、第
3、第4のプレートの例であり、本実施の形態の一体構
造は本発明の半導体実装対象中間構造体の例である。
Further, the circuit board A surface of the present embodiment is an example of the first surface of the circuit board of the present invention, and the circuit board B surface of the present embodiment is the second surface of the circuit board of the present invention. The semiconductor element A of the present embodiment is an example of the first semiconductor element of the present invention, and the semiconductor element B of the present embodiment is an example of the second semiconductor element of the present invention. The plates A, B, C, and D of the embodiment are examples of the first, second, third, and fourth plates, respectively, of the present invention. It is an example of a structure.

【0098】このように、本発明の半導体実装対象中間
構造体と半導体装置の製造方法は、回路基板のA面およ
びB面と半導体素子AまたはBを実装する位置に開口部
を有したプレートAとプレートBとの間に回路基板を介
在し、一体構造を構成することにより、回路基板の反り
を抑制した状態で、両面に半導体素子をフリップチップ
実装することができ、高い接続信頼性を得ることができ
る。
As described above, according to the method of manufacturing an intermediate structure to be mounted on a semiconductor and the semiconductor device of the present invention, the plate A having the opening at the position where the semiconductor element A or B is mounted on the surface A and the surface B of the circuit board is mounted. A circuit board is interposed between the circuit board and the plate B to form an integral structure, so that semiconductor elements can be flip-chip mounted on both sides in a state in which warpage of the circuit board is suppressed, and high connection reliability is obtained. be able to.

【0099】さらに、プレートの開口部に、突起構造を
有するプレートを配置することによって、回路基板の裏
面を支持できるため、回路基板の表面に実装される半導
体素子の実装荷重等によって生じる回路基板の変形が防
止でき、実装の信頼性をより向上させることができる。
Further, by disposing a plate having a protruding structure in the opening of the plate, it is possible to support the back surface of the circuit board. Deformation can be prevented, and the reliability of mounting can be further improved.

【0100】さらに、回路基板のA面およびB面にサイ
ズの異なる半導体素子AまたはBの実装を行う場合は、
プレートAの開口部の形状をプレートBより狭くしか
つ、半導体素子Bが実装される接合部の裏面をプレート
Aで支持することにより、大きいサイズである半導体素
子Bの接続信頼性に対する影響を最小現に抑制できる。
Further, when mounting semiconductor elements A or B having different sizes on the A and B surfaces of the circuit board,
By making the shape of the opening of the plate A narrower than the plate B and supporting the back surface of the joint where the semiconductor element B is mounted with the plate A, the influence on the connection reliability of the semiconductor element B having a large size is minimized. Actually it can be suppressed.

【0101】また、最初に小さいサイズの半導体素子を
実装した周辺以外は、比較的平坦である特徴を用いて、
回路基板の裏面の平坦部に大きいサイズの半導体素子B
とを両面実装させることにより、安定した接続状態を維
持することが可能である。
Also, except for the periphery where the small-sized semiconductor element is first mounted, the relatively flat feature is used to
A large-sized semiconductor element B on a flat portion on the back surface of the circuit board
By mounting on both sides, a stable connection state can be maintained.

【0102】さらに、上述のアンダーフィル樹脂は、硬
化反応率と半導体素子の反り量には、相対関係があるた
め、半導体素子の反り量の少ない硬化反応率80%〜9
8%の範囲で仮硬化させたることで基板の反りを減少さ
せることができ、裏面へ半導体素子を実装後両面のアン
ダーフィル樹脂を完全硬化することで半導体素子のフリ
ップチップ両面実装を容易にすることができる。
Further, in the above-mentioned underfill resin, since there is a relative relationship between the curing reaction rate and the amount of warpage of the semiconductor element, the curing reaction rate at which the amount of warpage of the semiconductor element is small is 80% to 9%.
By pre-curing in the range of 8%, the warpage of the substrate can be reduced, and after mounting the semiconductor element on the back surface, the underfill resin on both sides is completely cured, thereby facilitating the flip chip double-side mounting of the semiconductor element. be able to.

【0103】また、回路基板へ両面実装された半導体素
子を同じ硬化反応率を示す80〜98%のアンダーフィ
ル樹脂で仮硬化させた後、100%の硬化反応率で完全
硬化させることにより、反りの少ない状態で実装できか
つ、応力バランスの取れた状態でアンダーフィル樹脂を
硬化できる。このように封止材を一旦同じ硬化反応率の
状態にすることにより、応力バランスが取れ熱応力によ
る影響が抑制され信頼性が向上する。
Further, after the semiconductor element mounted on both sides of the circuit board is temporarily cured with an underfill resin of 80 to 98% having the same curing reaction rate, it is completely cured at a curing reaction rate of 100%, so that warpage is caused. The underfill resin can be cured in a state where the stress is well balanced and the underfill resin can be cured. As described above, once the sealing material is brought into the same curing reaction rate, the stress is balanced, the influence of the thermal stress is suppressed, and the reliability is improved.

【0104】さらに、上述の回路基板と半導体素子を電
気的に接合させる導電性接着剤は、従来のエポキシ系接
着剤と異なり、熱衝撃時の急激な温度変化により発生す
る熱応力を緩和することが可能な接着剤で接合されてい
るため、高信頼性を得ることができるとともに、1バン
プ当たり約3g程度を有しているため、半導体素子の取
り外しが容易であり実装後は、インサーキットテスター
等の電気的検査により、不良があればリペアーを行うこ
とができる。
Further, unlike the conventional epoxy adhesive, the conductive adhesive for electrically connecting the circuit board and the semiconductor element relieves the thermal stress generated by a rapid temperature change at the time of thermal shock. High reliability can be obtained because the bonding is performed with an adhesive that can be used, and since the bump has a weight of about 3 g, the semiconductor element can be easily removed. After mounting, the in-circuit tester can be used. Repair can be performed if there is a defect by an electrical inspection such as that described above.

【0105】また、回路基板に絶縁樹脂からなる仮止め
剤を半導体素子の実装領域の一部に塗布後、半導体素子
を実装して導電性接着剤と同時に硬化することにより、
半導体素子と回路基板が仮止め剤によって仮固定される
ため、装着時およびなんらかの外部的圧力に対して接続
状態を維持することができる。
Further, a temporary fixing agent made of an insulating resin is applied to a part of the mounting region of the semiconductor element on the circuit board, and then the semiconductor element is mounted and cured simultaneously with the conductive adhesive.
Since the semiconductor element and the circuit board are temporarily fixed by the temporary fixing agent, the connection state can be maintained at the time of mounting and any external pressure.

【0106】[0106]

【発明の効果】以上説明したところから明らかなよう
に、本発明は薄板で剛性が低い回路基板上へ半導体素子
を両面重なるように配して、両面ベアーチップ実装がで
きる半導体実装対象中間構造体と半導体装置の製造方法
を提供することが出来る。
As is apparent from the above description, the present invention provides a semiconductor mounting intermediate structure in which a semiconductor element is arranged on a thin, low-rigidity circuit board so that both sides thereof are superimposed, and a double-sided bare chip mounting can be performed. And a method for manufacturing a semiconductor device.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態における半導体実装治具の
一例を示す断面図である。
FIG. 1 is a sectional view showing an example of a semiconductor mounting jig according to an embodiment of the present invention.

【図2】本発明の実施の形態における半導体実装治具の
斜視図である。
FIG. 2 is a perspective view of a semiconductor mounting jig according to the embodiment of the present invention.

【図3】本発明の実施の形態における半導体実装治具が
他の手段で構成した断面図である。
FIG. 3 is a cross-sectional view of the semiconductor mounting jig according to the embodiment of the present invention formed by other means.

【図4】本発明の実施の形態における半導体実装治具
に、さらに突起構造のプレートを構成させた一例を示す
断面図である。
FIG. 4 is a cross-sectional view showing an example in which the semiconductor mounting jig according to the embodiment of the present invention further includes a plate having a projection structure.

【図5】本発明の実施の形態における半導体実装治具を
示す斜視図である。
FIG. 5 is a perspective view showing a semiconductor mounting jig according to the embodiment of the present invention.

【図6】本発明の実施の形態における半導体実装治具で
ある突起構造のプレートにさらに座ぐり部を構成させた
一例を示す断面図である。
FIG. 6 is a cross-sectional view illustrating an example in which a spot facing portion is further formed on a plate having a projection structure, which is a semiconductor mounting jig according to the embodiment of the present invention.

【図7】本発明の実施の形態における半導体実装治具を
用いて実装する場合における製造工程の一例を示す断面
図である。
FIG. 7 is a cross-sectional view illustrating an example of a manufacturing process when mounting is performed using the semiconductor mounting jig according to the embodiment of the present invention.

【図8】本発明の実施の形態における半導体実装治具
に、さらに突起構造のプレートを用いて実装する場合に
おける製造工程を示す断面図である。
FIG. 8 is a cross-sectional view showing a manufacturing process when the semiconductor mounting jig according to the embodiment of the present invention is further mounted using a plate having a protruding structure.

【図9】本発明の実施の形態における突起構造のプレー
トに、さらに座ぐり部を構成させた半導体実装治具を用
いて実装する場合における製造工程を示す断面図であ
る。
FIG. 9 is a cross-sectional view showing a manufacturing process in a case where the semiconductor device is mounted on a plate having a projection structure according to the embodiment of the present invention using a semiconductor mounting jig having a counterbore portion.

【図10】本発明の実施の形態における半導体実装治具
が異なった形状を有するプレートを用いて実装する場合
における製造工程を示す断面図である。
FIG. 10 is a cross-sectional view showing a manufacturing process when the semiconductor mounting jig according to the embodiment of the present invention is mounted using plates having different shapes.

【図11】本発明の実施の形態における両面フリップチ
ップ実装をする場合の回路基板の反り状態を示す模式図
である。
FIG. 11 is a schematic diagram illustrating a warped state of a circuit board when performing double-sided flip-chip mounting according to an embodiment of the present invention.

【図12】本発明の実施の形態におけるアンダーフィル
樹脂の硬化反応条件を示す相関図である。
FIG. 12 is a correlation diagram showing a curing reaction condition of the underfill resin in the embodiment of the present invention.

【図13】本発明の実施の形態におけるアンダーフィル
樹脂の硬化反応率と半導体素子の反り量を示す相関図で
ある。
FIG. 13 is a correlation diagram showing a curing reaction rate of an underfill resin and an amount of warpage of a semiconductor element in the embodiment of the present invention.

【図14】本発明の実施の形態における回路基板と半導
体素子を電気的に接続する構成を示した断面図である。
FIG. 14 is a cross-sectional view showing a configuration for electrically connecting a circuit board and a semiconductor element according to an embodiment of the present invention.

【図15】本発明の実施の形態における回路基板に絶縁
樹脂を塗布し、仮固定する場合の構成を示した製造工程
の斜視図である。
FIG. 15 is a perspective view of a manufacturing process showing a configuration in the case where an insulating resin is applied to a circuit board and temporarily fixed in the embodiment of the present invention.

【図16】本発明の実施の形態における仮固定法の構成
を示した断面図である。
FIG. 16 is a cross-sectional view illustrating a configuration of a temporary fixing method according to an embodiment of the present invention.

【図17】従来の半導体実装治具とその製法手順の一例
を示す断面図である。
FIG. 17 is a cross-sectional view showing an example of a conventional semiconductor mounting jig and an example of a manufacturing method thereof.

【図18】従来の回路基板の両面にフリップチップ実装
する場合の説明用の断面図である。
FIG. 18 is a cross-sectional view for explaining a case where flip-chip mounting is performed on both surfaces of a conventional circuit board.

【図19】従来の回路基板の片面にフリップチップ実装
する場合に発生する基板変形を示した模式図である。
FIG. 19 is a schematic diagram showing substrate deformation that occurs when flip-chip mounting is performed on one surface of a conventional circuit board.

【符号の説明】[Explanation of symbols]

1 プレートA 2 プレートB 3 回路基板 4 回路基板A面 5 半導体素子A 6 開口部 7 回路基板B面 8 半導体素子B 9 接合部 10 プレートC 11 座ぐり部 12 プレートD 13 アンダーフィル樹脂 14 基板ランド 15 2段突起バンプ 16 導電性接着剤 17 絶縁樹脂 18 溝加工部 19 取り付けビス 20 規制ピン Reference Signs List 1 plate A 2 plate B 3 circuit board 4 circuit board A surface 5 semiconductor element A 6 opening 7 circuit board B surface 8 semiconductor element B 9 bonding portion 10 plate C 11 spot facing portion 12 plate D 13 underfill resin 14 substrate land 15 Two-step projection bump 16 Conductive adhesive 17 Insulating resin 18 Groove processing part 19 Mounting screw 20 Regulator pin

フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 23/12 H01L 23/12 F H05K 3/32 3/34 509 (72)発明者 神澤 英雄 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 白石 司 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 祐伯 聖 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 天見 和由 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Fターム(参考) 5E319 AA03 AA08 AB05 AC04 CD16 GG11 GG20 5F044 KK23 LL07 RR01 RR17 RR18 RR19 5F061 AA01 BA03 CB02 FA03 Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat II (Reference) H01L 23/12 H01L 23/12 F H05K 3/32 3/34 509 (72) Inventor Hideo Kanzawa Kadoma, Osaka Pref. 1006 Kadoma, Matsushita Electric Industrial Co., Ltd. In-house (72) Inventor Kazuyoshi Amami 1006 Kazuma, Kazuma, Osaka Prefecture F-term (reference) 5E319 AA03 AA08 AB05 AC04 CD16 GG11 GG20 5F044 KK23 LL07 RR01 RR17 RR18 RR19 5F061 AA03 BA03 CB

Claims (15)

【特許請求の範囲】[Claims] 【請求項1】 回路基板と、 前記回路基板の第1の面に第1の半導体素子を実装する
位置に開口部を有する第1のプレートと、 前記回路基板の第2の面に第2の半導体素子を実装する
位置に開口部を有する第2のプレートとを備え、 前記回路基板の前記第1の面に前記第1のプレートが、
前記第2の面に前記第2のプレートがそれぞれ当接され
た半導体実装対象中間構造体であって、 前記第1のプレートの各フレームとそれらに対向する前
記第2のプレートの各フレームとは少なくとも一部が重
なっていることを特徴とする半導体実装対象中間構造
体。
A first plate having an opening at a position where a first semiconductor element is mounted on a first surface of the circuit board; and a second plate on a second surface of the circuit board. A second plate having an opening at a position where the semiconductor element is mounted, wherein the first plate is provided on the first surface of the circuit board,
A semiconductor mounting target intermediate structure in which the second plate is in contact with the second surface, wherein each frame of the first plate and each frame of the second plate opposed thereto are An intermediate structure to be mounted on a semiconductor, wherein the intermediate structure is at least partially overlapped.
【請求項2】 前記回路基板の前記第2の面の開口部に
対応する位置に突起部を有し、前記突起部が前記回路基
板の第2の面に当接する第3のプレートを備え、 前記第3のプレートは、前記第1の半導体を実装する際
に用いられることを特徴とする請求項1記載の半導体実
装対象中間構造体。
2. A third plate having a projection at a position corresponding to an opening on the second surface of the circuit board, wherein the projection is in contact with a second surface of the circuit board, 2. The intermediate structure according to claim 1, wherein the third plate is used when mounting the first semiconductor. 3.
【請求項3】 前記回路基板の前記第1の面の開口部に
対応する位置に突起部を有し、前記突起部には、前記第
1の半導体が実装されている位置に座ぐり構造が設けら
れており、前記突起部が前記回路基板の第1の面に当接
する第4のプレートを備え、 前記第4のプレートは、前記第2の半導体を実装する際
に用いられることを特徴とする請求項2記載の半導体実
装対象中間構造体。
3. A circuit board having a projection at a position corresponding to an opening on the first surface, wherein the projection has a spot facing structure at a position where the first semiconductor is mounted. And a fourth plate in which the protrusion is in contact with a first surface of the circuit board, wherein the fourth plate is used when mounting the second semiconductor. The intermediate structure to be mounted on a semiconductor according to claim 2.
【請求項4】 前記座ぐり構造の深さは、前記回路基板
表面から前記第1の半導体素子の裏面までの高さ以上で
あることを特徴とする請求項3記載の半導体実装対象中
間構造体。
4. The intermediate structure according to claim 3, wherein a depth of the counterbore structure is equal to or greater than a height from a front surface of the circuit board to a back surface of the first semiconductor element. .
【請求項5】 回路基板の第1の面と第2の面にそれぞ
れ第1及び第2の半導体素子をフリップチップ実装する
半導体装置の製造方法であって、 前記回路基板の第1の面に前記第1の半導体素子を実装
する位置に開口部を有する第1のプレートと、前記回路
基板の第2の面に前記第2の半導体素子を実装する位置
に開口部を有する第2のプレートとを、ぞれぞれ前記回
路基板の前記第1の面と前記第2の面に当接して半導体
実装対象中間構造体を形成し、 前記半導体実装対象中間構造体の前記第1のプレートの
各フレームとそれらに対向する前記第2のプレートの各
フレームとは少なくとも一部が重なっているものであ
り、 前記回路基板の第1の面に前記第1の半導体素子をフェ
ースダウンにて搭載して、アンダーフィル樹脂を硬化さ
せてフリップチップ実装し、 前記半導体実装対象中間構造体を反転させた後、前記回
路基板の第2の面に前記第2の半導体素子をフェースダ
ウンにて搭載して、アンダーフィル樹脂を硬化させてフ
リップ実装することを特徴とする半導体装置の製造方
法。
5. A method of manufacturing a semiconductor device, wherein first and second semiconductor elements are flip-chip mounted on a first surface and a second surface of a circuit board, respectively. A first plate having an opening at a position where the first semiconductor element is mounted; and a second plate having an opening at a position where the second semiconductor element is mounted on a second surface of the circuit board. Abuts the first surface and the second surface of the circuit board, respectively, to form a semiconductor mounting target intermediate structure; and each of the first plates of the semiconductor mounting target intermediate structure At least a part of the frame and each frame of the second plate facing the frame overlap, and the first semiconductor element is mounted face-down on the first surface of the circuit board. To cure the underfill resin After flip-chip mounting and inverting the semiconductor mounting target intermediate structure, the second semiconductor element is mounted face down on the second surface of the circuit board, and the underfill resin is cured and flipped. A method for manufacturing a semiconductor device, comprising: mounting.
【請求項6】 前記第1の半導体を搭載する際、前記回
路基板の前記第2の面の開口部に対応する位置に突起部
を有する第3のプレートを前記回路基板の第2の面に当
接させることを特徴とする請求項5記載の半導体装置の
製造方法。
6. When mounting the first semiconductor, a third plate having a protrusion at a position corresponding to an opening on the second surface of the circuit board is mounted on the second surface of the circuit board. 6. The method according to claim 5, wherein the contact is performed.
【請求項7】 前記第2の半導体素子を搭載する際、前
記第1の半導体素子が実装された位置に座ぐり構造を設
けた突起を前記回路基板の前記第1の面の開口部に対応
する位置に有する第4のプレートを前記回路基板の第1
の面に当接させることを特徴とする請求項5または6に
記載の半導体装置の製造方法。
7. When mounting the second semiconductor element, a projection provided with a spot facing structure at a position where the first semiconductor element is mounted corresponds to an opening in the first surface of the circuit board. A fourth plate at a position corresponding to the first position of the circuit board.
7. The method of manufacturing a semiconductor device according to claim 5, wherein the semiconductor device is brought into contact with the surface of the semiconductor device.
【請求項8】 回路基板の第1の面と第2の面の両面に
それぞれ半導体素子をフリップチップ実装する半導体装
置の製造方法であって、 前記両面に搭載する半導体素子のサイズが異なってお
り、前記両面に前記半導体素子を搭載する位置が重なっ
ている場合、 前記回路基板の第1の面にサイズの小さい方の前記半導
体素子をフェースダウンにて搭載して、アンダーフィル
樹脂を硬化させてフリップチップ実装し、 前記回路基板を反転させた後、前記回路基板の第2の面
にサイズの大きい方の前記半導体素子をフェースダウン
にて搭載して、アンダーフィル樹脂を硬化させてフリッ
プチップ実装することを特徴とする半導体装置の製造方
法。
8. A method of manufacturing a semiconductor device in which semiconductor elements are flip-chip mounted on both surfaces of a first surface and a second surface of a circuit board, wherein the sizes of the semiconductor elements mounted on the two surfaces are different. In the case where the positions where the semiconductor elements are mounted on the both surfaces are overlapped, the smaller semiconductor element is mounted face down on the first surface of the circuit board, and the underfill resin is cured. After flip-chip mounting and flipping the circuit board, the larger semiconductor element is mounted face-down on the second surface of the circuit board, and the underfill resin is cured to perform flip-chip mounting. A method of manufacturing a semiconductor device.
【請求項9】 回路基板の第1の面と第2の面にそれぞ
れ第1及び第2の半導体素子をフリップチップ実装する
半導体装置の製造方法であって、 前記回路基板の第1の面に前記第1の半導体素子をフェ
ースダウンにて搭載後、アンダーフィル樹脂を硬化反応
率98%以下で仮硬化させフリップチップ実装し、 前記回路基板の第2の面に前記第2の半導体素子をフェ
ースダウンにて搭載後、前記アンダーフィル樹脂を完全
硬化させてフリップチップ実装することを特徴とする半
導体装置の製造方法。
9. A method of manufacturing a semiconductor device, wherein first and second semiconductor elements are flip-chip mounted on a first surface and a second surface of a circuit board, respectively. After mounting the first semiconductor element face down, the underfill resin is preliminarily cured at a curing reaction rate of 98% or less and flip-chip mounted, and the second semiconductor element is mounted on the second surface of the circuit board by the face. A method for manufacturing a semiconductor device, wherein after mounting the semiconductor device in a down state, the underfill resin is completely cured and flip-chip mounted.
【請求項10】 回路基板の第1の面と第2の面の両面
にそれぞれ第1及び第2の半導体素子をフリップチップ
実装する半導体装置の製造方法であって、 前記回路基板の第1の面に前記第1の半導体素子をフェ
ースダウンにて搭載後、アンダーフィル樹脂を硬化反応
率98%以下で仮硬化させフリップチップ実装し、 前記回路基板の第2の面に前記第2の半導体素子をフェ
ースダウンにて搭載後、アンダーフィル樹脂を硬化反応
率98%以下で仮硬化させフリップチップ実装し、 前記両面のアンダーフィル樹脂を完全硬化させることを
特徴とする半導体装置の製造方法。
10. A method of manufacturing a semiconductor device, wherein first and second semiconductor elements are flip-chip mounted on both surfaces of a first surface and a second surface of a circuit board, respectively. After the first semiconductor element is mounted face down on the surface, the underfill resin is provisionally cured at a curing reaction rate of 98% or less and flip-chip mounted, and the second semiconductor element is mounted on the second surface of the circuit board. And mounting the flip-chip in a face-down manner, temporarily curing the underfill resin at a curing reaction rate of 98% or less, flip-chip mounting, and completely curing the underfill resin on both surfaces.
【請求項11】 前記回路基板の第1の面と第2の面に
用いられる前記アンダーフィル樹脂材料の熱膨張係数お
よびヤング率が同等であることを特徴とする請求項9ま
たは10に記載の半導体装置の製造方法。
11. The method according to claim 9, wherein the underfill resin materials used for the first surface and the second surface of the circuit board have the same thermal expansion coefficient and Young's modulus. A method for manufacturing a semiconductor device.
【請求項12】 回路基板の第1の面と第2の面にそれ
ぞれ第1及び第2の半導体素子をフリップチップ実装す
る半導体装置の製造方法であって、 前記回路基板の第1の面に前記第1の半導体素子を実装
する位置に開口部を有する第1のプレートと、前記回路
基板の第2の面に前記第2の半導体素子を実装する位置
に開口部を有する第2のプレートとを、ぞれぞれ前記回
路基板の前記第1の面と前記第2の面に当接して半導体
実装対象中間構造体を形成し、 前記半導体実装対象中間構造体の前記第1のプレートの
各フレームとそれらに対向する前記第2のプレートの各
フレームとは少なくとも一部が重なっているものであ
り、 前記回路基板の第1の面に前記第1の半導体素子をフェ
ースダウンにて搭載して電気的接続を施し、 前記半導体実装対象中間構造体を反転させた後、前記回
路基板の第2の面に前記第2の半導体素子をフェースダ
ウンにて搭載して電気的接続を施し、 前記第1及び第2の半導体素子と、前記回路基板との隙
間にアンダーフィル樹脂を充填後加熱硬化することを特
徴とする半導体装置の製造方法。
12. A method for manufacturing a semiconductor device, wherein first and second semiconductor elements are flip-chip mounted on a first surface and a second surface of a circuit board, respectively. A first plate having an opening at a position where the first semiconductor element is mounted; and a second plate having an opening at a position where the second semiconductor element is mounted on a second surface of the circuit board. Abuts the first surface and the second surface of the circuit board, respectively, to form a semiconductor mounting target intermediate structure; and each of the first plates of the semiconductor mounting target intermediate structure At least a part of the frame and each frame of the second plate facing the frame overlap, and the first semiconductor element is mounted face-down on the first surface of the circuit board. Electrical connection is made, and the semiconductor After inverting the target intermediate structure, the second semiconductor element is mounted face down on the second surface of the circuit board to make an electrical connection, and the first and second semiconductor elements are A method for manufacturing a semiconductor device, comprising: filling a gap with the circuit board with an underfill resin; and heating and curing the gap.
【請求項13】 前記第1の半導体に電気的接続を施す
際、前記回路基板の前記第2の面の開口部に対応する位
置に突起部を有する第3のプレートを前記回路基板の第
2の面に当接させることを特徴とする請求項12記載の
半導体装置の製造方法。
13. When making an electrical connection to the first semiconductor, a third plate having a protrusion at a position corresponding to an opening on the second surface of the circuit board is attached to a second plate of the circuit board. 13. The method for manufacturing a semiconductor device according to claim 12, wherein the semiconductor device is brought into contact with the surface.
【請求項14】 前記第2の半導体素子に電気的接続を
施す際、前記第1の半導体素子が実装された位置に座ぐ
り構造を設けた突起を前記回路基板の前記第1の面の開
口部に対応する位置に有する第4のプレートを前記回路
基板の第1の面に当接させることを特徴とする請求項1
2または13に記載の半導体装置の製造方法。
14. When making electrical connection to the second semiconductor element, a projection provided with a spot facing structure at a position where the first semiconductor element is mounted is formed in an opening on the first surface of the circuit board. 2. A circuit board according to claim 1, wherein a fourth plate provided at a position corresponding to the portion contacts the first surface of the circuit board.
14. The method for manufacturing a semiconductor device according to 2 or 13.
【請求項15】 請求項5〜14のいずれか記載の半導
体装置の製造方法において、前記半導体素子と前記回路
基板間の電気的な接続は、導電性接着剤を介して接続さ
れる構造であり、 前記半導体素子と前記回路基板間に絶縁樹脂を介在させ
て、前記導電性接着剤と同時に加熱硬化したことを特徴
とする半導体装置の製造方法。
15. The method for manufacturing a semiconductor device according to claim 5, wherein an electrical connection between said semiconductor element and said circuit board is connected via a conductive adhesive. A method of manufacturing a semiconductor device, wherein an insulating resin is interposed between the semiconductor element and the circuit board, and heat-cured simultaneously with the conductive adhesive.
JP2000145603A 2000-05-17 2000-05-17 Semiconductor mounting target intermediate structure and method of manufacturing semiconductor device Expired - Fee Related JP3300698B2 (en)

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