JP2001326260A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase strength at a pad part being touched by the probe terminal of an inspection equipment. SOLUTION: A second layer probe inspection pad metal 300 for laying a part of probe inspection pad in layer by lowering a first power supply main line 123 while ensuring a sufficient distance L2, and a contact 310 for touching the third and second layers of that probe inspection pad are arranged in an I/O cell 301.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which the strength of a pad portion with which a probe terminal of an inspection device contacts is increased.

[0002]

2. Description of the Related Art FIG. 4 shows a first configuration of a conventional semiconductor device employing a three-layer metal process. In FIG. 4, 127 is a silicon substrate. Reference numeral 101 denotes an input / output cell formed on the silicon substrate 127, which is a dedicated cell for inputting / outputting a signal.

An N-channel output / protection transistor section 111, a P-channel output / protection transistor section 112, and an output pre-buffer section 113 are formed on the surface of a silicon substrate 127. The N-channel output / protection transistor unit 111 includes an N-channel transistor for outputting an L level and an N-channel transistor for surge protection. The P-channel output / protection transistor section 112 includes a P-channel transistor for outputting an H level signal and a P-channel transistor for surge protection. The output prebuffer unit 113 has a circuit for switching the input and output of the input / output cell 101, and performs input prohibition during output and output prohibition during input.

A first layer metal 126 is formed on a silicon substrate 127 via a gate oxide film. First
The layer metal 126 controls signal input to the inside, signal output from the inside, and connection to the surge protection transistor (not shown).

On the first layer metal 126, a second layer pad metal 121, a second layer ground trunk line 122, and a first
Of the second layer power supply main line 123 and the second second layer power supply main line 12
4 are formed via the first and second metal interlayer films.
The second layer pad metal 121 is provided to increase the pad strength, and is provided for the pad metal contact 12.
5 is connected to the first layer metal 126. Second
The layer ground trunk line 122 shares the potential with cells arranged on both sides of the input / output cell 101 for the purpose of fixing the ground potential, and the N-channel output / protection transistor unit 11
1 is supplied with a source potential. The first second-layer power supply trunk line 123 shares a potential with cells arranged on both sides of the input / output cell 101 for the purpose of fixing the power supply potential, and
The source potential is supplied to the channel output / protection transistor unit 112. Second second-layer power supply main line 124
Is for sharing the potential with cells arranged on both sides of the input / output cell 101 for the purpose of fixing the power supply potential, and for supplying power to the output pre-buffer unit 113.

A third-layer pad metal 110 is provided on the second-layer pad metal 121, a third-layer ground main line 114 is provided on the second-layer ground main line 122, and a first-layer power supply main line 123 is provided on the first second-layer power main line 123. Has a first third-layer power supply main line 115 and a second
On the second-layer power supply trunk line 124, second third-layer power supply trunk lines 116 are formed via second and third metal interlayer films, respectively. The third layer pad metal 110 is a pad for probe inspection and bonding. Reference numeral 117 denotes a pad metal contact for connecting the third layer pad metal 110 and the second layer pad metal 121 to the same potential.
Reference numeral 18 denotes a ground main line contact for connecting the third layer ground main line 114 and the second layer ground main line 122 to the same potential, and 119 denotes a first third layer power main line 115 and a first
Is a first power supply main line contact for connecting the second layer power supply main line 123 to the same potential, and 120 is a first power supply main line contact for connecting the second third layer power supply main line 116 and the second second layer power supply main line 124 to the same potential. To the second power supply main line contact.

The probe of the inspection device is brought into contact with the third layer pad metal 110 to inspect the input / output cell 101 and the circuit to which the input / output cell 101 is connected.
In addition, wire bonding when assembling the semiconductor device is also performed. Therefore, the second layer pad metal 121 and the third
It has a laminated structure with the layer pad metal 110, and its strength is increased. Therefore, it has a characteristic that it is not easily broken even if the probe of the inspection device comes into contact with the probe a plurality of times.

FIG. 5 shows a second configuration of a conventional semiconductor device. In FIG. 5, those having the same numbers as those in FIG. 4 perform the same functions. The second configuration shown in FIG. 5 is different from the first configuration shown in FIG. 4 in that the pad metal in the input / output cell 201 is divided into a third-layer pad metal 110 and a third-layer probe test pad metal 210. Have been. this is,
Pad section, ground trunk line, 1st section to reduce cell area
This is because each of the power supply trunk lines has a single layer, and in particular, the strength of the pad metal is lower than that of the configuration of FIG. However, if the probe of the inspection apparatus comes into contact with the probe a plurality of times, the third-layer probe inspection pad metal 210 may be easily broken, and the probe of the inspection apparatus may penetrate the first second-layer power supply main line 123.

[0009]

In a semiconductor device, there is a demand for an improvement in bonding pad strength while reducing the area. In the conventional three-layer metal process technology, as shown in FIG. 4, a large area is required to improve the strength of a pad for performing a probe test and performing assembly bonding. In addition, as shown in FIG. 5, the pad strength was low and a small area was realized. That is, conventionally, there was a problem that the area was large with respect to the required strength as shown in FIG. 4, and the strength was insufficient with respect to the required area as shown in FIG.

An object of the present invention is to provide a semiconductor device having a small area and an increased strength of a pad portion.

[0011]

In order to achieve the above-mentioned object, in the first semiconductor device according to the present invention, the pad metal for probe inspection in the input / output cell is partially laminated to obtain a structure as shown in FIG. Improves the strength of the pad metal for probe inspection in the same area.

Further, a second semiconductor device according to the present invention comprises:
The entire area of the pad metal for probe inspection in the input / output cell is laminated.

Further, a third semiconductor device according to the present invention comprises:
In the power supply terminal cell, the entire area of the pad metal for probe inspection is laminated with the same area as in FIG.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

(First Embodiment) FIG. 1 shows a configuration of a semiconductor device according to a first embodiment of the present invention. In FIG. 1, the 100s and 200s correspond to the same reference numerals in FIGS. 4 and 5. The difference between the input / output cells 301 of the present invention is that the distance L1 in FIG. 5 is extended to L2, the first power supply main line 123 is lowered, and only a part of the probe test pad is laminated. Inspection pad metal 300
And a probe metal contact 3 for connecting the third layer and the second layer of the probe inspection pad.
10 is provided.

That is, the first second-layer power supply main line 123 is moved in a direction to reduce the overlap with the third-layer probe test pad metal 210, and the strength of the probe test pad metal is improved in the same area as that of FIG. A second-layer probe test pad metal 300 is formed by partially forming the second-layer probe test pad metal 300.

With this structure, as in FIG. 5, a part of the probe test pad becomes a laminated pad with a small area, as in FIG. 5, so that it can have strength enough to withstand a plurality of probe tests.

(Embodiment 2) FIG. 2 shows a configuration of a semiconductor device according to a second embodiment of the present invention. 2, 100's and 200's correspond to the same reference numerals in FIGS. 4 and 5, and 300's correspond to the same reference numerals in FIG. The difference between the input / output cell 401 of the present invention and FIG.
By increasing the middle distance L1 to L3, a laminated pad formation region 40 for laminating the entire region of the probe inspection pad
0, and the area of the second-layer probe test pad metal 300 in FIG.
0, and the probe of the inspection device is connected to the third layer pad metal (bonding pad) 11 as much as possible.
That is, the first power supply main line 115 has been moved to take the value closer to zero.

With this structure, an input / output cell 401 having an area larger than that of FIG. 5 but smaller than that of FIG. 4 can be realized. Since the entire area of the probe test pad is a laminated pad, it can withstand a plurality of probe tests. Can have strength.

(Embodiment 3) FIG. 3 shows a configuration of a semiconductor device according to a third embodiment of the present invention. First and second
Has been described with reference to the case of the input / output cell, but the case of the power supply terminal cell for supplying the power supply voltage will be described here. In FIG. 3, the 100s and 200s correspond to the same reference numerals in FIGS. 4 and 5. The power supply terminal cell 501 of the present invention differs from the first power supply main line of the second layer (FIG. 1).
By providing the dual-purpose part 500 of 123) in FIG. 4 and the pad metal for the second layer probe test (300 in FIGS. 1 and 2), the pad metal 210 for the third layer probe test with the same area as FIG. This is the point that all regions are laminated. 502 is a pad metal contact for probe inspection.

According to this structure, in the power supply terminal cell, as in FIG. 5, a part of the probe test pad becomes a laminated pad with a small area, so that it can have strength enough to withstand a plurality of probe tests.

[0022]

As described above, according to the semiconductor device of the present invention, there is an effect that the strength of the probe test pad metal can be improved in a small area.

[Brief description of the drawings]

FIGS. 1A and 1B are a plan view and a cross-sectional view, respectively, of a semiconductor device according to a first embodiment of the present invention.

FIGS. 2A and 2B are a plan view and a cross-sectional view, respectively, of a semiconductor device according to a second embodiment of the present invention.

FIGS. 3A and 3B are a plan view and a cross-sectional view, respectively, of a semiconductor device according to a third embodiment of the present invention.

FIGS. 4A and 4B are a plan view and a sectional view, respectively, of a semiconductor device according to a first conventional example.

FIGS. 5A and 5B are a plan view and a cross-sectional view, respectively, of a semiconductor device according to a second conventional example.

[Explanation of symbols]

101, 201, 301, 401 I / O cell 110 Third layer pad metal 111 N-channel output / protection transistor section 112 P-channel output / protection transistor section 113 Output prebuffer section 114 Third layer ground trunk 115 First third layer Power supply main line 116 Second third-layer power supply main line 117 Pad metal contact 118 Ground main line contact 119 First power supply main line contact 120 Second power supply main line contact 121 Second layer pad metal 122 Second layer ground main line 123 First first 2nd layer power supply main line 124 2nd 2nd layer power supply main line 125 pad metal contact 126 1st layer metal 127 silicon substrate 210 3rd layer probe inspection pad metal 300 2nd layer probe inspection pad metal 310 probe inspection pad metal Contact 400 Stack pad formation area 500 Dual-purpose part of first second layer power supply main line and second layer probe inspection pad metal 501 Power supply terminal cell 502 Probe inspection pad metal contact

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G032 AA00 AK00 AK01 AL03 4M106 AA01 AA02 AD03 5F033 MM05 VV07 VV12 9A001 BB06 LL05

Claims (3)

[Claims] 1. A semiconductor device employing a three-layer metal process, wherein an input / output cell for inputting / outputting a signal of the semiconductor device comprises: an N-channel output / protection transistor unit; a P-channel output / protection transistor unit; An output pre-buffer unit, a metal of a power supply trunk line and a ground trunk line, and a partially laminated pad for probe inspection and a single-layer pad for bonding provided on both of the transistor units. Semiconductor device. 2. A semiconductor device employing a three-layer metal process, wherein in an input / output cell for inputting / outputting a signal of the semiconductor device, an N-channel output / protection transistor unit; A P-channel output / protection transistor section provided at a fixed distance, an output pre-buffer section, a metal of a power supply main line and a ground main line, and provided on the two transistor sections and a gap therebetween;
A semiconductor device comprising a laminated pad for probe inspection and a single-layer pad for bonding. 3. A semiconductor device employing a three-layer metal process, wherein in a power supply terminal cell for inputting a power supply voltage of the semiconductor device, an N-channel output / protection transistor portion; A metal for a power main line and a ground main line, a pad for probe inspection connected to the metal for the power main line on both of the transistor portions, and a single-layer pad for bonding provided on both of the transistor portions. A semiconductor device characterized by the above-mentioned.