CN110085605B - Display device - Google Patents
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- CN110085605B CN110085605B CN201910406739.5A CN201910406739A CN110085605B CN 110085605 B CN110085605 B CN 110085605B CN 201910406739 A CN201910406739 A CN 201910406739A CN 110085605 B CN110085605 B CN 110085605B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1229—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different crystal properties within a device or between different devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Abstract
A display device comprises a substrate, a first element layer, a second element layer, a first adhesion layer and a display element layer. The first element layer, the first adhesive layer, the second element layer and the display element layer are sequentially stacked on the substrate. The first element layer comprises a plurality of signal lines and first thin film transistors. The first thin film transistor has a first gate, a first source, a first drain, and a first semiconductor pattern. The second element layer comprises a second thin film transistor electrically connected with the first thin film transistor. The second thin film transistor has a first polysilicon semiconductor pattern. At least one of the first grid electrode, the first source electrode and the first drain electrode and the plurality of signal lines belong to the same film layer. The material of the first semiconductor pattern includes a metal oxide semiconductor or an amorphous silicon semiconductor.
Description
Technical Field
The present invention relates to a display device, and more particularly, to a high-resolution display device.
Background
As the technology industry has been developed, display devices such as mobile phones (mobile phones), tablet computers (tablet computers), and electronic books (ebooks) have been widely used in daily life. In particular, in recent years, with the advent of multimedia applications such as stereoscopic display (stereoscopic display) and virtual reality (visual reality), there has been an increasing demand for display panels having ultra-high resolution in order to provide an amazing visual effect.
Under the increasing resolution of display panels, the driving circuit is designed under the pixel structure in a stacked structure to solve the problem of insufficient layout space of the driving circuit, which is one of the current solutions. However, the use of the stacked structure will increase the complexity of the manufacturing process and the production cost. Therefore, it is an important issue to simplify the process and reduce the production cost when the design of the driving circuit adopts the stacked structure.
Disclosure of Invention
The invention provides a display device which has the advantages of cost and good electrical property.
The display device comprises a substrate, a first element layer, a second element layer, a first adhesion layer and a display element layer. The first element layer is disposed on the substrate. The first element layer comprises a plurality of signal lines and first thin film transistors. The first thin film transistor has a first gate, a first source, a first drain, and a first semiconductor pattern. The second element layer is disposed on the first element layer. The second element layer comprises a second thin film transistor which is electrically connected with the first thin film transistor. The second thin film transistor has a second gate, a second source, a second drain, and a first polysilicon semiconductor pattern. The first adhesion layer is arranged between the first element layer and the second element layer. The display element layer is disposed on the second element layer. The display element layer comprises a first electrode which is electrically connected with the second thin film transistor. At least one of the first grid electrode, the first source electrode and the first drain electrode and the plurality of signal lines belong to the same film layer. The material of the first semiconductor pattern includes a metal oxide semiconductor or an amorphous silicon semiconductor.
In an embodiment of the invention, a first drain of the first thin film transistor of the display device is electrically connected to a second source of the second thin film transistor.
In an embodiment of the invention, the second gate of the second thin film transistor of the display device is disposed between the first polysilicon semiconductor patterns of the first thin film transistor and the second thin film transistor.
In an embodiment of the invention, the first element layer of the display device further includes a third thin film transistor having a third gate, a third source, a third drain and a second semiconductor pattern. At least one of the third grid electrode, the third source electrode and the third drain electrode and the plurality of signal lines belong to the same film layer. The material of the second semiconductor pattern comprises a metal oxide semiconductor or an amorphous silicon semiconductor.
In an embodiment of the invention, the display device further includes a third element layer and a second adhesive layer. The third element layer is disposed between the second element layer and the display element layer. The second adhesive layer is disposed between the second element layer and the third element layer. The third element layer includes a fourth thin film transistor. The fourth thin film transistor has a fourth gate, a fourth source, a fourth drain, and a second polysilicon semiconductor pattern. The third drain of the third thin film transistor is electrically connected with the fourth source of the fourth thin film transistor.
In an embodiment of the invention, a fourth gate of the fourth thin film transistor of the display device is disposed between the second polysilicon semiconductor patterns of the third thin film transistor and the fourth thin film transistor.
In an embodiment of the invention, the second element layer of the display device further includes a first conductive element electrically connected between the third drain of the third tft and the fourth source of the fourth tft.
In an embodiment of the invention, the first element layer of the display device further includes a fifth thin film transistor. The fifth thin film transistor has a fifth gate, a fifth source, a fifth drain, and a third semiconductor pattern. At least one of the fifth grid electrode, the fifth source electrode and the fifth drain electrode and the plurality of signal lines belong to the same film layer. The material of the third semiconductor pattern includes a metal oxide semiconductor or an amorphous silicon semiconductor.
In an embodiment of the invention, the display device further includes a fourth element layer and a third adhesive layer. The fourth element layer is disposed between the third element layer and the display element layer. The third adhesive layer is disposed between the third element layer and the fourth element layer. The fourth element layer includes a sixth thin film transistor. The sixth thin film transistor has a sixth gate, a sixth source, a sixth drain, and a third polysilicon semiconductor pattern. The fifth drain of the fifth thin film transistor is electrically connected with the sixth source of the sixth thin film transistor.
In an embodiment of the invention, a sixth gate of a sixth thin film transistor of the display device is disposed between the third polysilicon semiconductor patterns of the fifth thin film transistor and the sixth thin film transistor.
In an embodiment of the invention, the second element layer of the display device further includes a first conductive element. The first conductive element is electrically connected with the fifth drain electrode of the fifth thin film transistor. The third element layer further includes a second conductive element. The second conductive element is electrically connected between the first conductive element and the sixth source of the sixth thin film transistor.
In view of the above, in the display device according to the embodiment of the invention, the polysilicon thin film transistor and the thin film transistor having the metal oxide semiconductor or the amorphous silicon semiconductor are respectively disposed on the pixel circuit element layer and the circuit element layer which are bonded to each other by the adhesive layer, so that the process tolerance and the design margin of the circuit can be increased. In addition, at least one of the source electrode, the drain electrode and the grid electrode of the thin film transistor and the plurality of signal lines are the same film layer, so that the number of photomasks can be reduced, the processing procedure can be simplified, and the production cost can be effectively reduced. In addition, the polycrystalline silicon thin film transistor is electrically connected with the thin film transistor with the metal oxide semiconductor or the amorphous silicon semiconductor, so that leakage current (leakage current) generated by the polycrystalline silicon thin film transistor can be effectively reduced, and the display quality is improved.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic cross-sectional view of a display device according to an embodiment of the invention.
Fig. 2A to 2E are schematic structural cross-sectional views of the display device of fig. 1 at different stages in the manufacturing process.
Wherein the reference numerals are as follows:
10: display device
50: substrate
51: temporary substrate
100: circuit element layer
110. 210: buffer layer
120. 220, and (2) a step of: gate insulating layer
130. 230: interlayer insulating layer
140. 241, 241A to 241i, 242A to 242 e: conductive element
150. 250: insulating layer
150s, 250 s: surface of
160. 260, 261, 262a, 262 b: connecting pad
160s, 262 s: the top surface
200. 201, 202, 203: pixel circuit element layer
300: adhesive layer
400: display element layer
410. 411, 412, 413: a first electrode
420: pixel definition layer
421: opening of the container
430: display medium
440: second electrode
450: encapsulation layer
D. PD: drain electrode
G. PG: grid electrode
n: normal direction
PSC: polycrystalline silicon semiconductor pattern
S, PS: source electrode
SC: semiconductor pattern
SL, SL1 to SL 5: signal line
T, T1-T3, PT 1-PT 3: thin film transistor
VC1 a-VC 1 c: first vertical conductive structure
VC2 a-VC 2 b: second vertical conductive structure
VC 3: third vertical conductive structure
VC4a, VC4 b: fourth vertical conductive structure
Detailed Description
As used herein, "about", "approximately", "essentially", or "substantially" includes the stated value and the average value within an acceptable range of deviation of the specified value as determined by one of ordinary skill in the art, taking into account the measurement in question and the specified amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within, for example, ± 30%, ± 20%, ± 15%, ± 10%, ± 5%. Further, as used herein, "about", "approximately", "essentially", or "substantially" may be selected with respect to measured properties, cutting properties, or other properties, to select a more acceptable range of deviation or standard deviation, and not to apply one standard deviation to all properties.
In the drawings, the thickness of layers, films, panels, regions, etc. have been exaggerated for clarity. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connections. Further, "electrically connected" may mean that there are other elements between the two elements.
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Fig. 1 is a schematic cross-sectional view of a display device 10 according to an embodiment of the invention. Fig. 2A to 2E are schematic structural cross-sectional views of the display device 10 of fig. 1 at different stages in the manufacturing process. It should be noted that the manufacturing method of the display device 10 is to finish the circuit element layer 100 and each pixel circuit element layer 200, and then sequentially bond each pixel circuit element layer 200 to the circuit element layer 100 to form the display device 10.
Referring to fig. 1, the display device 10 includes a substrate 50, a circuit element layer 100 and at least one pixel circuit element layer 200. The circuit element layer 100 is disposed on the substrate 50. For example, in the present embodiment, the at least one pixel circuit element layer 200 includes a first pixel circuit element layer 201, a second pixel circuit element layer 202, and a third pixel circuit element layer 203 sequentially stacked on the circuit element layer 100, but the invention is not limited thereto. In some embodiments, a display device may have only one layer of pixel circuit elements 200. In other embodiments, the display device may have two pixel circuit element layers 200. The following description will be made of the formation and bonding flow of the circuit element layer 100 and the first pixel circuit element layer 201 of the display device 10.
Referring to fig. 2A, first, a circuit device layer 100 is formed, wherein the circuit device layer 100 includes a plurality of thin film transistors T and a buffer layer 110. The buffer layer 110 is disposed between the thin film transistor T and the substrate 50. For example, the thin film transistors T of the circuit element layer 100 include a thin film transistor T1, a thin film transistor T2, and a thin film transistor T3, which are sequentially arranged on the buffer layer 110. In the embodiment, the material of the buffer layer 110 may include silicon-doped III-V compound semiconductor, aluminum-doped III-V compound semiconductor, and magnesium-doped III-V compound semiconductor, but the invention is not limited thereto.
The thin film transistor T has a gate G, a source S, a drain D, and a semiconductor pattern SC. The circuit element layer 100 further includes a gate insulating layer 120 disposed between the gate electrode G and the semiconductor pattern SC. For example, in the present embodiment, the gate G of the thin film transistor T may be selectively disposed under the semiconductor pattern SC to form a bottom-gate thin film transistor (bottom-gate TFT), but the invention is not limited thereto. According to other embodiments, the gate electrode G of the thin film transistor T may also be disposed above the semiconductor pattern SC to form a top-gate type thin film transistor (top-gate TFT).
In accordance with the above, the circuit element layer 100 further includes an interlayer insulating layer 130 covering the semiconductor pattern SC of the thin film transistor T. The source S and the drain D of the thin film transistor T are disposed on the interlayer insulating layer 130 and respectively overlap two different regions of the semiconductor pattern SC. Specifically, the source S and the drain D respectively penetrate the interlayer insulating layer 130 to electrically connect the semiconductor patterns SC. In the present embodiment, the material of the semiconductor pattern SC includes a metal oxide semiconductor (metal oxide semiconductor) or an amorphous silicon semiconductor (amorphous silicon semiconductor). That is, the thin film transistor T may be an amorphous silicon thin film transistor (a-Si TFT) or a metal oxide thin film transistor (metal oxide TFT).
In the present embodiment, the gate G, the source S, the drain D, the semiconductor pattern SC, the gate insulating layer 120 and the interlayer insulating layer 130 may be respectively implemented by any semiconductor pattern, any gate insulating layer, any gate, any interlayer insulating layer, any source and any drain of a display device known to those skilled in the art, and the gate G, the source S, the drain D, the semiconductor pattern SC, the gate insulating layer 120 and the interlayer insulating layer 130 may be respectively formed by any method known to those skilled in the art, and thus, no further description is given herein.
The circuit element layer 100 further includes a plurality of signal lines SL. The plurality of signal lines SL include a plurality of first signal lines SL1 and a plurality of second signal lines SL 2. In some embodiments, the first signal lines SL1 and the second signal lines SL2 may be disposed on the substrate 50 in an intersecting manner. In this embodiment, the first signal line SL1 is, for example, a data line (data line), and the second signal line SL2 is, for example, a scan line (scan line). For example, the source S and the gate G of each thin film transistor T (e.g., the thin film transistors T1, T2, T3) may be electrically connected to a corresponding one of the first signal lines SL1 and a corresponding one of the second signal lines SL2, respectively, but the invention is not limited thereto.
At least one of the gate G, the source S and the drain D of the thin film transistor T and the plurality of signal lines SL belong to the same film layer. For example, in the present embodiment, the source S, the drain D and the first signal line SL1 of the thin film transistor T belong to the same layer, and the gate G and the second signal line SL2 of the thin film transistor T belong to the same layer; that is, the source S, the drain D and the first signal line SL1 of the tft T may be formed in the same process using the same mask, and the gate G and the second signal line SL2 of the tft T may be formed in the same process using the same mask. Therefore, the number of the light shield can be reduced, the process procedure can be simplified, and the production cost can be effectively reduced. However, the present invention is not limited thereto, and in some embodiments, the source S, the drain D and the first signal line SL1 of the thin film transistor T belong to the same layer, and the gate G and the second signal line SL2 of the thin film transistor T may be formed on different layers, respectively.
In the present embodiment, the plurality of signal lines SL may further include a plurality of third signal lines SL3, a plurality of fourth signal lines SL4, and a plurality of fifth signal lines SL 5. The third signal line SL3 is, for example, a second scan line (scan line), the fourth signal line SL4 is, for example, a first power line, and is selectively connected to a high voltage level (e.g., Vdd), and the fifth signal line SL5 is, for example, a second power line, and is selectively connected to a reference level (e.g., Vss), but the invention is not limited thereto. In the embodiment, the third signal line SL3 and the second signal line SL2 may belong to the same layer, and the fourth signal line SL4, the fifth signal line SL5 and the first signal line SL1 may belong to the same layer, but the invention is not limited thereto. In some embodiments, the third signal line SL3 and the second signal line SL2 may be formed on different layers, and the fourth signal line SL4, the fifth signal line SL5 and the first signal line SL1 may be formed on different layers.
In light of the above, the circuit device layer 100 further includes a plurality of conductive devices 140 electrically connected to the plurality of signal lines SL. In detail, in the present embodiment, the circuit device layer 100 has two conductive elements 140 disposed on the interlayer insulating layer 130 and penetrating through the interlayer insulating layer 130 and the gate insulating layer 120 respectively to be electrically connected to the second signal line SL2 and the third signal line SL 3. In particular, in the embodiment, the materials of the conductive element 140 and the source S and the drain D of the thin film transistor T may be selectively the same, that is, the conductive element 140 and the source S and the drain D of the thin film transistor T may belong to the same film layer, but the invention is not limited thereto.
The circuit device layer 100 further includes an insulating layer 150 and a plurality of pads 160. The insulating layer 150 covers the source S and the drain D of the thin film transistor T. The pads 160 are disposed on the insulating layer 150 and respectively penetrate through the insulating layer 150 to electrically connect the drains D of the tfts T, the conductive elements 140, the fourth signal line SL4 and the fifth signal line SL 5. For example, in the present embodiment, the top surfaces 160s of the pads 160 may protrude beyond the surface 150s of the insulating layer 150. However, the invention is not limited thereto, and according to other embodiments, the top surfaces 160s of the pads 160 can be substantially aligned with the surface 150s of the insulating layer 150.
In the present embodiment, the material of the insulating layer 150 may be an inorganic material, an organic material, or other suitable materials, wherein the inorganic material is, for example, silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials; the organic material is, for example, polyimide-based resin, epoxy-based resin, acryl-based resin, or other suitable material. In addition, the material of the pad 160 is typically a metal material due to conductivity. However, the invention is not limited thereto, and according to other embodiments, the pads 160 may also be made of other conductive materials, such as: an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or other suitable material, or a stacked layer of a metal material and other conductive materials.
Referring to fig. 2B, a pixel circuit element layer 200 (e.g., a first pixel circuit element layer 201) is formed on the temporary substrate 51, wherein the pixel circuit element layer 200 includes a plurality of pads 260 and a buffer layer 210. The pads 260 include a plurality of first pads 261 disposed on the temporary substrate 51, and the buffer layer 210 covers the plurality of first pads 261 and a portion of the surface of the temporary substrate 51. In the embodiment, the material of the buffer layer 210 may include silicon-doped III-V compound semiconductor, aluminum-doped III-V compound semiconductor, and magnesium-doped III-V compound semiconductor, but the invention is not limited thereto. In addition, the material of the pad 260 is typically a metal material due to conductivity. However, the invention is not limited thereto, and according to other embodiments, the pads 260 may also be made of other conductive materials, such as: an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or other suitable material, or a stacked layer of a metal material and other conductive materials.
In accordance with the above, the pixel circuit element layer 200 further includes a plurality of thin film transistors PT disposed on the buffer layer 210. Each of the thin film transistors PT has a gate electrode PG, a source electrode PS, a drain electrode PD, and a polysilicon semiconductor pattern PSC, that is, the thin film transistor PT is a polysilicon thin film transistor (polysilicon TFT). The pixel circuit element layer 200 further includes a gate insulating layer 220 disposed between the gate electrode PG and the polysilicon semiconductor pattern PSC. For example, in the present embodiment, the gate electrode PG of the thin film transistor PT is disposed above the polysilicon semiconductor pattern PSC to form a top-gate thin film transistor (top-gate TFT), but the present invention is not limited thereto. According to other embodiments, the thin film transistor PT may also be a bottom-gate thin film transistor (bottom-gate TFT).
The pixel circuit element layer 200 further includes an interlayer insulating layer 230 covering the gate electrode PG of the thin film transistor PT and a part of the surface of the gate insulating layer 220. The source and drain electrodes PS and PD of the thin film transistor PT are disposed on the interlayer insulating layer 230 and overlap different two regions of the polysilicon semiconductor pattern PSC, respectively. Specifically, the source and drain electrodes PS and PD penetrate the interlayer insulating layer 230 to electrically connect the polysilicon semiconductor pattern PSC, respectively.
In the present embodiment, the gate PG, the source PS, the drain PD, the polysilicon semiconductor pattern PSC, the gate insulating layer 220 and the interlayer insulating layer 230 may be respectively implemented by any semiconductor pattern, any gate insulating layer, any gate, any interlayer insulating layer, any source and any drain for a display device, which are well known to those skilled in the art, and the gate PG, the source PS, the drain PD, the polysilicon semiconductor pattern PSC, the gate insulating layer 220 and the interlayer insulating layer 230 may be respectively formed by any method known to those skilled in the art, so that no further description is provided herein.
Particularly, since the process temperature of the tft PT is relatively high, the process tolerance and the circuit design margin can be increased by disposing the tfts PT and T on the pixel circuit element layer 200 and the circuit element layer 100, respectively.
The pixel circuit element layer 200 further includes a plurality of first conductive elements 241 and a plurality of second conductive elements 242. For example, the plurality of first conductive elements 241 of the first pixel circuit element layer 201 include a first conductive element 241a, a first conductive element 241b, a first conductive element 241c and a first conductive element 241d, which are disposed on the interlayer insulating layer 230 and respectively penetrate through the interlayer insulating layer 230, the gate insulating layer 220 and the buffer layer 210 to be electrically connected to the corresponding plurality of first pads 261; in particular, the first conductive element 241a is electrically connected between the drain PD of the thin film transistor PT and the corresponding first pad 261, but the invention is not limited thereto.
For example, the plurality of second conductive elements 242 of the first pixel circuit element layer 201 include a second conductive element 242a, a second conductive element 242b and a second conductive element 242c, which are disposed on the gate insulating layer 220 and respectively penetrate through the gate insulating layer 220 and the buffer layer 210 to be electrically connected to the corresponding plurality of first pads 261. In particular, in the embodiment, any one of the plurality of second conductive elements 242 (for example, the second conductive element 242b) may be electrically connected to the gate PG of the tft 1, but the invention is not limited thereto. In the embodiment, the first conductive element 241, the source electrode PS and the drain electrode PD of the thin film transistor PT may belong to the same layer, and the second conductive element 242 and the gate electrode PG of the thin film transistor PT may belong to the same layer, but the invention is not limited thereto.
The pixel circuit element layer 200 further includes an insulating layer 250 covering the plurality of first conductive elements 241, the source PS and drain PD of the thin film transistor PT, and a portion of the surface of the interlayer insulating layer 230. The pads 260 further include second pads 262 disposed on the insulating layer 250. For example, in the present embodiment, the top surfaces 262s of the second pads 262 may protrude from the surface 250s of the insulating layer 250. However, the invention is not limited thereto, and according to other embodiments, the top surfaces 262s of the second pads 262 may be substantially aligned with the surface 250s of the insulating layer 250.
In detail, in the embodiment, the second pads 262 may include a plurality of second pads 262a and a plurality of second pads 262 b. The second pads 262a respectively penetrate through the insulating layer 250 to electrically connect the source PS of the thin film transistor PT, the first conductive element 241b, the first conductive element 241c and the first conductive element 241 d. The second pads 262b respectively penetrate through the insulating layer 250 and the interlayer insulating layer 230 to electrically connect the second conductive elements 242, but the invention is not limited thereto.
It should be noted that fig. 2B only shows the first pixel circuit element layer 201 in the plurality of pixel circuit element layers 200, however, it should be understood by those skilled in the art that the second pixel circuit element layer 202 and the third pixel circuit element layer 203 of the display device 10 of fig. 1 may be formed in the same or similar manner as the first pixel circuit element layer 201, and thus are not described herein again.
Referring to fig. 2C, an adhesive layer 300 is formed on the circuit device layer 100, wherein the adhesive layer 300 covers the pads 160 and a portion of the surface 150s of the insulating layer 150. In the present embodiment, the adhesive layer 300 can be implemented by any adhesive layer for display devices known to those skilled in the art, and the adhesive layer 300 can be formed by any method known to those skilled in the art, so that the description thereof is omitted here.
Referring to fig. 2D, the pixel circuit element layer 200 formed on the temporary substrate 51 is turned over to align with the circuit element layer 100, and after the second pads 262 of the pixel circuit element layer 200 are respectively overlapped with the pads 160 of the circuit element layer 100 in the normal direction n of the substrate 50, the temporary substrate 51 is brought close to the substrate 50, so that the pads 160 of the circuit element layer 100 are respectively contacted with the second pads 262 of the pixel circuit element layer 200.
Referring to fig. 2E, after the pixel circuit element layer 200 is bonded to the circuit element layer 100, the temporary substrate 51 is moved away from the substrate 50, so that the pixel circuit element layer 200 is separated from the temporary substrate 51, wherein the gate PG of the tft PT (e.g., the tft PT1) of the pixel circuit element layer 200 (e.g., the first pixel circuit element layer 201) is selectively disposed between the polysilicon semiconductor patterns PSC of the tfts T (e.g., the tft T1) and PT (e.g., the tft PT 1). However, the present invention is not limited thereto, and in some embodiments, the polysilicon semiconductor pattern PSC of the thin film transistor PT may also be disposed between the thin film transistor T and the gate electrode PG of the thin film transistor PT.
In response, after the pixel circuit element layer 200 (e.g., the first pixel circuit element layer 201) is bonded to the circuit element layer 100, the drain D of the tft T (e.g., the tft T1) is electrically connected to the source PS of the tft PT (e.g., the tft PT 1). It should be noted that fig. 2C to fig. 2E only take the bonding process of the first pixel circuit element layer 201 and the circuit element layer 100 as an example for exemplary illustration, and it should be understood by those skilled in the art that the bonding process of the second pixel circuit element layer 202 and the first pixel circuit element layer 201 and the bonding process of the third pixel circuit element layer 203 and the second pixel circuit element layer 202 in the present embodiment may be performed in the same or similar manner as the bonding process of the first pixel circuit element layer 201 and the circuit element layer 100, and therefore, no further description is given herein.
Particularly, in some embodiments, the adhesive layer 300 is, for example, an Anisotropic Conductive Film (ACF), and the adhesive layer 300 may be disposed between the second pads 262 of the first pixel circuit device layer 210 and the pads 160 of the circuit device layer 100; that is, after the first pixel circuit element layer 210 and the circuit element layer 100 are bonded, the second pads 262 of the first pixel circuit element layer 210 and the pads 160 of the circuit element layer 100, which are structurally separated, may also be electrically connected to each other through the adhesive layer 300 (e.g., anisotropic conductive film ACF).
Referring to fig. 1, the display device 10 may include a plurality of adhesive layers 300. In the present embodiment, the number of the adhesive layers 300 is three, and the adhesive layers are respectively disposed between the circuit device layer 100 and the first pixel circuit device layer 201, between the first pixel circuit device layer 201 and the second pixel circuit device layer 202, and between the second pixel circuit device layer 202 and the third pixel circuit device layer 203, but the number of the adhesive layers 300 is not limited thereto. In some embodiments, the number of adhesive layers 300 may depend on the number of pixel circuit element layers 200 that need to be bonded.
It should be noted that in the present embodiment, the tft PT1 of the first pixel circuit element layer 201, the tft PT2 of the second pixel circuit element layer 202, and the tft PT3 of the third pixel circuit element layer 203 are electrically connected to the tft T1, the tft T2, and the tft T3 of the circuit element layer 100, respectively. In detail, the pad 160 electrically connected to the tft T1 and the second pad 262a electrically connected to the tft PT1 form a first vertical conductive structure VC1a, and the tft T1 of the circuit device layer 100 is electrically connected to the tft PT1 of the first pixel circuit device layer 201 through the first vertical conductive structure VC1 a.
In response to the above, the pad 160 electrically connected to the tft T2, the first conductive element 241b of the first pixel circuit element layer 201, the electrically connected pad 260 (the first pad 261 and the second pad 262a) thereof, and the second pad 262a electrically connected to the tft PT2 may form the first vertical conductive structure VC1b, and the tft T2 of the circuit element layer 100 is electrically connected to the tft PT2 of the second pixel circuit element layer 202 through the first vertical conductive structure VC1 b. In addition, the pad 160 electrically connected to the thin film transistor T3, the first conductive element 241c of the first pixel circuit element layer 201 and the electrically connected pad 260 (the first pad 261 and the second pad 262a), the first conductive element 241b of the second pixel circuit element layer 202 and the electrically connected pad (the first pad 261 and the second pad 262a) thereof, and the second pad 262a electrically connected to the thin film transistor PT3 may form a first vertical conductive structure VC1c, and the thin film transistor T3 of the circuit element layer 100 is electrically connected to the thin film transistor PT3 of the third pixel circuit element layer 203 through the first vertical conductive structure VC1 c.
Particularly, in the present embodiment, the thin film transistor T1, the thin film transistor T2, and the thin film transistor T3 of the circuit element layer 100 are electrically connected to the thin film transistor PT1 of the first pixel circuit element layer 201, the thin film transistor PT2 of the second pixel circuit element layer 202, and the thin film transistor PT3 of the third pixel circuit element layer 203, respectively, so that leakage currents (leakage currents) generated by the thin film transistors PT1, PT2, and PT3 can be effectively reduced, thereby improving the display quality.
The display device 10 further includes a display element layer 400 disposed on the third pixel circuit element layer 203. In this embodiment, the display element layer 400 is formed after the bonding process of the circuit element layer 100 and the pixel circuit element layers 200. However, the present invention is not limited thereto, and the display element layer 400 may be formed in the manufacturing flow of the third pixel circuit element layer 203 according to other embodiments.
The display element layer 400 includes a plurality of first electrodes 410. In the present embodiment, the plurality of first electrodes 410 may include a first electrode 411, a first electrode 412 and a first electrode 413, which are disposed on the buffer layer 210 of the third pixel circuit element layer 203 and respectively penetrate through the gate insulating layer 220 and the interlayer insulating layer 230 of the third pixel circuit element layer 203 to electrically connect the plurality of first conductive elements 241A of the third pixel circuit element layer 203. In detail, in the present embodiment, the plurality of first conductive elements 241A of the third pixel circuit element layer 203 include a first conductive element 241e, a first conductive element 241f, and a first conductive element 241g, and the first electrode 411, the first electrode 412, and the first electrode 413 are electrically connected to the first conductive element 241e, the first conductive element 241f, and the first conductive element 241g, respectively, but the invention is not limited thereto.
In the present embodiment, the first electrode 411 is electrically connected to the tft PT1 of the first pixel circuit element layer 201, the first electrode 412 is electrically connected to the tft PT2 of the second pixel circuit element layer 202, and the first electrode 413 is electrically connected to the tft PT3 of the third pixel circuit element layer 203, but the invention is not limited thereto. In detail, the first conductive element 241a of the first pixel circuit element layer 201 and the electrically connected first pad 261 thereof, the first conductive element 241c of the second pixel circuit element layer 202 and the electrically connected pad 260 thereof (the first pad 261 and the second pad 262a), and the first conductive element 241e of the third pixel circuit element layer 203 and the electrically connected second pad 262a thereof may form a second vertical conductive structure VC2a, and the first electrode 411 of the display element layer 400 is electrically connected to the thin film transistor PT1 of the first pixel circuit element layer 201 through the second vertical conductive structure VC2 a.
In connection with the above, the first conductive element 241a of the second pixel circuit element layer 202 and the electrically connected first pad 261 thereof, the first conductive element 241f of the third pixel circuit element layer 203 and the electrically connected second pad 262a thereof may form a second vertical conductive structure VC2b, and the first electrode 412 of the display element layer 400 is electrically connected to the tft PT2 of the second pixel circuit element layer 202 through the second vertical conductive structure VC2 b. The first electrode 413 of the display device layer 400 is electrically connected to the tft PT3 of the third pixel circuit device layer 203 through the first conductive element 241 g.
In this embodiment, the display element layer 400 further includes a pixel defining layer 420 covering a portion of the surface of the buffer layer 210 of the third pixel circuit element layer 203 and having a plurality of openings 421 overlapping the plurality of first electrodes 410. In the embodiment, the pixel defining layer 420 may selectively cover a portion of the surface of the first electrode 410, that is, a vertical projection of the opening 421 of the pixel defining layer 420 on the substrate 50 is located within a vertical projection of the first electrode 410 on the substrate 50, but the invention is not limited thereto.
The display element layer 400 further includes a display medium 430 and a second electrode 440. In the present embodiment, the display medium 430 is disposed in the opening 421 of the pixel defining layer 420, and the material of the display medium 430 is, for example, a light emitting material. The light-emitting material includes organic electroluminescent material, fluorescent organic electroluminescent material, inorganic electroluminescent material or a combination of at least two of the above materials, but the invention is not limited thereto. The second electrode 440 covers the pixel defining layer 420 and fills the plurality of openings 421 of the pixel defining layer 420 to cover the display medium 430. The display element layer 400 may further include an encapsulation layer 450 covering the second electrode 440. In the present embodiment, the material of the encapsulation layer 450 may include silicon nitride, aluminum oxide, aluminum carbonitride, silicon oxynitride, acryl resin, Hexamethyldisiloxane (HMDSO), or glass.
On the other hand, in the present embodiment, the plurality of second conductive elements 242A of the third pixel circuit element layer 203 includes a second conductive element 242d and a second conductive element 242e, and the second conductive element 242d and the second conductive element 242e are electrically connected to the second signal line SL2 and the third signal line SL3 of the circuit element layer 100, respectively. In detail, the conductive element 140 of the circuit device layer 100 and the pad 160 electrically connected thereto, the second conductive element 242A of the first pixel circuit device layer 201 and the pad 260 electrically connected thereto (the first pad 261 and the second pad 262b), the second conductive element 242A of the second pixel circuit device layer 202 and the pad 260 electrically connected thereto (the first pad 261 and the second pad 262b), and the second pad 262b of the third pixel circuit device layer 203 may form a third vertical conductive structure VC 3.
To receive the above, the second signal line SL2 and the third signal line SL3 of the circuit device layer 100 are electrically connected to the second conductive element 242d and the second conductive element 242e of the third pixel circuit device layer 203 through two third vertical conductive structures VC3, respectively. In some embodiments, the third signal line SL3 is, for example, a scan line (scan line), and a scan start signal is transmitted among the first pixel circuit element layer 201, the second pixel circuit element layer 202, and the third pixel circuit element layer 203 through the third vertical conductive structure VC3 to drive the thin film transistor PT1, the thin film transistor PT2, and the thin film transistor PT3, respectively.
In the present embodiment, the pad 160 electrically connected to the fourth signal line SL4, the first conductive element 241d of the first pixel circuit element layer 201 and the pad 260 (the first pad 261 and the second pad 262a) electrically connected thereto, the first conductive element 241d of the second pixel circuit element layer 202 and the pad 260 (the first pad 261 and the second pad 262a) electrically connected thereto, and the second pad 262a electrically connected to the first conductive element 241h may form a fourth vertical conductive structure VC4a, and the fourth signal line SL4 is electrically connected to the first conductive element 241h of the third pixel circuit element layer 203 through the fourth vertical conductive structure VC4 a.
In addition, the pad 160 electrically connected to the fifth signal line SL5, the second conductive element 242a of the first pixel circuit element layer 201 and the pad 260 (the first pad 261 and the second pad 262b) electrically connected thereto, the second conductive element 242a of the second pixel circuit element layer 202 and the pad 260 (the first pad 261 and the second pad 262b) electrically connected thereto, and the second pad 262a electrically connected to the first conductive element 241i may form a fourth vertical conductive structure VC4b, and the fifth signal line SL5 is electrically connected to the first conductive element 241i of the third pixel circuit element layer 203 through the fourth vertical conductive structure VC4 b.
In some embodiments, the fourth signal line SL4 and the fifth signal line SL5 are power lines, for example, the fourth signal line SL4 may be connected to a high voltage level (e.g., Vdd), and the fifth signal line SL5 may be connected to a reference level (e.g., Vss). That is, the fourth signal line SL4 may transmit a high voltage signal to the first conductive element 241h of the third pixel circuit element layer 203 through the fourth vertical conductive structure VC4a to provide a high voltage source required for the pixel driving circuit, and the fifth signal line SL5 may transmit a reference signal to the first conductive element 241i of the third pixel circuit element layer 203 through the fourth vertical conductive structure VC4b to provide a reference signal required for the pixel driving circuit.
In summary, in the display device according to the embodiments of the invention, the polysilicon thin film transistor and the thin film transistor having the metal oxide semiconductor or the amorphous silicon semiconductor are respectively disposed on the pixel circuit element layer and the circuit element layer which are bonded to each other by the adhesive layer, so that the process tolerance and the design margin of the circuit can be increased. In addition, at least one of the source electrode, the drain electrode and the grid electrode of the thin film transistor and the plurality of signal lines are the same film layer, so that the number of photomasks can be reduced, the processing procedure can be simplified, and the production cost can be effectively reduced. In addition, the polycrystalline silicon thin film transistor is electrically connected with the thin film transistor with the metal oxide semiconductor or the amorphous silicon semiconductor, so that leakage current (leakage current) generated by the polycrystalline silicon thin film transistor can be effectively reduced, and the display quality is improved.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (11)
1. A display device, comprising:
a substrate;
a first device layer disposed on the substrate, the first device layer comprising:
a plurality of signal lines; and
a first thin film transistor having a first gate, a first source, a first drain and a first semiconductor pattern;
a second component layer disposed on the first component layer, the second component layer comprising:
a second thin film transistor electrically connected to the first thin film transistor and having a second gate, a second source, a second drain and a first polysilicon semiconductor pattern;
a first adhesive layer disposed between the first device layer and the second device layer; and
a display element layer disposed on the second element layer, the display element layer including a first electrode electrically connected to the second TFT,
at least one of the first gate, the first source and the first drain and the signal line belong to the same film layer, and the material of the first semiconductor pattern includes a metal oxide semiconductor or an amorphous silicon semiconductor.
2. The display device according to claim 1, wherein the first drain of the first thin film transistor is electrically connected to the second source of the second thin film transistor.
3. The display device according to claim 1, wherein the second gate of the second thin film transistor is disposed between the first polysilicon semiconductor pattern of the first thin film transistor and the second thin film transistor.
4. The display device of claim 1, wherein the first element layer further comprises:
a third thin film transistor having a third gate, a third source, a third drain and a second semiconductor pattern,
at least one of the third gate, the third source and the third drain and the signal line belong to the same film layer, and the material of the second semiconductor pattern includes a metal oxide semiconductor or an amorphous silicon semiconductor.
5. The display device of claim 4, further comprising:
a third element layer disposed between the second element layer and the display element layer, the third element layer comprising:
a fourth thin film transistor having a fourth gate, a fourth source, a fourth drain and a second polysilicon semiconductor pattern; and
a second adhesive layer disposed between the second device layer and the third device layer,
the third drain of the third thin film transistor is electrically connected to the fourth source of the fourth thin film transistor.
6. The display device according to claim 5, wherein the fourth gate of the fourth TFT is disposed between the second polysilicon semiconductor pattern of the third TFT and the fourth TFT.
7. The display device of claim 5, wherein the second device layer further comprises a first conductive element electrically connected between the third drain of the third TFT and the fourth source of the fourth TFT.
8. The display device of claim 5, wherein the first element layer further comprises:
a fifth thin film transistor having a fifth gate, a fifth source, a fifth drain and a third semiconductor pattern,
at least one of the fifth gate, the fifth source and the fifth drain and the signal line belong to the same film layer, and the third semiconductor pattern is made of a metal oxide semiconductor or an amorphous silicon semiconductor.
9. The display device of claim 8, further comprising:
a fourth element layer disposed between the third element layer and the display element layer, the fourth element layer comprising:
a sixth thin film transistor having a sixth gate, a sixth source, a sixth drain and a third polysilicon semiconductor pattern; and
a third adhesive layer disposed between the third device layer and the fourth device layer,
the fifth drain of the fifth thin film transistor is electrically connected to the sixth source of the sixth thin film transistor.
10. The display device according to claim 9, wherein the sixth gate of the sixth tft is disposed between the fifth tft and the third polysilicon semiconductor pattern of the sixth tft.
11. The display device of claim 9, wherein the second device layer further comprises a first conductive element electrically connected to the fifth drain of the fifth tft, and the third device layer further comprises a second conductive element electrically connected between the first conductive element and the sixth source of the sixth tft.
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| CN105355634B (en) * | 2015-11-20 | 2019-11-15 | 深圳市华星光电技术有限公司 | Thin-film transistor display panel and preparation method thereof |
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| KR102458660B1 (en) * | 2016-08-03 | 2022-10-26 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Display device and electronic device |
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