TWI677741B - Display apparatus - Google Patents

Abstract

A display device includes a substrate, a first element layer, a second element layer, a first adhesive layer, and a display element layer. The first element layer, the first adhesive layer, the second element layer, and the display element layer are sequentially stacked on the substrate. The first element layer includes a plurality of signal lines and a first thin film transistor. The first thin film transistor has a first gate, a first source, a first drain, and a first semiconductor pattern. The second element layer includes a second thin film transistor electrically connected to the first thin film transistor. The second thin film transistor has a first polycrystalline silicon semiconductor pattern. At least one of the first gate electrode, the first source electrode, and the first drain electrode belongs to the same film layer as the plurality of signal lines. The material of the first semiconductor pattern includes a metal oxide semiconductor or an amorphous silicon semiconductor.

Description

Display device

The present invention relates to a display device, and more particularly, to a high-resolution display device.

With the development of the technology industry, display devices such as mobile phones, tablet computers, or eBooks have been widely used in daily life. Especially in recent years, with the emergence of multimedia applications such as stereoscopic display and virtual reality, in order to provide stunning visual effects, the demand for ultra-high-resolution display panels has gradually increased.

With the continuous improvement of the display panel resolution, designing the driving circuit under the pixel structure in a stacked structure to solve the lack of layout space of the driving circuit is one of the current solutions. However, the use of stacked architectures will inevitably increase the complexity and production costs of the process. Therefore, in the design of the driving circuit using a stacked structure, how to simplify the process and reduce the production cost is an important issue.

The present invention provides a display device with cost advantages and good electrical properties.

The display device of the present invention includes a substrate, a first element layer, a second element layer, a first adhesive layer, and a display element layer. The first element layer is disposed on a substrate. The first element layer includes a plurality of signal lines and a first thin film transistor. The first thin film transistor has a first gate, a first source, a first drain, and a first semiconductor pattern. The second element layer is disposed on the first element layer. The second element layer includes a second thin film transistor and is electrically connected to the first thin film transistor. The second thin film transistor has a second gate, a second source, a second drain, and a first polycrystalline silicon semiconductor pattern. The first adhesive layer is disposed between the first element layer and the second element layer. The display element layer is disposed on the second element layer. The display element layer includes a first electrode and is electrically connected to the second thin film transistor. At least one of the first gate electrode, the first source electrode, and the first drain electrode belongs to the same film layer as the plurality of signal lines. The material of the first semiconductor pattern includes a metal oxide semiconductor or an amorphous silicon semiconductor.

In an embodiment of the present invention, the first drain electrode of the first thin film transistor and the second source electrode of the second thin film transistor of the display device are electrically connected.

In an embodiment of the present invention, the second gate of the second thin film transistor of the display device is disposed between the first thin film transistor and the first polycrystalline silicon semiconductor pattern of the second thin film transistor.

In an embodiment of the present invention, the first element layer of the display device further includes a third thin film transistor having a third gate, a third source, a third drain, and a second semiconductor pattern. At least one of the third gate, the third source, and the third drain belongs to the same film layer as the plurality of signal lines. The material of the second semiconductor pattern includes a metal oxide semiconductor or an amorphous silicon semiconductor.

In an embodiment of the present invention, the display device further includes a third element layer and a second adhesive layer. The third element layer is disposed between the second element layer and the display element layer. The second adhesive layer is disposed between the second element layer and the third element layer. The third element layer includes a fourth thin film transistor. The fourth thin film transistor has a fourth gate, a fourth source, a fourth drain, and a second polycrystalline silicon semiconductor pattern. The third drain electrode of the third thin film transistor is electrically connected to the fourth source of the fourth thin film transistor.

In an embodiment of the present invention, the fourth gate of the fourth thin film transistor of the display device is disposed between the third thin film transistor and the second polycrystalline silicon semiconductor pattern of the fourth thin film transistor.

In an embodiment of the present invention, the second element layer of the display device further includes a first conductive element, and the first conductive element is electrically connected to the third drain electrode of the third thin film transistor and the fourth thin film transistor. Between the fourth source.

In an embodiment of the present invention, the first element layer of the display device further includes a fifth thin film transistor. The fifth thin film transistor has a fifth gate, a fifth source, a fifth drain, and a third semiconductor pattern. At least one of the fifth gate, the fifth source, and the fifth drain belongs to the same film layer as the plurality of signal lines. The material of the third semiconductor pattern includes a metal oxide semiconductor or an amorphous silicon semiconductor.

In an embodiment of the present invention, the display device further includes a fourth element layer and a third adhesive layer. The fourth element layer is disposed between the third element layer and the display element layer. The third adhesive layer is disposed between the third element layer and the fourth element layer. The fourth element layer includes a sixth thin film transistor. The sixth thin film transistor has a sixth gate, a sixth source, a sixth drain, and a third polycrystalline silicon semiconductor pattern. The fifth drain of the fifth thin film transistor is electrically connected to the sixth source of the sixth thin film transistor.

In an embodiment of the present invention, the sixth gate of the sixth thin film transistor of the display device is disposed between the fifth thin film transistor and the third polycrystalline silicon semiconductor pattern of the sixth thin film transistor.

In an embodiment of the present invention, the second element layer of the display device further includes a first conductive element. The first conductive element is electrically connected to the fifth drain of the fifth thin film transistor. The third element layer further includes a second conductive element. The second conductive element is electrically connected between the first conductive element and the sixth source of the sixth thin film transistor.

Based on the above, the display device of the embodiment of the present invention is configured to pass through the polycrystalline silicon thin film transistor and the thin film transistor having a metal oxide semiconductor or an amorphous silicon semiconductor to a pixel circuit element layer and a circuit element that are bonded to each other with an adhesive layer Layer, which can increase process tolerance and circuit design margin. In addition, at least one of the source electrode, the drain electrode, and the gate electrode of the thin film transistor and the plurality of signal lines are in the same film layer, which can reduce the number of photomasks and simplify the manufacturing process to effectively reduce the production cost. In addition, by electrically connecting the polycrystalline silicon thin film transistor with a thin film transistor having a metal oxide semiconductor or an amorphous silicon semiconductor, the leakage current generated by the polycrystalline silicon thin film transistor can be effectively reduced to improve display quality.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

As used herein, "about," "approximately," "essentially," or "substantially" includes the stated value and an average value within an acceptable deviation range of a particular value determined by one of ordinary skill in the art, taking into account the The measurement in question and the specific number of measurement-related errors (ie, limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the stated value, or for example within ± 30%, ± 20%, ± 15%, ± 10%, ± 5%. Furthermore, the terms "about", "approximately", "essentially", or "substantially" used herein may be based on measurement properties, cutting properties, or other properties to select a more acceptable range of deviations or standard deviations. Not all standard properties apply.

In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and / or electrical connection. Furthermore, "electrically connected" may mean that there are other components between the two components.

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

FIG. 1 is a schematic cross-sectional view of a display device 10 according to an embodiment of the present invention. 2A to 2E are schematic structural cross-sectional views of the display device 10 of FIG. 1 at different stages in the manufacturing process. It is worth mentioning that the manufacturing method of the display device 10 is to separately complete the circuit element layer 100 and each pixel circuit element layer 200, and then sequentially bond each pixel circuit element layer 200 to the circuit element layer 100. To form a display device 10.

Referring to FIG. 1, the display device 10 includes a substrate 50, a circuit element layer 100 and at least one pixel circuit element layer 200. The circuit element layer 100 is provided on a substrate 50. For example, in this embodiment, the at least one pixel circuit element layer 200 includes a first pixel circuit element layer 201, a second pixel circuit element layer 202, and a second pixel circuit element layer 202, which are sequentially stacked on the circuit element layer 100. The third pixel circuit element layer 203, but the invention is not limited thereto. In some embodiments, the display device may have only one pixel circuit element layer 200. In other embodiments, the display device may have two pixel circuit element layers 200. The formation and bonding processes of the circuit element layer 100 and the first pixel circuit element layer 201 of the display device 10 will be described below.

Please refer to FIG. 2A. First, a circuit element layer 100 is formed. The circuit element layer 100 includes a plurality of thin film transistors T and a buffer layer 110. The buffer layer 110 is provided between the thin film transistor T and the substrate 50. For example, the plurality of thin film transistors T of the circuit element layer 100 includes a thin film transistor T1, a thin film transistor T2, and a thin film transistor T3, which are sequentially arranged on the buffer layer 110. In this embodiment, the material of the buffer layer 110 may include a silicon-doped III-V compound semiconductor, an aluminum-doped III-V compound semiconductor, and a magnesium-doped III-V compound semiconductor, but the present invention does not This is the limit.

The thin film transistor T includes a gate G, a source S, a drain D, and a semiconductor pattern SC. The circuit element layer 100 further includes a gate insulating layer 120 disposed between the gate G and the semiconductor pattern SC. For example, in this embodiment, the gate electrode G of the thin film transistor T may be selectively disposed below the semiconductor pattern SC to form a bottom gate type thin film transistor (bottom-gate TFT), but the present invention does not This is the limit. According to other embodiments, the gate G of the thin film transistor T may be disposed above the semiconductor pattern SC to form a top-gate thin film transistor (top-gate TFT).

Following the above, the circuit element layer 100 further includes an interlayer insulating layer 130 covering the semiconductor pattern SC of the thin film transistor T. The source S and the drain D of the thin film transistor T are disposed on the interlayer insulating layer 130 and overlap the two different regions of the semiconductor pattern SC, respectively. Specifically, the source S and the drain D respectively penetrate the interlayer insulating layer 130 to electrically connect the semiconductor pattern SC. In this embodiment, a material of the semiconductor pattern SC includes a metal oxide semiconductor (a metal oxide semiconductor) or an amorphous silicon semiconductor (amorphous silicon semiconductor). That is, the thin film transistor T may be an amorphous silicon thin film transistor (a-Si TFT) or a metal oxide thin film transistor (metal oxide TFT).

In this embodiment, the gate G, the source S, the drain D, the semiconductor pattern SC, the gate insulating layer 120, and the interlayer insulating layer 130 may be used for display devices known to those having ordinary knowledge in the technical field. Any semiconductor pattern, any gate insulation layer, any gate electrode, any interlayer insulation layer, any source electrode, and any drain electrode are implemented, and the gate electrode G, the source electrode S, the drain electrode D, and the semiconductor pattern SC The gate insulation layer 120 and the interlayer insulation layer 130 may be formed by any method well known to those having ordinary knowledge in the technical field, so they are not described herein.

The circuit element layer 100 further includes a plurality of signal lines SL. The plurality of signal lines SL include a plurality of first signal lines SL1 and a plurality of second signal lines SL2. In some embodiments, a plurality of first signal lines SL1 and a plurality of second signal lines SL2 may be disposed on the substrate 50 in an intersecting manner. In this embodiment, the first signal line SL1 is, for example, a data line, and the second signal line SL2 is, for example, a first scan line. For example, the source S and the gate G of each thin film transistor T (for example, thin film transistors T1, T2, and T3) can be electrically connected to a corresponding first signal line SL1 and a corresponding second signal, respectively. Line SL2, but the invention is not limited to this.

Following the above, at least one of the gate G, the source S, and the drain D of the thin film transistor T belongs to the same film layer as the plurality of signal lines SL. For example, in this embodiment, the source S, the drain D, and the first signal line SL1 of the thin film transistor T belong to the same film layer, and the gate G and the second signal line SL2 of the thin film transistor T belong to the same film That is, the source S, the drain D, and the first signal line SL1 of the thin film transistor T can be formed in the same process using the same mask, and the gate G and the second signal line SL2 of the thin film transistor T can be formed in the same process. Formed in the same process using the same mask. In this way, the number of photomasks can be reduced and the manufacturing process can be simplified to effectively reduce production costs. However, the present invention is not limited thereto. In some embodiments, the source S, the drain D, and the first signal line SL1 of the thin film transistor T belong to the same film layer, and the gate G of the thin film transistor T and the first signal line SL1 are in the same film layer. The two signal lines SL2 can be formed in different film layers, respectively.

In this embodiment, the plurality of signal lines SL may further include a plurality of third signal lines SL3, a plurality of fourth signal lines SL4, and a plurality of fifth signal lines SL5. The third signal line SL3 is, for example, a second scan line, the fourth signal line SL4 is, for example, a first power line, and can be selectively connected to a high voltage level (such as Vdd), and the fifth signal line SL5 is, for example, It is a second power line and can be selectively connected to a reference level (such as Vss), but the invention is not limited thereto. In this embodiment, the third signal line SL3 and the second signal line SL2 may selectively belong to the same film layer, and the fourth signal line SL4, the fifth signal line SL5, and the first signal line SL1 may selectively belong to the same film. Layer, but the invention is not limited to this. In some embodiments, the third signal line SL3 and the second signal line SL2 may be formed in different film layers, and the fourth signal line SL4, the fifth signal line SL5, and the first signal line SL1 may be formed in different film layers, respectively.

Following the above, the circuit element layer 100 further includes a plurality of conductive elements 140 electrically connected to the plurality of signal lines SL. In detail, in this embodiment, the circuit element layer 100 has two conductive elements 140 disposed on the interlayer insulating layer 130 and penetrating the interlayer insulating layer 130 and the gate insulating layer 120 respectively, and is electrically connected to the second signal. Line SL2 and the third signal line SL3. In particular, in this embodiment, the materials of the source S and the drain D of the conductive element 140 and the thin-film transistor T may be selectively the same, that is, the source S and the source S of the conductive element 140 and the thin-film transistor T are The drain electrodes D may belong to the same film layer, but the invention is not limited thereto.

The circuit element layer 100 further includes an insulating layer 150 and a plurality of pads 160. The insulating layer 150 covers the source S and the drain D of the thin film transistor T. A plurality of pads 160 are disposed on the insulation layer 150 and penetrate the insulation layer 150 to electrically connect the drain electrodes D of the thin film transistors T, the plurality of conductive elements 140, the fourth signal line SL4, and the fifth signal line SL5. . For example, in this embodiment, the top surfaces 160 s of the plurality of pads 160 may protrude from the surface 150 s of the insulating layer 150. However, the present invention is not limited to this. According to other embodiments, the top surface 160s of the plurality of pads 160 can substantially cut the surface 150s of the insulation layer 150.

In this embodiment, the material of the insulating layer 150 may be an inorganic material, an organic material, or other suitable materials, wherein the inorganic material is, for example, silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials; organic materials such as Polyimide resin, epoxy resin, acrylic resin, or other suitable materials. In addition, based on electrical conductivity considerations, the material of the pad 160 is generally a metal material. However, the present invention is not limited to this. According to other embodiments, the pad 160 may also use other conductive materials, such as alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or other suitable Materials, or stacked layers of metal materials and other conductive materials.

Referring to FIG. 2B, a pixel circuit element layer 200 (eg, a first pixel circuit element layer 201) is formed on the temporary substrate 51. The pixel circuit element layer 200 includes a plurality of pads 260 and a buffer layer 210. The plurality of contact pads 260 include a plurality of first contact pads 261 disposed on the temporary substrate 51, and the buffer layer 210 covers a portion of the surfaces of the plurality of first contact pads 261 and the temporary substrate 51. In this embodiment, the material of the buffer layer 210 may include a silicon-doped III-V compound semiconductor, an aluminum-doped III-V compound semiconductor, and a magnesium-doped III-V compound semiconductor, but the present invention does not This is the limit. In addition, based on considerations of electrical conductivity, the material of the pad 260 is generally a metal material. However, the present invention is not limited to this. According to other embodiments, the pad 260 may also use other conductive materials, such as: alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or other suitable materials. Materials, or stacked layers of metal materials and other conductive materials.

Following the above, the pixel circuit element layer 200 further includes a plurality of thin film transistors PT disposed on the buffer layer 210. Each thin film transistor PT has a gate PG, a source PS, a drain PD, and a polycrystalline silicon semiconductor pattern PSC. That is, the thin film transistor PT is a polycrystalline silicon TFT. The pixel circuit element layer 200 further includes a gate insulating layer 220 disposed between the gate PG and the polycrystalline silicon semiconductor pattern PSC. For example, in this embodiment, the gate PG of the thin film transistor PT is disposed above the polycrystalline silicon semiconductor pattern PSC to form a top-gate thin film transistor (top-gate TFT). Limited. According to other embodiments, the thin film transistor PT may be a bottom-gate thin film transistor (bottom-gate TFT).

The pixel circuit element layer 200 further includes an interlayer insulating layer 230 covering a part of the surface of the gate electrode PG and the gate insulating layer 220 of the thin film transistor PT. The source PS and the drain PD of the thin-film transistor PT are disposed on the interlayer insulating layer 230 and are respectively overlapped in two different regions of the polycrystalline silicon semiconductor pattern PSC. Specifically, the source PS and the drain PD respectively penetrate the interlayer insulating layer 230 to electrically connect the polycrystalline silicon semiconductor pattern PSC.

In this embodiment, the gate PG, the source PS, the drain PD, the polycrystalline silicon semiconductor pattern PSC, the gate insulating layer 220, and the interlayer insulating layer 230 may be used for display devices known to those having ordinary knowledge in the art. To achieve any semiconductor pattern, any gate insulation layer, any gate electrode, any interlayer insulation layer, any source electrode, and any drain electrode, and the gate PG, source PS, drain PD, polycrystalline silicon semiconductor The pattern PSC, the gate insulation layer 220, and the interlayer insulation layer 230 may be formed by any method well known to those having ordinary knowledge in the technical field, and therefore are not described herein.

In particular, because the thin-film transistor PT has a high process temperature, the thin-film transistor PT and the thin-film transistor T are separately disposed at the pixel circuit element layer 200 and the circuit element layer 100, which can increase the process tolerance and the circuit Design margin.

The pixel circuit element layer 200 further includes a plurality of first conductive elements 241 and a plurality of second conductive elements 242. For example, the plurality of first conductive elements 241 of the first pixel circuit element layer 201 include a first conductive element 241a, a first conductive element 241b, a first conductive element 241c, and a first conductive element 241d, and are disposed on the interlayer insulating layer 230, and penetrates the interlayer insulation layer 230, the gate insulation layer 220, and the buffer layer 210, respectively, to be electrically connected to the corresponding first pads 261; in particular, the first conductive element 241a is electrically connected to the thin film transistor Between the drain PD of the PT and the corresponding first pad 261, but the present invention is not limited thereto.

For example, the plurality of second conductive elements 242 of the first pixel circuit element layer 201 include a second conductive element 242a, a second conductive element 242b, and a second conductive element 242c. The gate insulation layer 220 and the buffer layer 210 are electrically connected to a corresponding plurality of first pads 261. In particular, in this embodiment, any one of the plurality of second conductive elements 242 (for example, the second conductive element 242b) may be electrically connected to the gate electrode PG of the thin film transistor PT1, but the present invention does not use this. Limited. In this embodiment, the source PS and the drain PD of the first conductive element 241 and the thin-film transistor PT may belong to the same film layer, and the gate electrode PG of the second conductive element 242 and the thin-film transistor PT may belong to the same film layer. However, the present invention is not limited to this.

The pixel circuit element layer 200 further includes an insulating layer 250 covering a portion of the surfaces of the plurality of first conductive elements 241, the source PS and the drain PD of the thin film transistor PT, and the interlayer insulating layer 230. The plurality of pads 260 further include a plurality of second pads 262 disposed on the insulating layer 250. For example, in this embodiment, the top surfaces 262s of the plurality of second pads 262 may protrude from the surface 250s of the insulating layer 250. However, the present invention is not limited thereto. According to other embodiments, the top surfaces 262s of the plurality of second pads 262 may substantially cut the surface 250s of the insulating layer 250.

In detail, in this embodiment, the plurality of second pads 262 may include a plurality of second pads 262a and a plurality of second pads 262b. The plurality of second pads 262a respectively penetrate the insulating layer 250 to electrically connect the source PS of the thin film transistor PT, the first conductive element 241b, the first conductive element 241c, and the first conductive element 241d. The plurality of second pads 262b penetrate the insulating layer 250 and the interlayer insulating layer 230 respectively to electrically connect the plurality of second conductive elements 242, but the invention is not limited thereto.

It should be noted that FIG. 2B only shows the first pixel circuit element layer 201 among the plurality of pixel circuit element layers 200. However, those with ordinary knowledge in the technical field to which the present invention should understand should understand that FIG. 1 The second pixel circuit element layer 202 and the third pixel circuit element layer 203 of the display device 10 can be formed the same or similar to the implementation mode and manufacturing method of the first pixel circuit element layer 201, so they are not added here. To repeat.

Please refer to FIG. 2C. Next, an adhesive layer 300 is formed on the circuit element layer 100. The adhesive layer 300 covers a plurality of pads 160 and a portion of the surface 150s of the insulating layer 150. In this embodiment, the adhesive layer 300 may be implemented by any adhesive layer for display devices known to those having ordinary knowledge in the technical field, and the adhesive layer 300 may be realized by any person having ordinary knowledge in the technical field. Any well-known method is used to form it, so it will not be repeated here.

Please refer to FIG. 2D. Next, the pixel circuit element layer 200 formed on the temporary substrate 51 is inverted, and aligned with the circuit element layer 100. A plurality of second connection of the pixel circuit element layer 200 is to be performed. After the pad 262 overlaps the plurality of pads 160 of the circuit element layer 100 in the normal direction n of the substrate 50, the temporary substrate 51 is brought close to the substrate 50, so that the plurality of pads 160 of the circuit element layer 100 and the pixels are respectively The plurality of second pads 262 of the circuit element layer 200 are in contact with each other.

Please refer to FIG. 2E. After the pixel circuit element layer 200 and the circuit element layer 100 are bonded, the temporary substrate 51 is kept away from the substrate 50, and the pixel circuit element layer 200 is separated from the temporary substrate 51. The pixel circuit element layer 200 (for example, the first A gate electrode PG of a thin film transistor PT (eg, thin film transistor PT1) of one pixel circuit element layer 201) may be selectively disposed between the thin film transistor T (eg, thin film transistor T1) and the thin film transistor PT (eg, thin film transistor PT1). Crystal PT1) between polycrystalline silicon semiconductor patterns PSC. However, the present invention is not limited thereto. In some embodiments, the polycrystalline silicon semiconductor pattern PSC of the thin film transistor PT may also be disposed between the thin film transistor T and the gate PG of the thin film transistor PT.

Following the above, after the pixel circuit element layer 200 (eg, the first pixel circuit element layer 201) is bonded to the circuit element layer 100, the drain D of the thin film transistor T (eg, the thin film transistor T1) and the thin film transistor PT ( For example, the source PS of the thin film transistor PT1) is electrically connected. It should be noted that FIG. 2C to FIG. 2E are only exemplified by taking the bonding process of the first pixel circuit element layer 201 and the circuit element layer 100 as an example. Those skilled in the art to which this invention belongs should understand Yes, the bonding process of the second pixel circuit element layer 202 and the first pixel circuit element layer 201 and the bonding process of the third pixel circuit element layer 203 and the second pixel circuit element layer 202 in this embodiment may be the same Or similar to the bonding method of the first pixel circuit element layer 201 and the circuit element layer 100, it will not be described in detail here.

It is particularly mentioned that in some embodiments, the adhesive layer 300 is, for example, an anisotropic conductive film (ACF), and the adhesive layer 300 may be disposed on the second contact of the first pixel circuit element layer 210. Between the pad 262 and the connection pad 160 of the circuit element layer 100; that is, after the first pixel circuit element layer 210 is bonded to the circuit element layer 100, the second pixel of the first pixel circuit element layer 210 that is structurally separated The pad 262 and the pad 160 of the circuit element layer 100 can also be electrically connected to each other through the adhesive layer 300 (for example, the anisotropic conductive adhesive film ACF).

Referring to FIG. 1, the display device 10 may include a plurality of adhesive layers 300. In this embodiment, the number of the adhesive layers 300 is three, and is disposed between the circuit element layer 100 and the first pixel circuit element layer 201, the first pixel circuit element layer 201 and the second pixel, respectively. Between the circuit element layers 202 and between the second pixel circuit element layer 202 and the third pixel circuit element layer 203, the number of the adhesive layers 300 is not limited thereto. In some embodiments, the number of the adhesive layers 300 may be determined according to the number of the pixel circuit element layers 200 to be bonded.

It is worth mentioning that, in this embodiment, the thin film transistor PT1 of the first pixel circuit element layer 201, the thin film transistor PT2 of the second pixel circuit element layer 202, and the thin film of the third pixel circuit element layer 203 The transistor PT3 is electrically connected to the thin film transistor T1, the thin film transistor T2, and the thin film transistor T3 of the circuit element layer 100, respectively. In detail, the pad 160 electrically connected to the thin film transistor T1 and the second pad 262a electrically connected to the thin film transistor PT1 can form a first vertical conductive structure VC1a, and the thin film transistor T1 of the circuit element layer 100 The first vertical conductive structure VC1a is electrically connected to the thin film transistor PT1 of the first pixel circuit element layer 201.

Following the above, the pad 160 electrically connected to the thin film transistor T2, the first conductive element 241b of the first pixel circuit element layer 201, and the pad 260 (the first pad 261 and the second pad) electrically connected thereto 262a) and the second pad 262a electrically connected to the thin film transistor PT2 can form a first vertical conductive structure VC1b, and the thin film transistor T2 of the circuit element layer 100 passes through the first vertical conductive structure VC1b and the second pixel circuit element The thin film transistor PT2 of the layer 202 is electrically connected. In addition, the pad 160 electrically connected to the thin-film transistor T3, the first conductive element 241c of the first pixel circuit element layer 201, and the pad 260 (the first pad 261 and the second pad 262a) electrically connected thereto. ), The first conductive element 241b of the second pixel circuit element layer 202 and its electrically connected pads (the first pad 261 and the second pad 262a) and the second pad electrically connected to the thin film transistor PT3 The pad 262a may form a first vertical conductive structure VC1c, and the thin film transistor T3 of the circuit element layer 100 is electrically connected to the thin film transistor PT3 of the third pixel circuit element layer 203 through the first vertical conductive structure VC1c.

In particular, in this embodiment, the thin-film transistor T1, the thin-film transistor T2, and the thin-film transistor T3 that pass through the circuit element layer 100 are respectively connected to the thin-film transistor PT1 of the first pixel circuit element layer 201 and the second The thin film transistor PT2 of the pixel circuit element layer 202 and the thin film transistor PT3 of the third pixel circuit element layer 203 are electrically connected, which can effectively reduce the leakage current caused by multiple thin film transistors PT1, PT2, and PT3. current) to improve display quality.

The display device 10 further includes a display element layer 400 disposed on the third pixel circuit element layer 203. It should be noted that, in this embodiment, the display element layer 400 is formed after the bonding process between the circuit element layer 100 and the plurality of pixel circuit element layers 200. However, the present invention is not limited to this. According to other embodiments, the display element layer 400 may also be formed in the manufacturing process of the third pixel circuit element layer 203.

The display element layer 400 includes a plurality of first electrodes 410. In this embodiment, the plurality of first electrodes 410 may include a first electrode 411, a first electrode 412, and a first electrode 413, which are disposed on the buffer layer 210 of the third pixel circuit element layer 203 and respectively penetrate the third layer. The gate insulating layer 220 and the interlayer insulating layer 230 of the pixel circuit element layer 203 are electrically connected to the plurality of first conductive elements 241A of the third pixel circuit element layer 203. In detail, in this embodiment, the plurality of first conductive elements 241A of the third pixel circuit element layer 203 include a first conductive element 241e, a first conductive element 241f, a first conductive element 241g, and a first electrode 411 The first electrode 412 and the first electrode 413 are electrically connected to the first conductive element 241e, the first conductive element 241f, and the first conductive element 241g, respectively, but the present invention is not limited thereto.

In this embodiment, the first electrode 411 is electrically connected to the thin film transistor PT1 of the first pixel circuit element layer 201, and the first electrode 412 is electrically connected to the thin film transistor PT2 of the second pixel circuit element layer 202. The first electrode 413 is electrically connected to the thin film transistor PT3 of the third pixel circuit element layer 203, but the invention is not limited thereto. In detail, the first conductive element 241a of the first pixel circuit element layer 201 and the first pad 261 electrically connected thereto, and the first conductive element 241c of the second pixel circuit element layer 202 and the electrical connection thereof The pad 260 (the first pad 261 and the second pad 262a) and the first conductive element 241e of the third pixel circuit element layer 203 and the second pad 262a electrically connected to the second pad 262a can form a second vertical conductive structure VC2a. The first electrode 411 of the display element layer 400 is electrically connected to the thin film transistor PT1 of the first pixel circuit element layer 201 through the second vertical conductive structure VC2a.

Following the above, the first conductive element 241a of the second pixel circuit element layer 202 and the first pad 261 electrically connected thereto, the first conductive element 241f of the third pixel circuit element layer 203, and the first electrically connected element 241f thereof. The two pads 262a can form a second vertical conductive structure VC2b, and the first electrode 412 of the display element layer 400 is electrically connected to the thin film transistor PT2 of the second pixel circuit element layer 202 through the second vertical conductive structure VC2b. The first electrode 413 of the display element layer 400 is electrically connected to the thin film transistor PT3 of the third pixel circuit element layer 203 through the first conductive element 241g.

In this embodiment, the display element layer 400 further includes a pixel definition layer 420 covering a part of the surface of the buffer layer 210 of the third pixel circuit element layer 203, and has a plurality of openings 421 overlapping the plurality of first electrodes 410. In this embodiment, the pixel definition layer 420 may selectively cover a part of the surface of the first electrode 410, that is, the vertical projection of the opening 421 of the pixel definition layer 420 on the substrate 50 is located on the substrate of the first electrode 410 on the substrate. The vertical projection on 50 is within, but the invention is not limited thereto.

The display element layer 400 further includes a display medium 430 and a second electrode 440. In this embodiment, the display medium 430 is disposed in the opening 421 of the pixel definition layer 420, and the material of the display medium 430 is, for example, a light-emitting material. The luminescent material includes a composition of an organic electroluminescent material, a fluorescent organic electroluminescent material, an inorganic electroluminescent material, or a composition of at least two of the foregoing materials, but the present invention is not limited thereto. The second electrode 440 covers the pixel definition layer 420 and fills the openings 421 of the pixel definition layer 420 to cover the display medium 430. The display element layer 400 may further include an encapsulation layer 450 covering the second electrode 440. In this embodiment, the material of the encapsulation layer 450 may include silicon nitride, aluminum oxide, aluminum nitride carbide, silicon oxynitride, acrylic resin, hexamethyldisiloxane (HMDSO), or glass.

On the other hand, in this embodiment, the plurality of second conductive elements 242A of the third pixel circuit element layer 203 include a second conductive element 242d and a second conductive element 242e, and the second conductive element 242d and the second conductive element 242e is electrically connected to the second signal line SL2 and the third signal line SL3 of the circuit element layer 100, respectively. In detail, the conductive element 140 of the circuit element layer 100 and its electrically connected pad 160, the second conductive element 242A of the first pixel circuit element layer 201, and its electrically connected pad 260 (the first pad) 261 and the second pad 262b), the second conductive element 242A of the second pixel circuit element layer 202, the electrically connected pad 260 (the first pad 261 and the second pad 262b), and the third pixel The second pad 262b of the circuit element layer 203 may form a third vertical conductive structure VC3.

Following the above, the second signal line SL2 and the third signal line SL3 of the circuit element layer 100 pass through the two third vertical conductive structures VC3 and the second conductive element 242d and the second conductive element 242e of the third pixel circuit element layer 203, respectively. Electrical connection. In some embodiments, the third signal line SL3 is, for example, a scan line, and the scan start signal is transmitted to the first pixel circuit element layer 201 and the second pixel circuit element layer through the third vertical conductive structure VC3. 202 and the third pixel circuit element layer 203 are transmitted to drive the thin film transistor PT1, the thin film transistor PT2, and the thin film transistor PT3, respectively.

In this embodiment, the pad 160 electrically connected to the fourth signal line SL4, the first conductive element 241d of the first pixel circuit element layer 201, and the pad 260 (the first pad 261 and the first pad 261) electrically connected thereto. The second pad 262a), the first conductive element 241d of the second pixel circuit element layer 202, the pad 260 (the first pad 261 and the second pad 262a) electrically connected to the first conductive element 241h, and the first conductive element 241h. The second pad 262a electrically connected may form a fourth vertical conductive structure VC4a, and the fourth signal line SL4 is electrically connected to the first conductive element 241h of the third pixel circuit element layer 203 through the fourth vertical conductive structure VC4a.

In addition, the pad 160 electrically connected to the fifth signal line SL5, the second conductive element 242a of the first pixel circuit element layer 201, and the electrically connected pad 260 (the first pad 261 and the second pad) 262b), the second conductive element 242a of the second pixel circuit element layer 202 and its electrically connected pad 260 (the first pad 261 and the second pad 262b), and the electrically connected pad 260a The second pad 262a can form a fourth vertical conductive structure VC4b, and the fifth signal line SL5 is electrically connected to the first conductive element 241i of the third pixel circuit element layer 203 through the fourth vertical conductive structure VC4b.

In some embodiments, the fourth signal line SL4 and the fifth signal line SL5 are, for example, power lines. For example, the fourth signal line SL4 may be connected to a high voltage level (such as Vdd), and the fifth signal line SL5 may be Connect to a reference level (eg Vss). That is, the fourth signal line SL4 can transmit a high voltage signal to the first conductive element 241h of the third pixel circuit element layer 203 through the fourth vertical conductive structure VC4a to provide a high voltage source required by the pixel driving circuit. The fifth signal line SL5 can transmit the reference signal to the first conductive element 241i of the third pixel circuit element layer 203 through the fourth vertical conductive structure VC4b to provide a reference signal required by the pixel driving circuit.

In summary, the display device of the embodiment of the present invention is provided with a polycrystalline silicon thin film transistor and a thin film transistor having a metal oxide semiconductor or an amorphous silicon semiconductor, which are respectively disposed on a pixel circuit element layer bonded to each other with an adhesive layer and The circuit element layer can increase process tolerance and circuit design margin. In addition, at least one of the source electrode, the drain electrode, and the gate electrode of the thin film transistor and the plurality of signal lines are in the same film layer, which can reduce the number of photomasks and simplify the manufacturing process to effectively reduce the production cost. In addition, by electrically connecting the polycrystalline silicon thin film transistor with a thin film transistor having a metal oxide semiconductor or an amorphous silicon semiconductor, the leakage current generated by the polycrystalline silicon thin film transistor can be effectively reduced to improve display quality.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

10‧‧‧ display device

50‧‧‧ substrate

51‧‧‧Temporary substrate

100‧‧‧Circuit element layer

110, 210‧‧‧ buffer layer

120, 220‧‧‧ Gate insulation

130, 230‧‧‧ interlayer insulation

140, 241, 241A, 241a ~ 241i, 242, 242A, 242a ~ 242e‧‧‧ conductive elements

150, 250‧‧‧ Insulation

150s, 250s‧‧‧ surface

160, 260, 261, 262, 262a, 262b

160s, 262s‧‧‧Top

200, 201, 202, 203‧‧‧ pixel circuit element layers

300‧‧‧ Adhesive layer

400‧‧‧Display component layer

410, 411, 412, 413‧‧‧ first electrode

420‧‧‧pixel definition layer

421‧‧‧ opening

430‧‧‧Display media

440‧‧‧Second electrode

450‧‧‧Encapsulation

D, PD‧‧‧ Drain

G, PG‧‧‧Gate

n‧‧‧normal direction

PSC‧‧‧Polycrystalline Silicon Semiconductor Pattern

S, PS‧‧‧Source

SC‧‧‧Semiconductor pattern

SL, SL1 ~ SL5‧‧‧ signal line

T, T1 ~ T3, PT, PT1 ~ PT3 ‧‧‧ thin film transistor

VC1a ~ VC1c‧‧‧The first vertical conductive structure

VC2a ~ VC2b‧‧‧Second vertical conductive structure

VC3‧‧‧The third vertical conductive structure

VC4a, VC4b‧‧‧ Fourth vertical conductive structure

FIG. 1 is a schematic cross-sectional view of a display device according to an embodiment of the present invention. 2A to 2E are schematic structural cross-sectional views of the display device of FIG. 1 at different stages in the manufacturing process.

Claims (11)

A display device includes: a substrate; a first element layer disposed on the substrate, the first element layer including: a plurality of signal lines; and a first thin film transistor having a first gate electrode, a first A source, a first drain, and a first semiconductor pattern; a second element layer disposed on the first element layer, the second element layer including: a second thin film transistor and the first thin film The transistor is electrically connected and has a second gate electrode, a second source electrode, a second drain electrode, and a first polycrystalline silicon semiconductor pattern. A first adhesive layer is disposed between the first element layer and the first element layer. Between the second element layers; and a display element layer disposed on the second element layer, the display element layer including a first electrode, the first electrode being electrically connected to the second thin film transistor, wherein the first At least one of a gate electrode, the first source electrode, and the first drain electrode belongs to the same film layer as the signal lines, and the material of the first semiconductor pattern includes a metal oxide semiconductor or an amorphous silicon semiconductor. The display device according to item 1 of the application, wherein the first drain of the first thin film transistor is electrically connected to the second source of the second thin film transistor. The display device according to item 1 of the scope of patent application, wherein the second gate of the second thin film transistor is disposed on the first thin film transistor and the first polycrystalline silicon semiconductor pattern of the second thin film transistor. between. The display device according to item 1 of the scope of patent application, wherein the first element layer further includes: a third thin film transistor having a third gate, a third source, a third drain and a first Two semiconductor patterns, wherein at least one of the third gate electrode, the third source electrode, and the third drain electrode belongs to the same film layer as the signal lines, and the material of the second semiconductor pattern includes a metal oxide semiconductor or Amorphous silicon semiconductor. The display device according to item 4 of the scope of patent application, further comprising: a third element layer disposed between the second element layer and the display element layer, the third element layer including: a fourth thin film transistor Having a fourth gate, a fourth source, a fourth drain, and a second polycrystalline silicon semiconductor pattern; and a second adhesive layer disposed on the second element layer and the third element layer Meanwhile, the third drain electrode of the third thin film transistor is electrically connected to the fourth source of the fourth thin film transistor. The display device according to item 5 of the scope of patent application, wherein the fourth gate of the fourth thin film transistor is disposed on the third thin film transistor and the second polycrystalline silicon semiconductor pattern of the fourth thin film transistor. between. The display device according to item 5 of the patent application, wherein the second element layer further includes a first conductive element, and the first conductive element is electrically connected to the third drain electrode of the third thin film transistor and the third thin film transistor. Between the fourth source of the fourth thin film transistor. The display device according to item 5 of the scope of patent application, wherein the first element layer further includes: a fifth thin-film transistor having a fifth gate, a fifth source, a fifth drain, and a first Three semiconductor patterns, wherein at least one of the fifth gate, the fifth source, and the fifth drain belongs to the same film layer as the signal lines, and the material of the third semiconductor pattern includes a metal oxide semiconductor or Amorphous silicon semiconductor. The display device according to item 8 of the scope of patent application, further comprising: a fourth element layer disposed between the third element layer and the display element layer, the fourth element layer including: a sixth thin film transistor Having a sixth gate, a sixth source, a sixth drain, and a third polycrystalline silicon semiconductor pattern; and a third adhesive layer disposed on the third element layer and the fourth element layer Meanwhile, the fifth drain electrode of the fifth thin film transistor is electrically connected to the sixth source of the sixth thin film transistor. The display device according to item 9 of the scope of patent application, wherein the sixth gate of the sixth thin film transistor is disposed on the fifth thin film transistor and the third polycrystalline silicon semiconductor pattern of the sixth thin film transistor. between. The display device according to item 9 of the scope of patent application, wherein the second element layer further includes a first conductive element, the first conductive element is electrically connected to the fifth drain of the fifth thin film transistor, and the first The three-element layer further includes a second conductive element, and the second conductive element is electrically connected between the first conductive element and the sixth source of the sixth thin film transistor.