CN109742127B - Pixel structure - Google Patents

Abstract

A pixel structure comprises a first element substrate, a first light-emitting element, a second light-emitting element, a first inorganic packaging layer, an organic packaging layer and a second inorganic packaging layer, wherein the first light-emitting element and the second light-emitting element are adjacent to each other. The first light-emitting element and the second light-emitting element are disposed on the first element substrate and electrically connected to the first element substrate, wherein the first light-emitting element includes a first light-emitting layer, and the second light-emitting element includes a second light-emitting layer. The first inorganic packaging layer covers the first light-emitting element and the second light-emitting element. The organic encapsulation layer is disposed on the first inorganic encapsulation layer, wherein the organic encapsulation layer has a first opening, and the first opening is located between the first light emitting layer of the first light emitting device and the second light emitting layer of the second light emitting device. The second inorganic packaging layer is configured on the organic packaging layer.

Description

Pixel structure

Technical Field

The present invention relates to a pixel structure, and more particularly, to a pixel structure applied to a display panel.

Background

As portable display panels are widely used, development of flexible display panels is more active, but the degree of bending of the flexible display panels is still limited. Therefore, how to improve the flexibility of the display panel has become one of the issues to be solved.

Disclosure of Invention

One embodiment of the present invention provides a pixel structure having improved flexibility.

The pixel structure of one embodiment of the present invention includes a first element substrate, a first light emitting element and a second light emitting element adjacent to each other, a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. The first light-emitting element and the second light-emitting element are disposed on the first element substrate and electrically connected to the first element substrate, wherein the first light-emitting element includes a first light-emitting layer, and the second light-emitting element includes a second light-emitting layer. The first inorganic packaging layer covers the first light-emitting element and the second light-emitting element. The organic encapsulation layer is disposed on the first inorganic encapsulation layer, wherein the organic encapsulation layer has a first opening, and the first opening is located between the first light emitting layer of the first light emitting device and the second light emitting layer of the second light emitting device. The second inorganic packaging layer is configured on the organic packaging layer.

In another embodiment of the present invention, a pixel structure includes a first element substrate, a first light emitting element and a second light emitting element adjacent to each other, and a package structure layer. The first element substrate has a first surface and a second surface opposite to each other and includes a first opening, wherein the first opening penetrates through the first surface and the second surface. The first light-emitting element and the second light-emitting element are disposed on the first element substrate and electrically connected to the first element substrate, wherein the first light-emitting element includes a first light-emitting layer, the second light-emitting element includes a second light-emitting layer, and the first opening is located between the first light-emitting layer of the first light-emitting element and the second light-emitting layer of the second light-emitting element. The packaging structure layer covers the first light-emitting element and the second light-emitting element.

In view of the above, in the pixel structure of at least one embodiment of the invention, the organic encapsulation layer has an opening between two adjacent light emitting layers, or the element substrate has openings penetrating through two surfaces thereof, so that the pixel structure has improved flexibility. Therefore, when the flexible display panel has the pixel structure, the flexible display panel has improved bending degree, and further the applicability of the flexible display panel is improved.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a schematic top view of a pixel structure according to an embodiment of the invention.

Fig. 2 is a circuit diagram and a signal path diagram of each film layer of the pixel structure of fig. 1.

Fig. 3 is a schematic sectional view taken along the sectional line I-I' in fig. 1.

Fig. 4A to 4E are schematic top views of pixel structures according to other embodiments of the present invention.

Fig. 5 is a schematic cross-sectional view of a pixel structure according to another embodiment of the invention.

Fig. 6 is a schematic cross-sectional view of a pixel structure according to another embodiment of the invention.

Fig. 7 is a schematic top view of a pixel structure according to another embodiment of the invention.

FIG. 8 is a circuit and signal path diagram of the various layers of the pixel structure of FIG. 7.

Fig. 9 is a schematic sectional view taken along the sectional line II-II' in fig. 7.

Fig. 10 is a schematic cross-sectional view of a pixel structure according to another embodiment of the invention.

Fig. 11 is a schematic cross-sectional view of a pixel structure according to another embodiment of the invention.

Description of reference numerals:

10. 20, 30, 40, 50, 60: pixel structure

100. 200 and 300: element substrate

102. 202, 302: insulating layer

A1, a2, C1, C2: electrode for electrochemical cell

ACF1, ACF 2: anisotropic conductive layer

CL: electrode layer

CR1, CR 2: channel region

CS1, CS 2: connection structure

d1, d 2: distance between two adjacent plates

D1, D2: drain electrode

DL1, DL2, DL3, SL1, SL 2: signal line

DR1, DR 2: drain region

E1, E2: luminescent layer

F1, F2, F3, F4, F5, F6, F7, F8: surface of

G1, G2: grid electrode

GI. 2GI, 3 GI: gate insulating layer

H1, H2, H3, H4, H5, H6: contact window

IL1, IL2, 2IL1, 2IL2, 3IL1, 3IL 2: interlayer insulating layer

O1, O2, O3: light emitting element

P1, P2: connecting pad

PDL: pixel definition layer

PL, 2PL, 3 PL: planarization layer

Q, R1, R2, R3, R4, R5, V1, V2, X, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9, Z1, Z2, Z3, Z4, Z5: opening of the container

S1, S2: source electrode

SC1, SC 2: semiconductor layer

SR1, SR 2: source region

t: thickness of

T1, T2, T3: active component

TFE, TFE3, TFE 6: packaging structure layer

TFEa, TFEc, TFE3a, TFE3c, TFE6a, TFE6 c: inorganic encapsulation layer

TFEb, TFE3b, TFE6 b: organic encapsulation layer

U1, U2, U3, U4, U5: pixel unit area

w1, w 2: side wall

Detailed Description

In this context, a range denoted by "a numerical value to another numerical value" is a general expression avoiding a recitation of all numerical values in the range in the specification. Thus, recitation of a range of values herein is intended to encompass any value within the range and any smaller range defined by any value within the range, as if the range and smaller range were explicitly recited in the specification.

As used herein, "about", "approximately", "essentially", or "substantially" includes the stated value and the average value within an acceptable range of deviation of the specified value as determined by one of ordinary skill in the art, taking into account the measurement in question and the specified amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within, for example, ± 30%, ± 20%, ± 15%, ± 10%, ± 5%. Further, as used herein, "about", "approximately", "essentially", or "substantially" may be selected with respect to measured properties, cutting properties, or other properties, to select a more acceptable range of deviation or standard deviation, and not to apply one standard deviation to all properties.

In the drawings, the thickness of layers, films, panels, regions, etc. have been exaggerated for clarity. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connections. Further, "electrically connected" may mean that there are other elements between the two elements.

Fig. 1 is a schematic top view of a pixel structure according to an embodiment of the invention. Fig. 2 is a circuit diagram and a signal path diagram of each film layer of the pixel structure of fig. 1. Fig. 3 is a schematic sectional view taken along the sectional line I-I' in fig. 1.

Referring to fig. 1, the pixel structure 10 may include a plurality of pixel unit regions U1-U3. Although fig. 1 discloses the pixel structure 10 including three pixel unit regions U1-U3, the number of pixel unit regions is not limited in the present invention, and may be adjusted according to the actual architecture, requirements, etc. of the pixel structure 10. In addition, the arrangement of the pixel unit areas U1-U3 is not limited to that shown in fig. 1, and can be adjusted according to the actual architecture and requirements of the pixel structure 10.

Referring to fig. 1 to fig. 3, the pixel structure 10 may include an element substrate 100, a plurality of light emitting elements O1-O3, and an encapsulation structure layer TFE, wherein the encapsulation structure layer TFE includes an inorganic encapsulation layer TFEa, an organic encapsulation layer TFEb, and an inorganic encapsulation layer TFEc. In addition, in the present embodiment, the pixel structure 10 may further include a pixel definition layer PDL and pads P1 to P2. For convenience of illustration, fig. 1 omits to show part of the film layers to clearly show the configuration relationship between the film layers.

In this embodiment, the device substrate 100 may include an insulating layer 102, a signal line SL, a plurality of signal lines DL1 to DL3, a plurality of active devices T1 to T3, a plurality of connection structures CS1 to CS2, a gate insulating layer GI, an interlayer insulating layer IL1, an interlayer insulating layer IL2, and a planarization layer PL.

In this embodiment, the insulating layer 102 is a substrate as the element substrate 100. In this embodiment, the material of the insulating layer 102 may include: an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stack of at least two of the above materials), an organic material (e.g., polyimide-based resin, epoxy-based resin, or acrylic-based resin), or a combination thereof, but the invention is not limited thereto. In this embodiment, the insulating layer 102 has a single-layer structure, but the present invention is not limited thereto. In other embodiments, the insulating layer 102 may also be a multilayer structure.

In the present embodiment, the signal lines SL are scanning lines, and the signal lines DL1 to DL3 are data lines, but the present invention is not limited to this. In this embodiment, the signal line SL may not be parallel to the signal lines DL 1-DL 3, i.e., the signal line SL intersects the signal lines DL 1-DL 3. In addition, the signal line SL and the signal lines DL1 to DL3 may be located on different layers, and a gate insulating layer GI (described in detail later) may be interposed between the signal line SL and the signal lines DL1 to DL 3. For electrical conductivity, the signal lines SL and DL 1-DL 3 are typically made of metal. However, the present invention is not limited thereto, and according to other embodiments, the signal line SL and the signal lines DL1 to DL3 may also be formed of, for example, an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, other non-metal materials having a conductive property, or a stacked layer of a metal material and the above materials. In this embodiment, the signal line SL and the signal lines DL1 to DL3 may have a single-layer or multilayer structure.

Referring to fig. 2, in the present embodiment, the active device T1 is disposed in the pixel unit region U1, the active device T2 is disposed in the pixel unit region U2, and the active device T3 is disposed in the pixel unit region U3. In the present embodiment, the active device T1 is electrically connected to the signal line DL1 and the signal line SL, the active device T2 is electrically connected to the signal line DL2 and the signal line SL, and the active device T3 is electrically connected to the signal line DL3 and the signal line SL.

Referring to fig. 3, in the present embodiment, the active device T1 may include a semiconductor layer SC1, a gate G1, a source S1 and a drain D1, wherein the semiconductor layer SC1 includes a source region SR1, a drain region DR1 and a channel region CR1, the gate G1 is located above the channel region CR1 and overlaps with the channel region CR1, the source S1 is electrically connected to the source region SR1 through a contact H1 formed in a gate insulating layer GI (described in detail later) and an interlayer insulating layer IL1 (described in detail later), and the drain D1 is electrically connected to the drain region DR1 through a contact H2 formed in the gate insulating layer GI (described in detail later) and the interlayer insulating layer IL1 (described in detail later). On the other hand, in the present embodiment, the active device T2 may include a semiconductor layer SC2, a gate G2, a source S2 and a drain D2, wherein the semiconductor layer SC2 includes a source region SR2, a drain region DR2 and a channel region CR2, the gate G2 is located above the channel region CR2 and overlaps with the channel region CR2, the source S2 is electrically connected to the source region SR2 through a contact window H3 formed in a gate insulating layer GI (described in detail later) and an interlayer insulating layer IL1 (described in detail later), and the drain D2 is electrically connected to the drain region DR2 through a contact window H4 formed in the gate insulating layer GI (described in detail later) and the interlayer insulating layer IL1 (described in detail later).

Although fig. 3 discloses only a partial structure of the pixel structure 10 corresponding to the cross-section line I-I' and does not disclose a specific structure of the active element T3, a person skilled in the art can understand the specific structure and layout of the active element T3 according to the related descriptions herein for the active element T1 and the active element T2. That is, it is understood by those skilled in the art that the active device T3 may include a semiconductor layer including a source region, a drain region and a channel region, a gate electrode overlying the channel region and overlapping the channel region, a source electrode electrically connected to the source region through a contact formed in a gate insulating layer (described in detail below) and an interlayer insulating layer (described in detail below), and a drain electrode electrically connected to the drain region through a contact formed in a gate insulating layer (described in detail below) and an interlayer insulating layer (described in detail below).

In the present embodiment, the active devices T1 to T3 are top gate thin film transistors, but the present invention is not limited thereto. In other embodiments, the active devices T1 through T3 may be bottom-gate tfts.

In this embodiment, the signal line DL1 is connected to the source S1, and the signal line DL2 is connected to the source S2. As shown in fig. 3, the signal line DL1 is directly connected to the source S1, and the signal line DL2 is directly connected to the source S2, but the invention is not limited thereto. In addition, although fig. 3 only discloses a partial structure of the pixel structure 10 corresponding to the cross-section line I-I', it can be understood by those skilled in the art that the signal line DL3 is connected to the source of the active device T3.

In this embodiment, the gate G1, the source S1, the drain D1, the gate G2, the source S2 and the drain D2 may include (but are not limited to): metals, alloys, nitrides of the foregoing materials, oxides of the foregoing materials, oxynitrides of the foregoing materials, other non-metallic but electrically conductive materials, or other suitable materials. In the present embodiment, the material of the semiconductor layers SC1 and SC2 may include polysilicon, i.e., the active devices T1 and T2 may be LTPS TFTs (Low Temperature Poly-Silicon Thin Film transistors). However, the present invention is not limited to the type of the active device. In other embodiments, the material of semiconductor layer SC1 and semiconductor layer SC2 may include amorphous silicon, microcrystalline silicon, nanocrystalline silicon, monocrystalline silicon, organic semiconductor materials, metal oxide semiconductor materials, carbon nanotubes/rods, perovskites, or other suitable materials.

In this embodiment mode, the gate insulating layer GI is formed entirely over the insulating layer 102 and covers the semiconductor layer SC1 and the semiconductor layer SC 2. The gate insulating layer GI may have a single-layer or multi-layer structure, and the material may include an inorganic material, an organic material, or other suitable materials, wherein the inorganic material includes (but is not limited to): silicon oxide, silicon nitride, or silicon oxynitride; organic materials include, for example (but are not limited to): a polyimide-based resin, an epoxy-based resin, or an acryl-based resin.

In this embodiment, the interlayer insulating layer IL1 is formed entirely on the insulating layer 102 and covers the gate G1 and the gate G2. The interlayer insulating layer IL1 may have a single-layer or multi-layer structure, and the material may include inorganic materials, such as (but not limited to): silicon oxide, silicon nitride, or silicon oxynitride; organic materials include, for example (but are not limited to): a polyimide-based resin, an epoxy-based resin, or an acryl-based resin.

In the present embodiment, the interlayer insulating layer IL2 is formed entirely on the insulating layer 102 and covers the active device T1 and the active device T2 to provide insulation and protection functions. The interlayer insulating layer IL2 may have a single-layer or multi-layer structure, and the material may include inorganic materials, such as (but not limited to): silicon oxide, silicon nitride, or silicon oxynitride; organic materials include, for example (but are not limited to): a polyimide-based resin, an epoxy-based resin, or an acryl-based resin.

In this embodiment, the planarization layer PL is formed entirely on the interlayer insulating layer IL2 to provide protection and planarization functions. The planarization layer PL may be a single layer or a multi-layer structure, and the material may include inorganic materials, such as (but not limited to): silicon oxide, silicon nitride, or silicon oxynitride; organic materials include, for example (but are not limited to): a polyimide-based resin, an epoxy-based resin, or an acryl-based resin.

In this embodiment mode, the connection structure CS1 is located in the insulating layer 102, the gate insulating layer GI, and the interlayer insulating layer IL1, and the connection structure CS2 is located in the insulating layer 102, the gate insulating layer GI, and the interlayer insulating layer IL 1. In this embodiment, the connection structure CS1 is connected to the signal line DL1, and the connection structure CS2 is connected to the signal line DL 2. As shown in fig. 3, the connection structure CS1 is directly connected to the signal line DL1, and the connection structure CS2 is directly connected to the signal line DL2, but the invention is not limited thereto. On the other hand, as described above, the signal line DL1 is connected to the source S1, and the signal line DL2 is connected to the source S2, so the signal line DL1 is connected to the source S1 and the connection structure CS1, and the signal line DL2 is connected to the source S1 and the connection structure CS 1. In this embodiment, the materials of the connection structures CS1 and CS2 may include (but are not limited to): metals, alloys, nitrides of the foregoing materials, oxides of the foregoing materials, oxynitrides of the foregoing materials, other non-metallic but electrically conductive materials, or other suitable materials. In addition, although fig. 3 discloses only a partial structure of the pixel structure 10 corresponding to the cross-sectional line I-I', it should be understood by those skilled in the art that the element substrate 100 includes a connection structure connected to the signal line DL 3.

In this embodiment, the pad P1 is connected to the connection structure CS1, and the pad P2 is connected to the connection structure CS 2. As shown in fig. 3, the pad P1 is directly connected to the connection structure CS1, and the pad P2 is directly connected to the connection structure CS2, but the invention is not limited thereto. On the other hand, as described above, the connection structure CS1 is connected to the signal line DL1, and the connection structure CS2 is connected to the signal line DL2, so that the connection structure CS1 is used to connect the signal line DL1 and the pad P1, and the connection structure CS2 is used to connect the signal line DL2 and the pad P2. In this embodiment, the material of the pads P1 and P2 may include metal, alloy, nitride of the above materials, oxide of the above materials, oxynitride of the above materials, other non-metal but conductive materials, or other suitable materials, wherein the metal is, for example (but not limited to): molybdenum, aluminum or titanium. In addition, in the present embodiment, each of the pads P1 and P2 may have a single-layer or multi-layer structure. In the present embodiment, the pads P1 and P2 are used to electrically connect to an external circuit, such as a flexible circuit board and/or an ic chip. In addition, although fig. 3 only discloses a partial structure of the pixel structure 10 corresponding to the cross-sectional line I-I', it should be understood by those skilled in the art that the device substrate 100 includes a pad connected to the signal line DL 3.

Referring to fig. 2, in the present embodiment, the light emitting device O1 is disposed in the pixel unit region U1, the light emitting device O2 is disposed in the pixel unit region U2, and the light emitting device O3 is disposed in the pixel unit region U3. In addition, in the present embodiment, the light emitting device O1 is electrically connected to the active device T1, the light emitting device O2 is electrically connected to the active device T2, and the light emitting device O3 is electrically connected to the active device T3. Although fig. 2 only discloses that the light emitting elements O1-O3 are electrically connected to the active elements T1-T3, respectively, it should be understood by those skilled in the art that the light emitting elements O1-O3 are actually driven by a driving unit having, for example, an architecture of 1T1C, an architecture of 2T1C, an architecture of 3T1C, an architecture of 3T2C, an architecture of 4T1C, an architecture of 4T2C, an architecture of 5T1C, an architecture of 5T2C, an architecture of 6T1C, an architecture of 6T2C, an architecture of 7T2C, or any possible architecture. That is, the active devices T1 through T3 may be one of the driving units for driving the light emitting devices O1 through O3, respectively.

Referring to fig. 1 and fig. 3, in the present embodiment, the light emitting element O1 is disposed adjacent to the light emitting element O2. Although fig. 3 discloses only a partial structure of the pixel structure 10 corresponding to the cross-sectional line I-I', it should be understood by anyone skilled in the art that the light emitting element O3 is disposed adjacent to the light emitting element O2.

In this embodiment mode, the light-emitting element O1 includes a light-emitting layer E1, an electrode a1, and an electrode C1. In this embodiment, the electrode a1 is electrically connected to the drain D1 of the active device T1 through a contact hole H5 formed in the interlayer insulating layer IL2 and the planarization layer PL. That is, in this embodiment, the electrode a1 is electrically connected to the element substrate 100. In this embodiment mode, the light-emitting layer E1 is disposed between the electrode a1 and the electrode C1 and is formed in the opening V1 of the pixel defining layer PDL. In this embodiment mode, a portion where the electrode a1 overlaps with the light-emitting layer E1 serves as an anode of the light-emitting element O1, and a portion where the electrode C1 overlaps with the light-emitting layer E1 serves as a cathode of the light-emitting element O1, but the present invention is not limited thereto, and in other embodiment modes, a portion where the electrode a1 overlaps with the light-emitting layer E1 serves as a cathode of the light-emitting element O1, and a portion where the electrode C1 overlaps with the light-emitting layer E1 serves as an anode of the light-emitting element O1. On the other hand, in this embodiment mode, the light-emitting element O2 may include a light-emitting layer E2, an electrode a2, and an electrode C2. In this embodiment, the electrode a2 is electrically connected to the drain D2 of the active device T2 through a contact hole H6 formed in the interlayer insulating layer IL2 and the planarization layer PL. That is, in this embodiment, the electrode a2 is electrically connected to the element substrate 100. In this embodiment mode, the light-emitting layer E2 is disposed between the electrode a2 and the electrode C2 and is formed in the opening V2 of the pixel defining layer PDL. In this embodiment mode, a portion where the electrode a2 overlaps with the light-emitting layer E2 serves as an anode of the light-emitting element O2, and a portion where the electrode C2 overlaps with the light-emitting layer E2 serves as a cathode of the light-emitting element O2, but the present invention is not limited thereto, and in other embodiment modes, a portion where the electrode a2 overlaps with the light-emitting layer E2 serves as a cathode of the light-emitting element O2, and a portion where the electrode C2 overlaps with the light-emitting layer E2 serves as an anode of the light-emitting element O2.

In this embodiment, the material of the electrode a1 and the electrode a2 can be a transparent conductive material, an opaque conductive material, or a stacked layer of the foregoing materials. The transparent conductive material may comprise a metal oxide conductive material, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, other suitable oxides, or a stack of at least two of the foregoing. The opaque conductive material may include a metal material.

In this embodiment mode, the light-emitting layers E1 and E2 can be any light-emitting layers known to those skilled in the art to be used in display panels. The light-emitting layers E1 and E2 may be a red organic light-emitting layer, a green organic light-emitting layer, a blue organic light-emitting layer, an organic light-emitting layer of another color, or a combination thereof.

In this embodiment, the material of the electrode C1 and the electrode C2 can be transparent conductive material or opaque conductive material. The transparent conductive material may include a metal oxide conductive material, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, a thin metal, other suitable oxide, or a stacked layer of at least two of the foregoing. The opaque conductive material may comprise a metal. In addition, in this embodiment mode, the electrode C1 and the electrode C2 are connected to each other to form an electrode layer CL. In other words, in this embodiment mode, a portion of the electrode layer CL corresponding to the light-emitting layer E1 is an electrode C1 of the light-emitting element O1, and a portion of the electrode layer CL corresponding to the light-emitting layer E2 is an electrode C2 of the light-emitting element O2.

In this embodiment, the material of the pixel definition layer PDL may include a photosensitive polyimide material, an acryl material, a siloxane material, a phenolic resin material, an oxide, a nitride, or an oxynitride, but the invention is not limited thereto.

In addition, any person skilled in the art can selectively dispose an electron transport layer, an electron injection layer, a hole transport layer, a hole injection layer, or a combination of the above four layers at a suitable position between the electrode a1 and the electrode C1 and a suitable position between the electrode a2 and the electrode C2, respectively. In addition, although fig. 3 discloses only a partial structure of the pixel structure 10 and does not show a specific structure of the light emitting element O3, a person skilled in the art can understand a specific structure and layout of the light emitting element O3 and the like according to the related description of the light emitting element O1 and the light emitting element O2, and the detailed description is omitted here.

In this embodiment, the inorganic sealing layer TFEa covers the light emitting element O1 and the light emitting element O2 to isolate moisture, humidity, and the like. In this embodiment, the material of the inorganic encapsulation layer TFEa may include (but is not limited to): silicon nitride, aluminum oxide, or silicon oxynitride.

In the present embodiment, the organic encapsulation layer TFEb is disposed on the inorganic encapsulation layer TFEa to isolate impurities, particles, and the like generated in the process. In this embodiment, the material of the organic encapsulation layer TFEb may include (but is not limited to): acrylic, epoxy, or silicon oxycarbide. As shown in fig. 3, in this embodiment mode, the organic encapsulation layer TFEb has an opening Q between the light-emitting layer E1 of the light-emitting element O1 and the light-emitting layer E2 of the light-emitting element O2. Specifically, the opening Q penetrates through the surface F1 and the surface F2 of the organic encapsulation layer TFEb, which are disposed opposite to each other. In other words, in the present embodiment, the organic encapsulation layer TFEb is a patterned film layer, and the opening Q may expose a portion of the inorganic encapsulation layer TFEa. On the other hand, as shown in fig. 1, in the present embodiment, the opening Q is located between the pixel cell region U1 and the pixel cell region U2 and the pixel cell region U1 and the pixel cell region U3. Although fig. 3 discloses only a partial structure of the pixel structure 10 corresponding to the cross-section line I-I', it can be understood by those skilled in the art from the foregoing description that the organic encapsulation layer TFEb has an opening Q also located between the light-emitting layer E1 of the light-emitting element O1 and the light-emitting layer E3 of the light-emitting element O3.

Although fig. 1 only discloses that the pixel structure 10 has the opening Q only between the pixel unit region U1 and the pixel unit region U2 and the pixel unit region U1 and the pixel unit region U3, the present invention is not limited thereto. In one embodiment, in addition to the opening Q between the pixel cell region U1 and the pixel cell region U2 and between the pixel cell region U1 and the pixel cell region U3, the organic encapsulation layer TFEb may have an opening Q between the emission layer E2 of the light emitting element O2 and the emission layer E3 of the light emitting element O3 (as shown in fig. 4A). In another embodiment, the organic encapsulation layer TFEb may have no opening between the pixel cell region U1 and the pixel cell region U2 and between the pixel cell region U1 and the pixel cell region U3 but only an opening Q between the emission layer E2 of the light emitting element O2 and the emission layer E3 of the light emitting element O3 (as shown in fig. 4B).

In addition, as shown in fig. 1, although the pixel structure 10 is viewed from an upper viewing angle, the outline of the opening Q is rectangular and the number thereof is one, but the present invention is not limited thereto. In one embodiment, when the pixel structure 10 is viewed from an upward viewing angle, the outline of the opening Q may be elliptical and the number of the openings Q may be two (as shown in fig. 4C). In another embodiment, when the pixel structure 10 is viewed from an above-viewing angle, the outline of the opening Q may be circular and the number may be two (as shown in fig. 4D).

In addition, although fig. 1 discloses only one pixel structure 10, it should be understood by those skilled in the art that when applied to a device, the number of pixel structures 10 may be multiple and present an array arrangement, and at this time, the opening Q may be located between two pixel structures 10 (as shown in fig. 4E).

In addition, in this embodiment, a distance d1 is formed between a vertical projection of the sidewall w1 of the opening Q adjacent to the light emitting element O1 on the device substrate 100 and a vertical projection of the edge of the light emitting layer E1 on the device substrate 100, and a distance d2 is formed between a vertical projection of the sidewall w2 of the opening Q adjacent to the light emitting element O2 on the device substrate 100 and a vertical projection of the edge of the light emitting layer E2 on the device substrate 100, wherein the distance d1 is greater than or equal to the thickness t of the organic encapsulation layer TFEb, and the distance d2 is greater than or equal to the thickness t of the organic encapsulation layer TFEb. As such, in the present embodiment, even if the organic encapsulation layer TFEb has the opening Q, the organic encapsulation layer TFEb can still provide good protection for the light-emitting element O1 and the light-emitting element O2. In addition, in the present embodiment, the thickness t of the organic encapsulation layer TFEb is between about 1 micron and about 10 microns.

In this embodiment, the inorganic encapsulation layer TFEc is disposed on the organic encapsulation layer TFEb for isolating moisture, humidity, and the like. In the present embodiment, the organic encapsulation layer TFEb is located between the inorganic encapsulation layer TFEa and the inorganic encapsulation layer TFEc. In this embodiment, the material of the inorganic encapsulation layer TFEc may include (but is not limited to): silicon nitride, aluminum oxide, or silicon oxynitride. It should be noted that the material of the inorganic encapsulating layer TFEa and the material of the inorganic encapsulating layer TFEc may be the same or different.

It is to be noted that, in the present embodiment, the pixel structure 10 has enhanced flexibility by the organic encapsulation layer TFEb in the encapsulation structure layer TFE having the opening Q between the light-emitting layer E1 of the light-emitting element O1 and the light-emitting layer E2 of the light-emitting element O2. Therefore, when the flexible display panel has the pixel structure 10, the flexible display panel has an improved bending degree, thereby increasing the applicability of the flexible display panel.

In the foregoing embodiment, the flexibility of the pixel structure 10 is increased due to the organic encapsulation layer TFEb having the opening Q, but the invention is not limited thereto. Hereinafter, other embodiments will be described with reference to fig. 5 and 6. It should be noted that the following embodiments follow the reference numerals and some contents of the foregoing embodiments, wherein the same or similar reference numerals are used to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

Fig. 5 is a schematic cross-sectional view of a pixel structure according to another embodiment of the invention. The position of the cross-section of fig. 5 may correspond to the position of the cross-section line I-I' in fig. 1. Referring to fig. 5 and fig. 3 together, the pixel structure 20 of fig. 5 is similar to the pixel structure 10 of fig. 3, so the same or similar elements are denoted by the same or similar symbols, and descriptions of the same technical contents are omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments. The differences between the pixel structure 20 of fig. 5 and the pixel structure 10 of fig. 3 will be explained below.

Referring to fig. 5, in the pixel structure 20, the element substrate 100 has an opening R1 overlapping with the opening Q. Specifically, the opening R1 penetrates through the surface F3 and the surface F4 of the device substrate 100 that are opposite to each other. In other words, in this embodiment, the opening R1 is located in the insulating layer 102, the gate insulating layer GI, the interlayer insulating layer IL1, the interlayer insulating layer IL2, and the planarization layer PL. On the other hand, in the present embodiment, the opening R1 is disposed in a region where no element or trace is provided in the element substrate 100.

In the pixel structure 20, the pixel defining layer PDL, the electrode layer CL, the inorganic encapsulating layer TFEa, and the inorganic encapsulating layer TFEc respectively have an opening R2, an opening R3, an opening R4, and an opening R5 which overlap with the opening R1. In other words, in the present embodiment, the opening R1, the opening R2, the opening R3, the opening R4, and the opening R5 together constitute a communication opening penetrating the pixel structure 20. In the present embodiment, the opening R1, the opening R2, the opening R3, the opening R4, and the opening R5 completely overlap with each other, but the present invention is not limited thereto. In other embodiments, at least one of the opening R1, the opening R2, the opening R3, the opening R4, and the opening R5 may partially overlap the others.

In addition, in this embodiment, the pixel structure 20 has the opening R1, the opening R2, the opening R3, the opening R4, and the opening R5 which overlap with the opening Q, but the invention is not limited thereto. In other embodiments, the pixel structure 20 may have one, two, three, or four of the opening R1, the opening R2, the opening R3, the opening R4, and the opening R5.

In addition, from the foregoing description regarding the position, number and contour of the opening Q, those skilled in the art should understand that the present invention is not limited to the position, number and contour of the openings R1, R1, R2, R3, R4 and R5. For the rest, please refer to the foregoing embodiments, which are not described herein.

It should be noted that, in addition to the opening Q in the organic encapsulation layer TFEb, the pixel structure 20 further has the opening R1, the opening R1, the opening R2, the opening R3, the opening R4 or the opening R5, so that flexibility can be further improved. Therefore, when the flexible display panel has the pixel structure 20, the flexible display panel has an improved bending degree, thereby increasing the applicability of the flexible display panel.

Fig. 6 is a schematic cross-sectional view of a pixel structure according to another embodiment of the invention. The position of the cross-section of fig. 6 can be referred to the position of the cross-section line I-I' in fig. 1. Referring to fig. 6 and fig. 5, the pixel structure 30 of fig. 6 is similar to the pixel structure 10 of fig. 3, and the difference is mainly: in the pixel structure 30, the element substrate 100 has an opening X and the package structure layer TFE3 has no opening; in the pixel structure 10, the package structure layer TFE has an opening Q, and the element substrate 100 has no opening. The following description will be made regarding differences between the pixel structure 30 of fig. 6 and the pixel structure 10 of fig. 3, the same or similar elements are denoted by the same or similar symbols, and the description of the same technical contents is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments.

Referring to fig. 6, in the pixel structure 30, the encapsulation structure layer TFE3 includes an inorganic encapsulation layer TFE3a, an organic encapsulation layer TFE3b, and an inorganic encapsulation layer TFE3 c. In this embodiment mode, the inorganic encapsulating layer TFE3a covers the light emitting element O1 and the light emitting element O2 and is used for moisture, humidity, or the like. In this embodiment, the materials of the inorganic encapsulation layer TFE3a may include (but are not limited to): silicon nitride, aluminum oxide, or silicon oxynitride. In this embodiment, the organic encapsulation layer TFE3b is disposed on the inorganic encapsulation layer TFE3a to isolate impurities, particles, and the like generated in the process. In this embodiment, the materials of the organic encapsulation layer TFE3b may include (but are not limited to): acrylic, epoxy, or silicon oxycarbide. In this embodiment, the inorganic encapsulating layer TFE3c is disposed on the organic encapsulating layer TFE3b to isolate moisture, humidity, and the like. In this embodiment, the organic encapsulation layer TFE3b is located between the inorganic encapsulation layer TFE3a and the inorganic encapsulation layer TFE3 c. In this embodiment, the materials of the inorganic encapsulation layer TFE3c may include (but are not limited to): silicon nitride, aluminum oxide, or silicon oxynitride. The materials of the inorganic encapsulating layer TFE3a and the inorganic encapsulating layer TFE3c may be the same or different.

In the pixel structure 30, the element substrate 100 has an opening X. Specifically, the opening X penetrates the surface F3 and the surface F4 of the device substrate 100, which are disposed opposite to each other. In other words, in this embodiment, the opening X is located in the insulating layer 102, the gate insulating layer GI, the interlayer insulating layer IL1, the interlayer insulating layer IL2, and the planarization layer PL. In the present embodiment, the opening X is disposed in a region of the element substrate 100 where no element or trace is disposed. In addition, as shown in fig. 6, in the present embodiment, the pixel defining layer PDL is disposed on the opening X, but the present invention is not limited thereto. In other embodiments, a portion of the pixel definition layer PDL may fill the opening X.

In this embodiment, the opening X is located between the light-emitting layer E1 of the light-emitting element O1 and the light-emitting layer E2 of the light-emitting element O2. Although fig. 6 discloses only a partial structure of the pixel structure 30, according to the foregoing description of the pixel structure 10 of fig. 1 to 3, especially the description of the positions, the number and the outlines of the openings Q, it should be understood by those skilled in the art that the present invention is not limited to the positions, the number and the outlines of the openings X. For the rest, please refer to the foregoing embodiments, which are not described herein.

It should be noted that, in the present embodiment, the pixel structure 30 has enhanced flexibility due to the element substrate 100 having the opening X penetrating the surface F3 and the surface F4. Therefore, when the flexible display panel has the pixel structure 30, the flexible display panel has an improved bending degree, thereby increasing the applicability of the flexible display panel.

In the pixel structures 10, 20 and 30, the element substrate 100 includes a plurality of active elements T1-T3, but the invention is not limited thereto. Hereinafter, other embodiments will be described with reference to fig. 7 to 11. It should be noted that the following embodiments follow the reference numerals and some contents of the foregoing embodiments, wherein the same or similar reference numerals are used to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

Fig. 7 is a schematic top view of a pixel structure according to another embodiment of the invention. Fig. 8 is a circuit and signal path diagram of each film layer of the pixel structure of fig. 8. Fig. 9 is a schematic sectional view taken along the sectional line II-II' in fig. 7. Referring to fig. 7-9 and fig. 1-3, the pixel structure 40 is similar to the pixel structure 10, and the difference is mainly: the pixel structure 40 includes three device substrates 100-300, wherein the device substrate 100 includes an active device T1, the device substrate 200 includes an active device T2, and the device substrate 300 includes an active device T3; the pixel structure 10 includes only one device substrate 100, and the device substrate 100 includes an active device T1, an active device T2, and an active device T3. The differences between the pixel structure 40 and the pixel structure 10 will be described below, the same or similar elements are denoted by the same or similar symbols, and the description of the same technical contents is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments.

Referring to fig. 7, the pixel structure 40 may include a pixel unit region U1, a pixel unit region U4, and a pixel unit region U5. In this embodiment, the active device T1 and the light emitting device O1 electrically connected to each other are disposed in the pixel unit region U1, the active device T2 and the light emitting device O2 electrically connected to each other are disposed in the pixel unit region U4, and the active device T3 and the light emitting device O3 electrically connected to each other are disposed in the pixel unit region U5. In the present embodiment, the active device T1 is electrically connected to the signal line DL1 and the signal line SL, the active device T2 is electrically connected to the signal line DL2 and the signal line SL1, and the active device T3 is electrically connected to the signal line DL3 and the signal line SL 2. Although fig. 7 discloses the pixel structure 40 including three pixel unit regions U1, U4-U5, the number of pixel unit regions is not limited in the present invention, and may be adjusted according to the actual architecture, requirements, etc. of the pixel structure 40. In addition, the arrangement of the pixel unit regions U1, U4-U5 is not limited to that shown in fig. 7, and can be adjusted according to the actual architecture, requirements, and the like of the pixel structure 40.

Referring to fig. 7 to 9, in the present embodiment, the pixel structure 40 includes an element substrate 200 disposed below the element substrate 100. In detail, the device substrate 200 may include an insulating layer 202, an active device T2, a signal line SL1, a signal line DL2, a gate insulating layer 2GI, an interlayer insulating layer 2IL1, an interlayer insulating layer 2IL2, and a planarization layer 2PL, wherein the insulating layer 202 serves as a substrate of the device substrate 200, and the signal line SL1 serves as a scan line. In other words, in the present embodiment, the active device T2 and the light emitting device O2 disposed in the pixel unit area U4 are located below the device substrate 100 and above the device substrate 100, respectively. In addition, the insulating layer 202, the signal line SL1, the gate insulating layer 2GI, the interlayer insulating layer 2IL1, the interlayer insulating layer 2IL2, and the planarization layer 2PL in the device substrate 200 may be made of the same or similar materials as those of the corresponding ones of the device substrate 100 (i.e., the insulating layer 102, the signal line SL, the gate insulating layer GI, the interlayer insulating layer IL1, the interlayer insulating layer IL2, and the planarization layer PL), and therefore, the description thereof will not be repeated.

In addition, in the present embodiment, the pixel structure 40 includes an element substrate 300 disposed below the element substrate 100, wherein the element substrate 200 is located between the element substrate 100 and the element substrate 300. In detail, the device substrate 300 may include an insulating layer 302, an active device T3, a signal line SL2, a signal line DL3, a gate insulating layer 3GI, an interlayer insulating layer 3IL1, an interlayer insulating layer 3IL2, and a planarization layer 3PL, wherein the insulating layer 302 serves as a substrate of the device substrate 300, and the signal line SL2 serves as a scan line. In other words, in the present embodiment, the active device T3 and the light emitting device O3 disposed in the pixel unit area U5 are located below the device substrates 100 and 200 and above the device substrate 100, respectively. In addition, the insulating layer 302, the signal line SL2, the gate insulating layer 3GI, the interlayer insulating layer 3IL1, the interlayer insulating layer 3IL2, and the planarization layer 3PL in the device substrate 300 may be made of the same or similar materials as those of the corresponding ones of the device substrate 100 (i.e., the insulating layer 102, the signal line SL, the gate insulating layer GI, the interlayer insulating layer IL1, the interlayer insulating layer IL2, and the planarization layer PL), and therefore, the description thereof will not be repeated.

In addition, in the present embodiment, the pixel structure 40 includes an anisotropic conductive layer ACF1 and an anisotropic conductive layer ACF 2. Specifically, the anisotropic conductive layer ACF1 is disposed between the device substrate 100 and the device substrate 200, and the anisotropic conductive layer ACF2 is disposed between the device substrate 200 and the device substrate 300 for providing an electrical path. As shown in fig. 8, the light emitting device O2 can be electrically connected to the active device T2 through the anisotropic conductive layer ACF1, and the light emitting device O3 can be electrically connected to the active device T3 through the anisotropic conductive layer ACF1 and the anisotropic conductive layer ACF 2. Although fig. 8 and 9 disclose that the pixel structure 40 includes the anisotropic conductive layer ACF1 and the anisotropic conductive layer ACF2, the invention is not limited thereto. In other embodiments, the pixel structure 40 may not include an anisotropic conductive layer. For the rest, please refer to the foregoing embodiments, which are not described herein.

It is to be noted that, in the present embodiment, the organic encapsulation layer TFEb in the encapsulation structure layer TFE has the opening Q between the light-emitting layer E1 of the light-emitting element O1 and the light-emitting layer E2 of the light-emitting element O2, so that the pixel structure 40 has enhanced flexibility even if the pixel structure 40 has a plurality of element substrates 100 to 300 stacked on each other. Therefore, when the flexible display panel has the pixel structure 40, the flexible display panel has an improved bending degree, thereby increasing the applicability of the flexible display panel.

In addition, according to the above description of the position, number and outline of the opening Q in the pixel structure 10, those skilled in the art should understand that the position, number and outline of the opening Q in the pixel structure 40 are not limited to those depicted in fig. 6. In other words, the position, number and outline of the openings Q in the pixel structure 40 are not limited by the present invention.

As described above, the flexibility of the pixel structure 40 is increased due to the organic encapsulation layer TFEb having the opening Q, but the invention is not limited thereto. Hereinafter, other embodiments will be described with reference to fig. 10 and 11. It should be noted that the following embodiments follow the reference numerals and some contents of the foregoing embodiments, wherein the same or similar reference numerals are used to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

Fig. 10 is a schematic cross-sectional view of a pixel structure according to another embodiment of the invention. The position of the cross-section of fig. 10 may correspond to the position of the cross-section line II-II' in fig. 7. Referring to fig. 10 and 9, the pixel structure 50 of fig. 10 is similar to the pixel structure 40 of fig. 9, so the same or similar elements are denoted by the same or similar symbols, and descriptions of the same technical contents are omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments. Hereinafter, a description will be given of a difference between the pixel structure 50 of fig. 10 and the pixel structure 40 of fig. 9.

Referring to fig. 10, in the pixel structure 50, the element substrate 100 has an opening Y1 overlapping with the opening Q. Specifically, the opening Y1 penetrates through the surface F3 and the surface F4 of the device substrate 100 that are opposite to each other. In other words, in this embodiment, the opening Y1 is located in the insulating layer 102, the gate insulating layer GI, the interlayer insulating layer IL1, the interlayer insulating layer IL2, and the planarization layer PL. On the other hand, in the present embodiment, the opening Y1 is disposed in a region where no element or trace is provided in the element substrate 100.

In the pixel structure 50, the element substrate 200 has an opening Y2 overlapping with the opening Q and the opening Y1. Specifically, the opening Y2 penetrates through the surface F5 and the surface F6 of the device substrate 200 that are opposite to each other. In other words, in this embodiment, the opening Y2 is located in the insulating layer 202, the gate insulating layer 2GI, the interlayer insulating layer 2IL1, the interlayer insulating layer 2IL2, and the planarization layer 2 PL. On the other hand, in the present embodiment, the opening Y2 is disposed in a region where no element or trace is provided in the element substrate 200.

In the pixel structure 50, the element substrate 300 has an opening Y3 overlapping with the opening Q, the opening Y1, and the opening Y2. Specifically, the opening Y3 penetrates through the surface F7 and the surface F8 of the device substrate 300 that are opposite to each other. In other words, in this embodiment, the opening Y3 is located in the insulating layer 302, the gate insulating layer 3GI, the interlayer insulating layer 3IL1, the interlayer insulating layer 3IL2, and the planarization layer 3 PL. On the other hand, in the present embodiment, the opening Y3 is disposed in a region where no element or trace is provided in the element substrate 300.

In the pixel structure 50, the pixel defining layer PDL, the electrode layer CL, the inorganic sealing layer TFEa, the inorganic sealing layer TFEc, the anisotropic conductive layer ACF1, and the anisotropic conductive layer ACF2 have an opening Y4, an opening Y5, an opening Y6, an opening Y7, an opening Y8, and an opening Y9, respectively, which overlap with the opening Y1. In other words, in the present embodiment, the opening Y1, the opening Y2, the opening Y3, the opening Y4, the opening Y5, the opening Y6, the opening Y7, the opening Y8, and the opening Y9 together constitute a communication opening penetrating the pixel structure 50. In the present embodiment, the opening Y1, the opening Y2, the opening Y3, the opening Y4, the opening Y5, the opening Y6, the opening Y7, the opening Y8, and the opening Y9 completely overlap with each other, but the present invention is not limited thereto. In other embodiments, at least one of opening Y1, opening Y2, opening Y3, opening Y4, opening Y5, opening Y6, opening Y7, opening Y8, and opening Y9 may partially overlap the others.

In this embodiment, the pixel structure 50 includes the aperture Y1, the aperture Y2, the aperture Y3, the aperture Y4, the aperture Y5, the aperture Y6, the aperture Y7, the aperture Y8, and the aperture Y9 which overlap with the aperture Q, but the present invention is not limited thereto. In other embodiments, the pixel structure 50 may have one, two, three, four, five, six, seven or eight of the opening Y1, the opening Y2, the opening Y3, the opening Y4, the opening Y5, the opening Y6, the opening Y7, the opening Y8 and the opening Y9.

In addition, from the foregoing description on the position, number and outline of the openings Q in the pixel structure 10, those skilled in the art should understand that the present invention is not limited to the position, number and outline of the openings Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 and Y9. For the rest, please refer to the foregoing embodiments, which are not described herein.

It should be noted that, in addition to the opening Q in the organic encapsulation layer TFEb, the pixel structure 50 further has an opening Y1, an opening Y2, an opening Y3, an opening Y4, an opening Y5, an opening Y6, an opening Y7, an opening Y8, or an opening Y9, so that flexibility can be further improved. Therefore, when the flexible display panel has the pixel structure 50, the flexible display panel has an improved bending degree, thereby increasing the applicability of the flexible display panel.

Fig. 11 is a schematic cross-sectional view of a pixel structure according to another embodiment of the invention. The position of the cross-section of fig. 11 can be referred to the position of the cross-section line II-II' in fig. 7. Referring to fig. 11 and fig. 9, the pixel structure 60 of fig. 11 is similar to the pixel structure 40 of fig. 9, and the difference is mainly: in the pixel structure 60, the element substrate 100 has an opening Z1 and the package structure layer TFE6 has no opening; in the pixel structure 40, the package structure layer TFE has an opening Q and the element substrate 100 has no opening. The following description will be made regarding differences between the pixel structure 60 of fig. 11 and the pixel structure 40 of fig. 7, the same or similar elements are denoted by the same or similar symbols, and the description of the same technical contents is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments.

Referring to fig. 11, in the pixel structure 60, the encapsulation structure layer TFE6 includes an inorganic encapsulation layer TFE6a, an organic encapsulation layer TFE6b, and an inorganic encapsulation layer TFE6 c. In this embodiment mode, the inorganic encapsulating layer TFE6a covers the light emitting element O1 and the light emitting element O2 and is used for moisture, humidity, or the like. In this embodiment, the materials of the inorganic encapsulation layer TFE6a may include (but are not limited to): silicon nitride, aluminum oxide, or silicon oxynitride. In this embodiment, the organic encapsulation layer TFE6b is disposed on the inorganic encapsulation layer TFE6a to isolate impurities, particles, etc. generated in the process. In this embodiment, the materials of the organic encapsulation layer TFE6b may include (but are not limited to): acrylic, epoxy, or silicon oxycarbide. In this embodiment, the inorganic encapsulating layer TFE6c is disposed on the organic encapsulating layer TFE6b to isolate moisture, humidity, and the like. In this embodiment, the organic encapsulation layer TFE6b is located between the inorganic encapsulation layer TFE6a and the inorganic encapsulation layer TFE6 c. In this embodiment, the materials of the inorganic encapsulation layer TFE6c may include (but are not limited to): silicon nitride, aluminum oxide, or silicon oxynitride. The materials of the inorganic encapsulating layer TFE6a and the inorganic encapsulating layer TFE6c may be the same or different.

In the pixel structure 60, the element substrate 100 has an opening Z1. Specifically, the opening Z1 penetrates through the surface F3 and the surface F4 of the device substrate 100 that are opposite to each other. In other words, in this embodiment, the opening Z1 is located in the insulating layer 102, the gate insulating layer GI, the interlayer insulating layer IL1, the interlayer insulating layer IL2, and the planarization layer PL. On the other hand, in the present embodiment, the opening Z1 is disposed in a region where no element or trace is provided in the element substrate 100.

In the pixel structure 60, the element substrate 200 has an opening Z2 overlapping with the opening Z1. Specifically, the opening Z2 penetrates through the surface F5 and the surface F6 of the device substrate 200 that are opposite to each other. In other words, in this embodiment, the opening Z2 is located in the insulating layer 202, the gate insulating layer 2GI, the interlayer insulating layer 2IL1, the interlayer insulating layer 2IL2, and the planarization layer 2 PL. On the other hand, in the present embodiment, the opening Z2 is disposed in a region where no element or trace is provided in the element substrate 200.

In the pixel structure 60, the element substrate 300 has an opening Z3 overlapping with the openings Z1 and Z2. Specifically, the opening Z3 penetrates through the surface F7 and the surface F8 of the device substrate 300. In other words, in this embodiment, the opening Z3 is located in the insulating layer 302, the gate insulating layer 3GI, the interlayer insulating layer 3IL1, the interlayer insulating layer 3IL2, and the planarization layer 3 PL. On the other hand, in the present embodiment, the opening Z3 is disposed in a region where no element or trace is provided in the element substrate 300. In addition, as shown in fig. 11, in the present embodiment, the pixel definition layer PDL is disposed on the opening Z1, but the present invention is not limited thereto. In other embodiments, a portion of the pixel definition layer PDL may fill the opening Z1.

In the pixel structure 60, the anisotropic conductive layer ACF1 and the anisotropic conductive layer ACF2 have an opening Z4 and an opening Z5, respectively, which overlap with the opening Z1. In other words, in the present embodiment, the opening Z1, the opening Z2, the opening Z3, the opening Z4, and the opening Z5 together constitute a communication opening. In the present embodiment, the opening Z1, the opening Z2, the opening Z3, the opening Z4, and the opening Z5 completely overlap with each other, but the present invention is not limited thereto. In other embodiments, at least one of opening Z1, opening Z2, opening Z3, opening Z4, and opening Z5 may partially overlap the others.

In this embodiment, the pixel structure 60 includes the opening Z1, the opening Z2, the opening Z3, the opening Z4, and the opening Z5, but the present invention is not limited thereto. In other embodiments, the pixel structure 50 may have one, two, three, four, or five of the opening Z1, the opening Z2, the opening Z3, the opening Z4, and the opening Z5.

In this embodiment, the opening Z1, the opening Z2, the opening Z3, the opening Z4, and the opening Z5 are located between the light-emitting layer E1 of the light-emitting element O1 and the light-emitting layer E2 of the light-emitting element O2. Although fig. 11 discloses only a partial structure of the pixel structure 60, according to the foregoing descriptions regarding the pixel structure 40 of fig. 7 to 9 and the pixel structure 10 of fig. 1 to 3, especially regarding the position, number and outline of the opening Q, it should be understood by those skilled in the art that the present invention is not limited to the position, number and outline of the opening Z1, the opening Z2, the opening Z3, the opening Z4 and the opening Z5. For the rest, please refer to the foregoing embodiments, which are not described herein.

It should be noted that, in the present embodiment, the element substrate 100 has the opening Z1 penetrating the surface F3 and the surface F4, so that the pixel structure 60 has enhanced flexibility even if the pixel structure 60 has a plurality of element substrates 100 to 300 stacked on each other. On the other hand, in addition to the opening Z1 in the element substrate 100, the pixel structure 60 may further have an opening Z2, an opening Z3, an opening Z4, or an opening Z5, so that flexibility may be further improved. Therefore, when the flexible display panel has the pixel structure 60, the flexible display panel has an improved bending degree, thereby increasing the applicability of the flexible display panel.

In summary, in the pixel structure of at least one embodiment of the invention, the organic encapsulation layer has an opening between two adjacent light emitting layers, or the element substrate has openings penetrating through two surfaces thereof, so that the pixel structure has improved flexibility. Therefore, when the flexible display panel has the pixel structure, the flexible display panel has improved bending degree, and further the applicability of the flexible display panel is improved.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (6)

1. A pixel structure, comprising:

a first element substrate;

a first light emitting element and a second light emitting element which are adjacent to each other, are disposed on the first element substrate and electrically connected to the first element substrate, wherein the first light emitting element includes a first light emitting layer, and the second light emitting element includes a second light emitting layer;

a first inorganic encapsulation layer covering the first light emitting element and the second light emitting element;

an organic encapsulating layer disposed on the first inorganic encapsulating layer, wherein the organic encapsulating layer has a first opening between the first light emitting layer of the first light emitting device and the second light emitting layer of the second light emitting device, wherein the organic encapsulating layer is a patterned film;

a second inorganic encapsulation layer disposed on the organic encapsulation layer; and

and a second element substrate disposed below the first element substrate, wherein the first element substrate includes a first active element electrically connected to the first light-emitting element, and the second element substrate includes a second active element electrically connected to the second light-emitting element.

2. The pixel structure of claim 1, wherein the organic encapsulation layer has a first surface and a second surface disposed opposite to each other, and the first opening penetrates through the first surface and the second surface.

3. The pixel structure of claim 1, wherein the first device substrate has a third surface and a fourth surface disposed opposite to each other, the first device substrate has a second opening, and the second opening penetrates through the third surface and the fourth surface and overlaps with the first opening.

4. The pixel structure of claim 1, wherein the second device substrate has a fifth surface and a sixth surface disposed opposite to each other, the second device substrate has a third opening, and the third opening penetrates through the fifth surface and the sixth surface and overlaps with the first opening.

5. The pixel structure of claim 1,

a perpendicular projection of a first sidewall of the first opening adjacent to the first light-emitting element on the first element substrate is a first distance away from a perpendicular projection of an edge of the first light-emitting layer on the first element substrate, an

The first distance is greater than or equal to the thickness of the organic encapsulation layer.

6. A pixel structure, comprising:

a first element substrate having a first surface and a second surface opposite to each other and including a first opening, wherein the first opening penetrates through the first surface and the second surface;

a first light emitting element and a second light emitting element which are adjacent to each other and are disposed on the first element substrate and electrically connected to the first element substrate, wherein the first light emitting element includes a first light emitting layer, the second light emitting element includes a second light emitting layer, and the first opening is located between the first light emitting layer of the first light emitting element and the second light emitting layer of the second light emitting element;

a packaging structure layer covering the first light-emitting element and the second light-emitting element; and

and a second element substrate disposed below the first element substrate, wherein the first element substrate includes a first active element electrically connected to the first light-emitting element, and the second element substrate includes a second active element electrically connected to the second light-emitting element.

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