JPH0794679A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide an SOI(Semiconductor On Insulator) type semiconductor device having enhanced ESD(ElectroStatic Discharge) resistance. CONSTITUTION:The SOT type semiconductor device having a semiconductor surface layer on an insulating substrate comprises a pair of feeder lines 5, 6 formed on the semiconductor surface layer, a pair of low resistivity semiconductor regions 2a, 2b disposed in the surface layer while being connected with the pair of feeder lines, and a dielectric region 1a disposed between the pair of low resistivity semiconductor regions, wherein the pair of low resistivity semiconductor regions provide a capacitor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an SOI (semiconductor on insulator) type semiconductor device having improved electrostatic discharge (ESD) resistance.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, when static electricity enters from the outside through a pin or the like and is discharged in the circuit, the function of the semiconductor integrated circuit is often impaired. Below CMO
The S semiconductor integrated circuit will be described as an example.

3 (A) to 3 (C) show examples of ESD noise protection measures according to conventional techniques. FIG. 3A shows an ESD noise countermeasure circuit for the pad 50 receiving the input signal.

The pad 50 is set to p before connecting to the internal circuit.
Channel MOS transistor pMOS and n channel M
It is connected to a series circuit of OS transistors nMOS. A p-channel MOS transistor pMOS is connected between the power supply voltage V _DD and the signal line connected to the pad 50, and an n-channel MOS transistor nMOS is connected between the signal line connected to the pad 50 and the power supply voltage V _SS. Has been done.

The gate electrode of the pMOS is connected to the power supply voltage V _DD side (referred to as the source S), and the gate electrode of the nMOS is connected to the power supply voltage V _SS (source S). In such a circuit, the signal input to the pad 50 is V _SS
During the period between V _DD and V _DD , both pMOS and nMOS are turned off.

When a positive charge enters the pad 50 and its potential becomes higher than V _DD , the relationship between the source S and the drain D of the pMOS is reversed. Positive charges flow from the drain D side of the pMOS to the source S side and are absorbed by the power supply V _DD .

Negative charges enter the pad 50,
When the potential of the source voltage V _SS becomes equal to or lower than the power supply voltage V _SS , the relationship between the source S and the drain D of the nMOS is reversed, and the negative charge flows from the drain D to the source S and is absorbed by the power supply wiring V _SS .

FIG. 3B shows E as shown in FIG.
It is sectional drawing which shows the structural example of SD protection circuit. A p-type well 52 is formed in a substrate 51 such as n-type Si.
An n-channel MOS transistor is formed in well 52. That is, the n ⁺ type region 5 is formed in the p well 52.
3, 54 are formed, and the insulated gate electrode 55 is formed on the channel region defined between them.

In addition, in the p well 52, p⁺Mold area 56
Is formed. p⁺Mold regions 56 and n ⁺The mold region 53 is a game
Power supply voltage V together with the electrode 55_SSConnected to. While the other
n⁺The mold region 54 is connected to the pad 50. In this configuration
In addition, n⁺The mold region 53 is the source S shown in FIG.
And n⁺The mold region 54 becomes the drain D.

According to this structure, an n channel MOS transistor is formed in the p well 52, but at the same time, a bipolar transistor structure is also formed between the n ⁺ type region 54, the p well 52 and the n type substrate 51. .

As described above, when the potential of the pad 50 becomes lower than V _SS , the roles of the source S and the drain D are reversed, and negative charges flow from the drain 54 to the source 53. On the other hand, by adjusting the thickness and the impurity concentration between the n ⁺ type region 54 of the p well 52 and the region sandwiched by the substrate 51, a punch-through current flows from the n ⁺ type region 54 to the n type substrate 51. can do.

That is, when a negative charge invades the pad 50, a punch-through current flows from the n ⁺ region 54 to the substrate 51 as the negative potential of the pad 50 increases, and at the same time, nMO increases.
When S turns on, negative charges also flow from the n ⁺ type region 54 through the n ⁺ type region 53 to V _SS .

A similar ESD current flows when a pMOS transistor is formed in the n well region. However, the polarity is reversed. In addition to this, there is also a path that flows as a reverse diode current to the well 52 via the pn junction formed by the drain diffusion layer 54 and the p well 52.
In this case, if the ESD noise is negative charge, it flows to V _SS or the substrate via the drain junction of the nMOS, or pM
Flows to V _DD or the substrate through the source junction of the OS. In the case of positively charged noise, it is the same except that the drain / source is switched.

FIG. 3C shows a case where a similar structure is formed in the ultrathin film SOI-CMOS integrated circuit device. An insulating region 58 such as SiO ₂ is formed on a supporting substrate 59 such as a Si substrate, and an nMOS transistor is formed on this insulating region.

That is, n⁺The mold regions 53 and 54 face each other
And the p-channel 57 is arranged between them. p
An insulated gate electrode 55 is formed on the channel 57.
It n ⁺The mold region 53 and the insulated gate electrode 55 have a power source V_SSTo
Connected, n⁺The mold region 54 is connected to the pad 50.

In this structure, because of the SOI structure, n
No current flows from the MOS to the substrate 59. Therefore, nM
Although the OS exists, the bipolar transistor that exists accompanying the case of FIG. 3B does not exist.

Further, since there is no well, there is no pn diode below the drain diffusion layer.

When performing an ESD test, the V _DD or V _SS line may be left floating and charge may be applied to the input pad from the capacitor. In addition, when ESD noise is added under actual use conditions and charges escape to the V _DD line or V _SS line, both lines may be in a floating state and may not be absorbed. In such a case, charges cannot escape in the ultra-thin film SOI-CMOS circuit, and an ESD defect is likely to occur.

As measures against such ESD, a method of providing an opening in a part of the buried oxide film and a method of making a part of the SOI structure into a non-SOI structure (that is, a CMOS structure similar to the bulk) have been proposed. . According to these methods, it is possible to let the charges escape to the supporting substrate.

However, in order to provide an opening in a part of the buried oxide film, the number of processes is increased and an extra area is required. Further, if the SOI structure is a non-SOI structure, the SOI is
There are problems that the advantages of the structure are reduced, the number of processes is increased, and there is a possibility of disconnection of the wiring at the step portion.

[0021]

In the SOI type semiconductor device, there remains a problem to be solved as an ESD countermeasure.
An object of the present invention is to provide an SOI type semiconductor device having improved ESD resistance.

[0022]

The SOI type semiconductor device of the present invention is an SO having a semiconductor surface layer on an insulating support substrate.
An I-type semiconductor device comprising: a pair of power supply lines (5, 6) formed on a semiconductor surface layer; and a pair of power supply lines connected to the pair of power supply lines and arranged in the surface layer. A low resistivity semiconductor region (2a, 2b) and a dielectric region (1a) disposed between the pair of low resistivity semiconductor regions;
The pair of low resistance semiconductor regions form a capacitance.

[0023]

Since the capacitance is connected between the pair of power supply lines, the ESD failure is unlikely to occur even if the ESD noise enters the pad.

[0024]

1 shows the structure of an SOI type semiconductor device according to a basic embodiment of the present invention. 1A is a schematic partial cross-sectional view of an SOI semiconductor device, and FIG. 1B is a partial circuit diagram of the SOI semiconductor device.

In FIG. 1A, low resistivity semiconductor regions 2a and 2b are formed in an insulating region 1 on the surface of a supporting substrate of an SOI type semiconductor device. A V _SS line 5 and a V _DD line 6 are connected to the low resistivity semiconductor regions 2a and 2b, respectively.

The low-resistivity semiconductor regions 2a and 2b are separated by a dielectric region 1a, and the surface thereof is covered with an insulating film 4. Contact holes 7a and 7b are formed in the insulating film 4, and the V _SS line 5 and the V _DD line 6 are in contact with the low resistivity semiconductor regions 2a and 2b, respectively.

A capacitance C is formed between the low resistivity semiconductor regions 2a and 2b. This capacitance is equivalent to the low resistivity semiconductor region 2
a and 2b may be arranged in close proximity to each other and may be formed directly with the dielectric region 1a interposed therebetween, and the low-resistivity semiconductor regions 2a and 2b may be respectively formed via the SOI insulating region 1 and the capacitor formed with the supporting semiconductor substrate. You may form it.

Although not shown in FIG. 1A, the other parts of this SOI semiconductor device have the same p
A series connection of MOS and nMOS is formed, and the power supply line V
Connected between _SS and V _DD .

FIG. 1B shows an equivalent circuit of such an ESD protection circuit. The pads 10a, 10b, 10c include
The power supply voltage V _DD , the input signal, and the power supply voltage V _SS are applied respectively.

A pMOS 11a is connected between the line connected to the pad 10a and a line connected to the pad 10b, and an nMOS 11b is connected between the pads 10b and 10c.
Are connected. Further, the capacitor C is connected between the lines connected to the pads 10a and 10c.

When ESD noise is incident on the pad 10b, electric charges are generated depending on the polarity of the ESD noise.
Flows to the line connected to 0c. Where the pad 10
Since the capacitance C is connected between the lines connected to a and 10c, the incident electric charge is absorbed by the capacitance C.

FIG. 2 shows an example of a manufacturing method for forming two semiconductor regions buried in an insulating region as shown in FIG. In FIG. 2A, masks 13a and 13b made of resist or the like are formed on a bonding substrate 12 for forming a semiconductor device.

As shown in FIG. 2B, the reactive ion etching (R) is performed using these masks 13a and 13b.
By performing etching such as IE), the mask 13
The protruding semiconductor regions 12a and 12b are left under a and 13b. After that, the masks 13a and 13b are removed.

As shown in FIG. 2C, Si is formed on the bonding substrate 12 on which the protrusions are formed by CVD or the like.
An insulating film 14 such as O ₂ and a polycrystalline semiconductor layer 15 such as polycrystalline Si are deposited. In the state immediately after the deposition, the polycrystalline semiconductor layer 15 has a surface having irregularities, but by polishing this surface, a flat surface as shown in the figure is obtained.

Next, as shown in FIG. 2D, a supporting substrate 16 such as a Si substrate is prepared, and the bonded substrate 1 is bonded so that the polycrystalline semiconductor layer 15 is bonded to the surface of the supporting substrate 16.
Place 2.

In this state, the supporting substrate 16 and the bonding substrate 12 are adhered by being kept at a high temperature of about 1000 ° C., for example. The bonding process can be simplified and stabilized by using voltage and pressure together with temperature.

As shown in FIG. 2 (E), after laminating, the laminated substrate 12 is polished from the upper side in the drawing to
Only the protrusions 12a and 12b are left. In this state, the semiconductor regions 12a and 12b formed on the bonding substrate 12 are left in the insulating film 14 in a separated state.

The semiconductor regions 12a and 12b are doped with impurities at a high concentration at any stage. In this way, the low resistivity semiconductor region shown in FIG. 1A is formed.

A large number of semiconductor regions embedded in the insulating film are formed by the same method, and pMOS,
An nMOS or the like can be formed. An insulating film is formed on the SOI structure thus formed, contact holes are formed, and then a wiring layer is formed, whereby the semiconductor structure shown in FIG. 1A is obtained.

In the structure shown in FIG. 2 (E),
The semiconductor regions 12a and 12b face the polycrystalline semiconductor layer 15 formed on the support substrate 16 with the insulating film 14 interposed therebetween. That is, the semiconductor regions 12a and 12b also form a capacitance with the supporting substrate.

Various shapes are possible as the shape of the semiconductor region forming the capacitance for ESD protection. FIG. 4 shows a planar configuration example of an ESD protection capacitor according to an embodiment of the present invention. The low resistivity semiconductor region 23 arranged in the insulating region 25 is
From the common backbone part, three branch parts 23a, 23b, 2
3c has a projecting shape. Similarly, the other semiconductor regions 24 arranged in the insulating region 25 also have a shape in which three branch-shaped portions 24a, 24b, and 24c project from the common backbone portion.

The semiconductor region 23 and the semiconductor region 24 are arranged in an interdigital form such that the branch portions 23a to 23c and 24a to 24c thereof are engaged with each other.
The semiconductor region 23 is connected to the V _SS line 21, and the semiconductor region 24 is connected to the V _DD line 22.

By adopting such an interdigital shape, the facing area between the semiconductor region 23 and the semiconductor 24 increases, and the capacitance of the capacitance formed increases.
FIG. 5 shows an arrangement example in which a capacitor having the structure shown in FIG. 4 is arranged on an integrated circuit chip. An integrated circuit portion is formed in the central portion of the semiconductor chip 20, and pads are formed in the peripheral portion. V between the central circuit and the peripheral pads
_{The SS} line 21 and the V _DD line 22 are arranged so as to surround the central region.

The ESD protection circuit 2 as shown in FIG. 4 is provided at a plurality of places between the V _SS line 21 and the V _DD line 22.
6 is arranged. In the configuration shown, three ESDs
The protection circuits 26a, 26b, 26c are shown. By disposing the capacitors in a distributed manner, the protection function for the entire power supply line is made uniform.

The number of ESD protection circuits can be increased or decreased as necessary. Further, the ESD protection circuit can be formed over the entire length of the V _SS line 21 and the V _DD line 22 facing each other.

In the ultra-thin SOI type CMOS circuit,
The semiconductor layers forming the semiconductor device are, for example, about 0.
It is made extremely thin with 1 μm. In such a case, the area of the side surface of the semiconductor region forming the capacitance becomes smaller according to the thickness. In order to increase the capacitance, it is sufficient to reduce the thickness of the dielectric layer between the semiconductor regions, but if it is too thin, the breakdown voltage will be insufficient.

For example, when a dielectric layer of SiO ₂ is used, a dielectric region having a thickness of about 0.5 μm is left between opposing semiconductor regions. It is necessary to secure the thickness of the dielectric layer between the semiconductor regions so that the leakage current is negligible and the dielectric breakdown does not occur. As one measure, a dielectric layer having a minimum exposure line width is used.

The ESD noise is generated by the human body or the like, but a voltage of about 500 V is typically generated. ES like this
In order to reduce the D voltage, it is desirable that the capacitance be large. FIG. 6 shows a planar shape suitable for further increasing the capacitance of the capacitance formed between the semiconductor regions.

The semiconductor region 23 has two branch portions 23.
a, 23b and two similar branch portions 24a, 24
It is arranged so as to face the semiconductor region 24 having b. These branch portions 23a, 23b and 24a, 24b are arranged so as to interlock with each other in an interdigital shape.

Further, in each of the opposed branch portions, a protruding portion 28 further protruding from the branch portion 23a is formed, and a protruding region 27 protruding from the branch portion 24 is also formed, and the protruding portions 28 are alternately engaged with each other. Are arranged as follows. These protrusions 27 and 28 allow the semiconductor region 23,
The peripheral length of the opposing portion of 24 increases.

That is, the areas of the side surfaces of the semiconductor regions 23 and 24 are increased. By arranging the increased side surfaces to face each other, the capacitance of the capacitance formed between them also increases.

FIG. 7 shows an ESD according to another embodiment of the present invention.
An example of arrangement of protection capacitors is shown. The semiconductor regions 23 and 24 are two-dimensionally and alternately arranged to form a checkered pattern. A dielectric region is arranged around each semiconductor region 23, 24.

On these semiconductor regions, power supply wirings 21a, 21b, 21c and 21d are obliquely provided as shown in the figure.
And 22a, 22b, 22c, ... Are alternately arranged. That is, the semiconductor region 23 is connected to the V _SS line 21, and the semiconductor region 24 is connected to the V _DD line 22.
Therefore, each semiconductor region 23, 24 is surrounded by a semiconductor region connected to another power supply line, and a capacitance is formed on all side surfaces thereof.

In the present embodiment, by reducing the area of the main surface of each semiconductor region and making contact with the power supply line from the main surface side, the capacitance is increased and the voltage drop in the semiconductor region can be almost ignored. It is also possible to do so.

Since the ESD noise has a high voltage, if the conductive region has a sharp edge, a discharge is likely to occur at the sharp edge. FIG. 8 shows a configuration example of an ESD protection capacitor having a high breakdown voltage according to another embodiment of the present invention. A circular semiconductor region 24 and a ring-shaped semiconductor region 23 surrounding it are formed in the insulating region, and a capacitance is formed between them.

A V _SS line 21 and a V _DD line 22 are arranged on these semiconductor regions with an insulating film _interposed therebetween, and a ring-shaped semiconductor region 23 and a circular semiconductor region are provided with a contact hole 28 formed in the insulating film interposed therebetween. Ohmic contact with 24.

In this structure, the semiconductor regions 23 and 2 are
There is no protrusion on the opposing surface of No. 4, and the breakdown voltage is improved. Therefore, it is possible to reduce the thickness of the dielectric region between the semiconductor regions 23 and 24.

Note that these semiconductor regions do not necessarily have to be circular, and may have any shape such as an elliptical shape or an oval shape that forms a gentle curve. When one of the power supply wirings has a ground potential, it is preferable to arrange the ground potential outside.

In the SOI type structure, the semiconductor layers formed on the surface layer can form a capacitance between them, and when a semiconductor substrate is used as a support substrate, a capacitance is also formed between the semiconductor substrate and the support substrate.

FIG. 9 shows an SOI according to another embodiment of the present invention.
An example of the configuration of the ESD protection capacitor of the semiconductor device of the present invention is shown. The insulating film 25 is arranged on the supporting Si substrate 29, and the semiconductor regions 23 and 24 are arranged in the insulating film 25. The semiconductor regions 23 and 24 face the support substrate 29 via a part of the insulating film 25, and form capacitors C1 and C2.

The surfaces of the semiconductor regions 23 and 24 are covered with the insulating film 3
Covered by 1. The contact hole 2 is formed in the insulating film 31.
8 is formed to expose a part of the semiconductor regions 23 and 24. V _SS line 2 to cover these contact holes
1, V _DD line 22 is formed. That is, the EDS formed by the semiconductor region 23, the support substrate 29, and the semiconductor region 24 is provided between the V _SS line 21 and the V _DD line 22.
The protection capacitor is connected.

In FIG. 1 (A) and FIGS. 4 to 9, ES is shown.
Although only the capacitance portion for the D protection circuit is shown, a MOS transistor structure as shown in FIG. 3C is formed on the same semiconductor chip to form an ESD protection circuit as shown in FIG. 1B. . As the ESD protection capacitor, the configurations shown in FIGS. 1, 4 to 8 and the configuration shown in FIG. 9 can be combined or combined.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example,
It will be apparent to those skilled in the art that various changes, improvements, combinations and the like can be made.

[0064]

As described above, according to the present invention,
An SOI semiconductor device having improved ESD resistance is provided without complicating the manufacturing process.

[Brief description of drawings]

FIG. 1 is a sectional view and a circuit diagram showing a basic embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device shown in FIG.

FIG. 3 is a circuit diagram and a cross-sectional view for explaining a conventional technique.

FIG. 4 is a plan view showing a planar shape of an ESD protection capacitor according to an exemplary embodiment of the present invention.

FIG. 5 is a plan view showing an arrangement of ESD protection capacitors in a chip.

FIG. 6 is a plan view showing a planar shape of an ESD protection capacitor according to an exemplary embodiment of the present invention.

FIG. 7 is a plan view showing a planar shape of an ESD protection capacitor according to an exemplary embodiment of the present invention.

FIG. 8 is a plan view showing a planar shape of an ESD protection capacitor according to an exemplary embodiment of the present invention.

FIG. 9 is a cross-sectional view schematically showing a structure of an ESD protection capacitor according to an embodiment of the present invention.

[Explanation of symbols]

1 Insulation Region 2 Low Resistivity Semiconductor Region 3 Insulation Film 5 _VSS Line 6 V _DD Line 7 Contact Hole 10 Pad 11 MOS Transistor 12 Bonding Substrate 13 Mask 14 Insulation Film 15 Polycrystalline Semiconductor Layer 16 Support Substrate 21, 22 Power Supply Wiring 23, 24 Semiconductor region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/092 27/12 K

Claims (9)

[Claims] 1. An SOI semiconductor device having a semiconductor surface layer on an insulating support substrate, comprising a pair of power supply lines (5, 5) formed on the semiconductor surface layer.
6), a pair of low resistivity semiconductor regions (2a, 2b) connected to the pair of power supply lines and disposed in the surface layer, and disposed between the pair of low resistivity semiconductor regions. And a dielectric region (1a), wherein the pair of low resistance semiconductor regions form a capacitance. 2. The SOI semiconductor device according to claim 1, wherein the supporting substrate includes a semiconductor substrate, and an insulating layer continuous with the dielectric region is formed on a surface of the semiconductor substrate. 3. The pair of low resistivity semiconductor regions (2a, 2a,
The SOI type semiconductor device according to claim 2, wherein 2b) face each other on the side surface thereof via the dielectric region (1a) to form a capacitor. 4. The SOI semiconductor device according to claim 3, wherein a plurality of pairs of the pair of low resistivity semiconductor regions are provided and connected to a common pair of power supply lines. 5. The SOI semiconductor device according to claim 3, wherein the pair of low-resistivity semiconductor regions has an interdigital portion in a shape projected onto the surface of the support substrate. 6. The outer edges of the pair of low-resistivity semiconductor regions do not have bent portions forming an angle of 90 degrees or less.
The SOI semiconductor device according to any one of 1. 7. The SOI semiconductor device according to claim 3, wherein one of the pair of low resistivity semiconductor regions has a shape surrounding the other. 8. The SOI type semiconductor device according to claim 4, wherein the pair of low-resistivity semiconductor regions are arranged in a checkered pattern, and the pair of power supply lines are alternately connected. 9. The SOI according to claim 2, wherein the pair of low resistivity semiconductor regions form a capacitance via the semiconductor substrate.
Type semiconductor device.