CN217114392U - Pixel structure for reducing capacitance of touch line - Google Patents

Pixel structure for reducing capacitance of touch line Download PDF

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CN217114392U
CN217114392U CN202220812806.0U CN202220812806U CN217114392U CN 217114392 U CN217114392 U CN 217114392U CN 202220812806 U CN202220812806 U CN 202220812806U CN 217114392 U CN217114392 U CN 217114392U
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metal layer
insulating layer
pixel
electrode
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张桂瑜
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CPT Technology Group Co Ltd
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CPT Technology Group Co Ltd
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Abstract

The utility model discloses a pixel structure for reducing capacitance of a touch line, which comprises a substrate, and a first metal layer, a grid electrode insulating layer, a semiconductor layer, a second metal layer, a first insulating layer, a third metal layer, an organic layer, a second insulating layer, a common electrode, a third insulating layer and a pixel electrode which are arranged on the substrate from bottom to top in sequence; the organic layer is prepared behind the third metal layer, so that the organic layer and the second insulating layer are arranged between the third layer of metal serving as the touch line and the common electrode, the thickness of the organic layer is 5-10 times that of the second insulating layer, the distance between the touch line (the third layer of metal) and the common electrode is increased, the capacitance between the touch line (the third layer of metal) and the common electrode is reduced, and the total capacitance of the touch line (TP line) is also reduced. The utility model discloses touch line total capacitance has reduced 38.7%. And the touch sensitivity is improved.

Description

Pixel structure for reducing capacitance of touch line
Technical Field
The utility model relates to a show technical field, especially relate to a reduce pixel structure of touch-control line capacitance.
Background
For the product of tic (touch in panel), i.e. the touch screen line (TP line for short), a three-layer metal design is adopted, i.e. the touch line is prepared from a third layer of metal (M3). For the previous design, M3 is fabricated after an Organic layer (OC), as shown in fig. 1, and both Top COM and Mid COM architectures are suitable. Take the pixel of Mid COM architecture as an example. For the MID COM architecture, only one insulating layer is sandwiched between the touch line and the common electrode, and the thickness of the insulating layer is 0.2-0.5 um; for the TOP COM architecture, only two layers of insulating layers and one layer of pixel electrode are sandwiched between the touch line and the common electrode, the thickness is 0.4 um-1 um, and the distance between the touch line and the common electrode is too close, so that the capacitance between the touch line and the common electrode is too large.
Disclosure of Invention
An object of the utility model is to provide a reduce pixel structure of touch-control line capacitance.
The utility model adopts the technical proposal that:
a pixel structure for reducing capacitance of a touch line comprises a substrate, and a first metal layer, a grid electrode insulating layer, a semiconductor layer, a second metal layer, a first insulating layer, a third metal layer, an organic layer, a second insulating layer, a common electrode, a third insulating layer and a pixel electrode which are sequentially arranged on the substrate from bottom to top; the first metal layer covers part of the upper surface of the substrate and is used as a grid electrode of the thin film transistor, namely a scanning line; the grid insulation layer completely covers the first metal layer and a non-first metal layer covering area on the substrate; the semiconductor layer is arranged on the grid electrode insulating layer and corresponds to the first metal layer, and the semiconductor layer is used as a channel of the thin film transistor; the semiconductor layer is provided with a second metal layer, the second metal layer forms a source electrode and a drain electrode of the thin film transistor on the upper surfaces of the two sides of the semiconductor layer respectively, the source electrode of the thin film transistor is a data line, and the first insulating layer is arranged on the second metal layer and isolates the second metal layer;
the third metal layer is arranged on the upper surface of the first insulating layer, and the third metal layer is a touch line; the common electrode is arranged on the upper surface of the second insulating layer and corresponds to the third metal layer region;
and pixel through holes are correspondingly formed in the vertical directions of the third insulating layer, the second insulating layer, the organic layer and the first insulating layer between the pixel electrode and the second metal layer, and the pixel electrode is arranged in the pixel through hole and is in contact with a region serving as a drain electrode of the thin film transistor in the second metal layer through the pixel through hole.
Further, a drain electrode of the thin film transistor partially covers the upper surface area on the semiconductor layer side, and another portion of the drain electrode of the thin film transistor covers the gate insulating layer.
Further, the material of the gate insulating layer is one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide.
A method for preparing a pixel structure for reducing the capacitance of a touch line comprises the following steps:
step 1, providing a substrate, and manufacturing a first metal layer on part of the upper surface of the substrate;
step 2, manufacturing a grid electrode insulating layer to completely cover the first metal layer and a non-first metal layer covering area on the substrate;
step 3, manufacturing a semiconductor layer on the grid insulation layer corresponding to the first metal layer;
step 4, manufacturing a second metal layer on the semiconductor layer, and etching a pattern on the second metal layer to form a source electrode and a drain electrode of the thin film transistor on the upper surfaces of the two sides of the semiconductor layer respectively;
step 5, manufacturing a first insulating layer on the second metal layer, completely covering and isolating the second metal layer, and manufacturing a pixel through hole at the position of the first insulating layer corresponding to the drain electrode of the thin film transistor;
step 6, manufacturing a third metal layer on the first insulating layer;
step 7, manufacturing an organic layer to cover the upper surfaces of the third metal layer and the first insulating layer, and developing the organic layer to expose the pixel through hole;
step 8, manufacturing second insulating layers on the organic layer corresponding to the two side areas of the pixel through hole;
step 9, manufacturing a common electrode on the upper surface of the second insulating layer corresponding to the third metal layer region;
step 10, manufacturing third insulating layers in the areas on two sides of the pixel through hole, wherein the third insulating layers are stacked on the second insulating layers and cover the common electrode;
and 11, manufacturing a pixel electrode in the pixel through hole, wherein the pixel electrode partially penetrates through the pixel through hole to be in contact with a region serving as a drain electrode of the thin film transistor in the second metal layer.
Further, the material of the first insulating layer is silicon oxide (SiOx) or silicon nitride (SiNx) or a combination of the two.
Further, in step 8, the two side portions of the second insulating layer corresponding to the pixel via hole are covered on the first insulating layer.
A pixel structure for reducing capacitance of a touch line comprises a substrate, and a first metal layer, a grid electrode insulating layer, a semiconductor layer, a second metal layer, a first insulating layer, a third metal layer, a second insulating layer, an organic layer, a common electrode, a third insulating layer and a pixel electrode which are sequentially arranged on the substrate from bottom to top; the first metal layer covers part of the upper surface of the substrate and is used as a grid electrode of the thin film transistor, namely a scanning line; the grid insulation layer completely covers the first metal layer and a non-first metal layer covering area on the substrate; the semiconductor layer is arranged on the grid electrode insulating layer and corresponds to the first metal layer, and the semiconductor layer is used as a channel of the thin film transistor; the semiconductor layer is provided with a second metal layer, the second metal layer forms a source electrode and a drain electrode of the thin film transistor on the upper surfaces of the two sides of the semiconductor layer respectively, the source electrode of the thin film transistor is a data line, and the first insulating layer is arranged on the second metal layer and isolates the second metal layer;
the third metal layer is arranged on the upper surface of the first insulating layer, and the third metal layer is a touch line; the common electrode is arranged on the upper surface of the organic layer and corresponds to the third metal layer region;
and pixel through holes are correspondingly formed in the vertical directions of the third insulating layer, the second insulating layer, the organic layer and the first insulating layer between the pixel electrode and the second metal layer, and the pixel electrode is arranged in the pixel through hole and is in contact with a region serving as a drain electrode of the thin film transistor in the second metal layer through the pixel through hole.
Further, a drain electrode of the thin film transistor partially covers the upper surface area on the semiconductor layer side, and another portion of the drain electrode of the thin film transistor covers the gate insulating layer.
Further, the material of the gate insulating layer is one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide.
A method for preparing a pixel structure for reducing the capacitance of a touch line comprises the following steps:
step 1, providing a substrate, and manufacturing a first metal layer on part of the upper surface of the substrate;
step 2, manufacturing a grid electrode insulating layer to completely cover the first metal layer and a non-first metal layer covering area on the substrate;
step 3, manufacturing a semiconductor layer on the grid insulation layer corresponding to the first metal layer;
step 4, manufacturing a second metal layer on the semiconductor layer, and etching a pattern on the second metal layer to form a source electrode and a drain electrode of the thin film transistor on the upper surfaces of the two sides of the semiconductor layer respectively;
step 5, manufacturing a first insulating layer on the second metal layer, completely covering and isolating the second metal layer, and manufacturing a pixel through hole at the position of the first insulating layer corresponding to the drain electrode of the thin film transistor;
step 6, manufacturing a third metal layer on the first insulating layer;
step 7, manufacturing a second insulating layer to cover the upper surfaces of the third metal layer and the first insulating layer;
step 8, manufacturing an organic layer on the second insulating layer, and developing the organic layer to expose the pixel through hole;
step 9, manufacturing a common electrode on the upper surface of the organic layer corresponding to the third metal layer region;
step 10, manufacturing third insulating layers in the areas on two sides of the pixel through hole, wherein the third insulating layers are stacked on the organic layer and cover the common electrode;
and 11, manufacturing a pixel electrode in the pixel through hole, wherein the pixel electrode partially penetrates through the pixel through hole to be in contact with a region serving as a drain electrode of the thin film transistor in the second metal layer.
Further, the material of the first insulating layer adopts silicon oxide (SiOx) or silicon nitride (SiNx) or a combination of the two.
Further, in step 10, two side portions of the third insulating layer corresponding to the pixel via hole are covered on the second insulating layer.
The utility model adopts the above technical scheme, exchange the processing procedure order of organic layer and third metal level, will have the organic layer preparation after the third metal level for increase the organic layer of one deck between touch-control line and the common electrode, and have the organic layer generally thicker, about 2um, the thickness of insulating layer generally is 0.2~0.5um, and the organic layer thickness is 5~10 times of one deck insulating layer. Therefore, the distance between the touch line and the common electrode is increased, the capacitance between the touch line and the common electrode is reduced, and the total capacitance of the touch line is also reduced.
Drawings
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments;
FIG. 1 is a cross-sectional view of a pixel structure in the prior art;
fig. 2 is a schematic cross-sectional view of a pixel structure according to embodiment 1 of the present invention;
fig. 3 is a schematic cross-sectional view of a pixel structure according to embodiment 2 of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
Example 1: as shown in fig. 2, the utility model discloses a pixel structure for reducing capacitance of touch line, which comprises a substrate, and a first metal layer 2, a gate insulating layer 3, a semiconductor layer 4, a second metal layer, a first insulating layer 7, a third metal layer 9, an organic layer 8, a second insulating layer 10, a common electrode 11, a third insulating layer 12 and a pixel electrode 13 which are sequentially arranged on the substrate 1 from bottom to top; the first metal layer 2 covers partial area of the upper surface of the substrate 1, and the first metal layer 2 is used as a grid electrode of the thin film transistor, namely a scanning line; the gate insulating layer 3 completely covers the first metal layer 2 and the area on the substrate 1 not covered by the first metal layer 2; the semiconductor layer 4 is arranged on the grid insulating layer 3 corresponding to the first metal layer 2, and the semiconductor layer 4 is used as a channel of the thin film transistor; a second metal layer is arranged on the semiconductor layer 4, a source electrode 5 and a drain electrode 6 of the thin film transistor are respectively formed on the upper surfaces of the two sides of the semiconductor layer 4 by the second metal layer, the source electrode 5 of the thin film transistor is a data line, and the first insulating layer 7 is arranged on the second metal layer and isolates the second metal layer;
the third metal layer 9 is arranged on the upper surface of the first insulating layer 7, and the third metal layer 9 is a touch line; the common electrode 11 is disposed on the upper surface of the second insulating layer 10 corresponding to the third metal layer 9.
Pixel via holes are correspondingly arranged in the vertical direction of the third insulating layer 12, the second insulating layer 10, the organic layer 8 and the first insulating layer 7 between the pixel electrodes 13 and the second metal layer, and the pixel electrodes 13 are arranged in the pixel via holes and are in contact with the region serving as the thin film transistor drain electrodes 6 in the second metal layer through the pixel via holes.
Further, the drain electrode 6 of the thin film transistor partially covers the upper surface area on the side of the semiconductor layer 4, and another part of the drain electrode 6 of the thin film transistor covers the gate insulating layer 3.
Further, the material of the gate insulating layer 3 is one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide.
A method for preparing a pixel structure for reducing the capacitance of a touch line comprises the following steps:
step 1, providing a substrate 1, and manufacturing a first metal layer 2 on part of the upper surface of the substrate 1;
step 2, manufacturing a grid insulation layer 3 to completely cover the first metal layer 2 and a non-first metal layer 2 covering area on the substrate 1;
step 3, manufacturing a semiconductor layer 4 on the grid insulation layer 3 corresponding to the position of the first metal layer 2;
step 4, manufacturing a second metal layer on the semiconductor layer 4, and etching a pattern on the second metal layer to form a source electrode 5 and a drain electrode 6 of the thin film transistor on the upper surfaces of the two sides of the semiconductor layer 4 respectively;
step 5, manufacturing a first insulating layer 7 on the second metal layer, completely covering and isolating the second metal layer, and manufacturing a pixel through hole at the position of the first insulating layer 7 corresponding to the drain electrode 6 of the thin film transistor;
step 6, manufacturing a third metal layer 9 on the first insulating layer 7;
step 7, manufacturing an organic layer 8 to cover the upper surfaces of the third metal layer 9 and the first insulating layer 7, and developing the organic layer 8 to expose pixel through holes;
step 8, manufacturing second insulating layers 10 on the organic layer 8 corresponding to the two side areas of the pixel through hole;
step 9, manufacturing a common electrode 11 on the upper surface of the second insulating layer 10 in a region corresponding to the third metal layer 9;
step 10, manufacturing third insulating layers 12 in the areas on two sides of the pixel via hole, wherein the third insulating layers 12 are laminated on the second insulating layer 10 and cover the common electrode 11;
and 11, manufacturing a pixel electrode in the pixel through hole, wherein the pixel electrode partially penetrates through the pixel through hole to be in contact with a region serving as the drain electrode 6 of the thin film transistor in the second metal layer.
Further, the material of the first insulating layer 7 is silicon oxide (SiOx) or silicon nitride (SiNx), or a combination of the two.
Further, in step 8, the second insulating layer 10 covers the first insulating layer 7 corresponding to the two side portions of the pixel via.
Example 2: as shown in fig. 3, a pixel structure for reducing capacitance of a touch line includes a substrate 1, and a first metal layer 2, a gate insulating layer 3, a semiconductor layer 4, a second metal layer, a first insulating layer 7, a third metal layer 9, a second insulating layer 10, an organic layer 8, a common electrode 11, a third insulating layer 12, and a pixel electrode 13 sequentially disposed on the substrate 1 from bottom to top; the first metal layer 2 covers partial area of the upper surface of the substrate 1, and the first metal layer 2 is used as a grid electrode of the thin film transistor, namely a scanning line; the gate insulating layer 3 completely covers the first metal layer 2 and the area on the substrate 1 not covered by the first metal layer 2; the semiconductor layer 4 is arranged on the grid insulating layer 3 corresponding to the first metal layer 2, and the semiconductor layer 4 is used as a channel of the thin film transistor; a second metal layer is arranged on the semiconductor layer 4, a source electrode 5 and a drain electrode 6 of the thin film transistor are respectively formed on the upper surfaces of the two sides of the semiconductor layer 4 by the second metal layer, the source electrode of the thin film transistor is a data line, and the first insulating layer 7 is arranged on the second metal layer and isolates the second metal layer;
the third metal layer 9 is arranged on the upper surface of the first insulating layer 7 and corresponds to the source electrode 5 area of the thin film transistor, and the third metal layer 9 is a touch line; the common electrode 11 is arranged on the upper surface of the organic layer 8 and corresponds to the area of the third metal layer 9;
pixel via holes are correspondingly arranged in the vertical direction of the third insulating layer 12, the second insulating layer 10, the organic layer 8 and the first insulating layer 7 between the pixel electrodes 13 and the second metal layer, and the pixel electrodes 13 are arranged in the pixel via holes and are in contact with the region serving as the thin film transistor drain electrodes 6 in the second metal layer through the pixel via holes. The pixel electrode 13 is connected to the drain electrode 6 of the thin film transistor.
Further, the drain electrode 6 of the thin film transistor partially covers the upper surface area on the side of the semiconductor layer 4, and another part of the drain electrode 6 of the thin film transistor covers the gate insulating layer 3.
Further, the material of the gate insulating layer 3 is one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide.
A method for preparing a pixel structure for reducing the capacitance of a touch line comprises the following steps:
step 1, providing a substrate 1, and manufacturing a first metal layer 2 on part of the upper surface of the substrate 1;
step 2, manufacturing a grid insulation layer 3 to completely cover the first metal layer 2 and a non-first metal layer 2 covering area on the substrate 1;
step 3, manufacturing a semiconductor layer 4 on the grid insulation layer 3 corresponding to the position of the first metal layer 2;
step 4, manufacturing a second metal layer on the semiconductor layer 4, and etching a pattern on the second metal layer to form a source electrode 5 and a drain electrode 6 of the thin film transistor on the upper surfaces of the two sides of the semiconductor layer 4 respectively;
step 5, manufacturing a first insulating layer 7 on the second metal layer, completely covering and isolating the second metal layer, and manufacturing a pixel through hole at the position of the first insulating layer 7 corresponding to the drain electrode 6 of the thin film transistor;
step 6, manufacturing a third metal layer 9 on the first insulating layer 7;
step 7, manufacturing a second insulating layer 10 to cover the upper surfaces of the third metal layer 9 and the first insulating layer 7;
step 8, manufacturing an organic layer 8 on the second insulating layer 10, and developing the organic layer 8 to expose the pixel through hole;
step 9, manufacturing a common electrode 11 on the upper surface of the organic layer 8 in a region corresponding to the third metal layer 9;
step 10, manufacturing third insulating layers 12 in the areas on two sides of the pixel through hole, wherein the third insulating layers 12 are laminated on the organic layer 8 and cover the common electrode 11;
and 11, manufacturing a pixel electrode in the pixel through hole, wherein the pixel electrode partially penetrates through the pixel through hole to be in contact with a region serving as the drain electrode 6 of the thin film transistor in the second metal layer.
Further, the material of the first insulating layer 7 is silicon oxide (SiOx) or silicon nitride (SiNx), or a combination of the two.
Further, in step 10, portions of the third insulating layer 12 corresponding to two sides of the pixel via hole are covered on the second insulating layer 10.
The utility model discloses to the product of TIC (touch in Panel), touch screen line (TP line for short) promptly on the panel, adopt the design of three-layer metal, the framework of touch line with third layer metal preparation promptly. Both Top COM and Mid COM architectures are suitable. Taking 11 inches panel as an example, the utility model discloses touch-control line total capacitance for the previous example has reduced 38.7%. The touch sensitivity can be improved.
The utility model adopts the above technical scheme, exchange organic layer 8 and third metal level M3's processing procedure order, will have organic layer 8 to prepare after the third metal level, make increase one deck organic layer 8 between touch-control line and the sharing electrode 11, and organic layer 8 is generally thicker, about 2 mu M, the thickness of insulating layer is generally at 0.2~0.5 mu M, organic layer 8 thickness is 5~10 times of one deck insulating layer, thickness is at 2.2~2.5 mu M, make the distance increase between touch-control line and the sharing electrode 11 like this, electric capacity between touch-control line and the sharing electrode 11 reduces, the total electric capacity of touch-control line also reduces.
It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. The embodiments and features of the embodiments in the present application may be combined with each other without conflict. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the detailed description of the embodiments of the present application is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Claims (8)

1. A pixel structure for reducing capacitance of a touch line is characterized in that: the organic light-emitting diode comprises a substrate, and a first metal layer, a grid electrode insulating layer, a semiconductor layer, a second metal layer, a first insulating layer, a third metal layer, an organic layer, a second insulating layer, a common electrode, a third insulating layer and a pixel electrode which are sequentially arranged on the substrate from bottom to top; the first metal layer covers part of the upper surface of the substrate and is used as a grid electrode of the thin film transistor, namely a scanning line; the grid insulation layer completely covers the first metal layer and a non-first metal layer covering area on the substrate; the semiconductor layer is arranged on the grid electrode insulating layer and corresponds to the first metal layer, and the semiconductor layer is used as a channel of the thin film transistor; the semiconductor layer is provided with a second metal layer, the second metal layer forms a source electrode and a drain electrode of the thin film transistor on the upper surfaces of the two sides of the semiconductor layer respectively, the source electrode of the thin film transistor is a data line, and the first insulating layer is arranged on the second metal layer and isolates the second metal layer;
the third metal layer is arranged on the upper surface of the first insulating layer, and the third metal layer is a touch line; the common electrode is arranged on the upper surface of the second insulating layer and corresponds to the third metal layer region;
and pixel through holes are correspondingly formed in the vertical directions of the third insulating layer, the second insulating layer, the organic layer and the first insulating layer between the pixel electrode and the second metal layer, and the pixel electrode is arranged in the pixel through hole and is in contact with a region serving as a drain electrode of the thin film transistor in the second metal layer through the pixel through hole.
2. The pixel structure of claim 1, wherein: the drain electrode of the thin film transistor partially covers the upper surface area on one side of the semiconductor layer, and the other part of the drain electrode of the thin film transistor partially covers the gate insulating layer.
3. The pixel structure of claim 1, wherein: the gate insulating layer is made of one of silicon oxide, silicon nitride, silicon oxynitride and aluminum oxide.
4. The pixel structure of claim 1, wherein: the second insulating layer covers the first insulating layer corresponding to the two side parts of the pixel via hole.
5. A pixel structure for reducing capacitance of a touch line is characterized in that: the organic light-emitting diode comprises a substrate, and a first metal layer, a grid electrode insulating layer, a semiconductor layer, a second metal layer, a first insulating layer, a third metal layer, a second insulating layer, an organic layer, a common electrode, a third insulating layer and a pixel electrode which are sequentially arranged on the substrate from bottom to top; the first metal layer covers part of the upper surface of the substrate and is used as a grid electrode of the thin film transistor, namely a scanning line; the grid insulating layer completely covers the first metal layer and a non-first metal layer covering area on the substrate; the semiconductor layer is arranged on the grid electrode insulating layer and corresponds to the first metal layer, and the semiconductor layer is used as a channel of the thin film transistor; the semiconductor layer is provided with a second metal layer, the second metal layer forms a source electrode and a drain electrode of the thin film transistor on the upper surfaces of the two sides of the semiconductor layer respectively, the source electrode of the thin film transistor is a data line, and the first insulating layer is arranged on the second metal layer and isolates the second metal layer;
the third metal layer is arranged on the upper surface of the first insulating layer, and the third metal layer is a touch line; the common electrode is arranged on the upper surface of the organic layer and corresponds to the third metal layer region;
and pixel through holes are correspondingly formed in the vertical directions of the third insulating layer, the second insulating layer, the organic layer and the first insulating layer between the pixel electrode and the second metal layer, and the pixel electrode is arranged in the pixel through hole and is in contact with a region serving as a drain electrode of the thin film transistor in the second metal layer through the pixel through hole.
6. The pixel structure of claim 5, wherein: the drain electrode of the thin film transistor partially covers the upper surface area on one side of the semiconductor layer, and the other part of the drain electrode of the thin film transistor partially covers the gate insulating layer.
7. The pixel structure of claim 5, wherein: the gate insulating layer is made of one of silicon oxide, silicon nitride, silicon oxynitride and aluminum oxide.
8. The pixel structure of claim 5, wherein: the third insulating layer covers the second insulating layer corresponding to the two side portions of the pixel via hole.
CN202220812806.0U 2022-04-08 2022-04-08 Pixel structure for reducing capacitance of touch line Active CN217114392U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202220812806.0U CN217114392U (en) 2022-04-08 2022-04-08 Pixel structure for reducing capacitance of touch line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202220812806.0U CN217114392U (en) 2022-04-08 2022-04-08 Pixel structure for reducing capacitance of touch line

Publications (1)

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CN217114392U true CN217114392U (en) 2022-08-02

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