CN215896391U - Display panel and display device - Google Patents
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- CN215896391U CN215896391U CN202121334072.1U CN202121334072U CN215896391U CN 215896391 U CN215896391 U CN 215896391U CN 202121334072 U CN202121334072 U CN 202121334072U CN 215896391 U CN215896391 U CN 215896391U
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Abstract
The embodiment of the application provides a display panel and a display device. The display panel includes: a substrate; the low-temperature polycrystalline silicon thin film transistor is arranged on the substrate and comprises a first active layer, a first grid electrode, a first source electrode and a first drain electrode, wherein a first grid electrode insulating layer and a first interlayer insulating layer are sequentially stacked and covered on the first active layer; the oxide thin film transistor comprises a second active layer, a second grid electrode and a second source electrode, wherein the second source electrode and the second active layer are arranged on the same layer, and a second grid electrode insulating layer and a second interlayer insulating layer are sequentially stacked and covered on the second active layer; and the pixel electrode is connected with the second active layer through a first through hole, and the first through hole penetrates through the second gate insulating layer and the second interlayer insulating layer.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
With the development of the application technology of the OLED (Organic Light-Emitting Diode) in the display screen, people have higher and higher requirements for Low power consumption performance of the display device, and an LTPS (Low Temperature polysilicon) display technology which drives TFTs and switches TFTs and can realize lower energy consumption gradually becomes mainstream.
However, in the current display panel adopting the LTPO technology, the film structure of the display area is complicated, and thus the manufacturing process of the product is also complicated. This presents a significant challenge to both the cost of manufacturing and the yield of the product.
SUMMERY OF THE UTILITY MODEL
An object of the present invention is to provide a display panel, a method for manufacturing the display panel, and a display device, so as to reduce the process complexity of the product, thereby reducing the cost of the product and improving the yield of the product.
The specific technical scheme is as follows:
an embodiment of a first aspect of the present application provides a display panel, including:
a substrate;
the low-temperature polycrystalline silicon thin film transistor is arranged on the substrate and comprises a first active layer, a first grid electrode, a first source electrode and a first drain electrode, wherein a first grid electrode insulating layer and a first interlayer insulating layer are sequentially stacked and covered on the first active layer;
the oxide thin film transistor comprises a second active layer, a second grid electrode and a second source electrode, wherein the second source electrode and the second active layer are arranged on the same layer, and a second grid electrode insulating layer and a second interlayer insulating layer are sequentially stacked and covered on the second active layer;
and the pixel electrode is connected with the second active layer through a first through hole, and the first through hole penetrates through the second gate insulating layer and the second interlayer insulating layer.
In some embodiments, a planarization layer is disposed between the pixel electrode and the second interlayer insulating layer, and the first via hole further penetrates the planarization layer.
In some embodiments, the second gate electrode is disposed on a side of the second gate insulating layer facing away from the second active layer, and the second interlayer insulating layer covers the second gate electrode;
and a light shielding layer is arranged on one side of the first gate insulating layer, which is far away from the substrate, and the light shielding layer is arranged opposite to the second active layer.
In some embodiments, the second gate electrode is disposed on a side of the first gate insulating layer facing away from the substrate, the second active layer is disposed on a side of the first interlayer insulating layer facing away from the first gate insulating layer, and the second gate electrode and the second active layer are oppositely disposed.
In some embodiments, the second gate electrode is disposed on a side of the first gate insulating layer facing away from the substrate, the second active layer is disposed on a side of the first interlayer insulating layer facing away from the first gate insulating layer, and the second gate electrode and the second active layer are oppositely disposed;
the oxide thin film transistor further comprises a third grid electrode, the third grid electrode is arranged on one side, away from the substrate, of the second grid insulation layer, and the third grid electrode is connected with the second grid electrode through a second through hole penetrating through the first interlayer insulation layer and the second grid insulation layer.
In some embodiments, the first source and the first drain are disposed on a side of the first interlayer insulating layer facing away from the first gate insulating layer, the first source is connected to the first active layer through a third via, the first drain is connected to the first active layer through a fourth via, and the first source, the first drain, and the second active layer are disposed on the same layer.
An embodiment of a second aspect of the present application provides a display panel, including:
a substrate;
the low-temperature polycrystalline silicon thin film transistor is arranged on the substrate and comprises a first active layer, a first grid electrode, a first source electrode and a first drain electrode, wherein a first grid electrode insulating layer and a first interlayer insulating layer are sequentially stacked and covered on the first active layer;
the oxide thin film transistor comprises a second active layer, a second grid electrode and a second source electrode, wherein the second source electrode and the second active layer are arranged on the same layer, and a second grid electrode insulating layer and a second interlayer insulating layer are sequentially stacked and covered on the second active layer;
the pixel electrode is connected with the switching electrode, the switching electrode is made of transparent metal oxide, the switching electrode is connected with the second active layer through a first through hole, and the first through hole penetrates through the second grid insulating layer and the second interlayer insulating layer.
In some embodiments, a planarization layer is disposed between the pixel electrode and the second interlayer insulating layer, a second via hole is disposed on the planarization layer, and the pixel electrode is connected to the transfer electrode through the second via hole.
In some embodiments, the second gate electrode is disposed on a side of the second gate insulating layer facing away from the second active layer, and the second interlayer insulating layer covers the second gate electrode;
and a light shielding layer is arranged on one side of the first gate insulating layer, which is far away from the substrate, and the light shielding layer is arranged opposite to the second active layer.
In some embodiments, the second gate electrode is disposed on a side of the first gate insulating layer facing away from the substrate, the second active layer is disposed on a side of the first interlayer insulating layer facing away from the first gate insulating layer, and the second gate electrode and the second active layer are oppositely disposed.
In some embodiments, the second gate electrode is disposed on a side of the first gate insulating layer facing away from the substrate, the second active layer is disposed on a side of the first interlayer insulating layer facing away from the first gate insulating layer, and the second gate electrode and the second active layer are oppositely disposed;
the oxide thin film transistor further comprises a third grid electrode, the third grid electrode is arranged on one side, away from the substrate, of the second grid insulation layer, and the third grid electrode is connected with the second grid electrode through a second through hole penetrating through the first interlayer insulation layer and the second grid insulation layer.
In some embodiments, the first source and the first drain are disposed on a side of the first interlayer insulating layer facing away from the first gate insulating layer, the first source is connected to the first active layer through a third via, the first drain is connected to the first active layer through a fourth via, and the first source, the first drain, and the second active layer are disposed on the same layer.
Embodiments of a third aspect of the present application propose a display device including the display panel in any of the embodiments of the first aspect.
Embodiments of a fourth aspect of the present application propose a display device including the display panel in any of the embodiments of the second aspect.
The embodiment of the application has the following beneficial effects:
in the display panel and the display device provided by the embodiment of the application, the display panel comprises the low-temperature polysilicon thin film transistor and the oxide thin film transistor, and the display panel adopts the LTPO technology. In the display panel of the embodiment of the present application, the second source electrode and the second active layer of the oxide thin film transistor are disposed on the same layer, so that the second source electrode can be directly connected to the second active layer without connecting the second source electrode to the second active layer by disposing a via hole as in the prior art. Therefore, compared with the display panel adopting the LTPO technology in the prior art, the display panel in the embodiment of the application reduces the number of the through holes, so that the complexity of the manufacturing process of the product is reduced, the manufacturing cost of the product is reduced, and the yield of the product is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and it is also obvious for a person skilled in the art to obtain other embodiments according to the drawings.
Fig. 1 is a schematic cross-sectional view of a display panel in an embodiment of a first aspect of the present application;
FIG. 2 is a schematic top view of a partial structure (including only oxide thin film transistor portions) of a display panel according to an embodiment of the first aspect of the present application;
FIG. 3 is a schematic cross-sectional view of another display panel in an embodiment of the first aspect of the present application;
FIG. 4 is a schematic cross-sectional view of another display panel in an embodiment of the first aspect of the present application;
FIG. 5 is a schematic cross-sectional view of a display panel according to an embodiment of the second aspect of the present application;
FIG. 6 is a schematic cross-sectional view of another display panel in an embodiment of the second aspect of the present application;
fig. 7 is a schematic cross-sectional view of another display panel in an embodiment of the second aspect of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the description herein are intended to be within the scope of the present disclosure.
As shown in fig. 1 to 4, an embodiment of a first aspect of the present application proposes a display panel 10. The display panel 10 includes a substrate 100, a low temperature polysilicon thin film transistor 200, an oxide thin film transistor 300, and a pixel electrode 400. Specifically, the low temperature polysilicon thin film transistor 200 is disposed on the substrate 100, the low temperature polysilicon thin film transistor 200 includes a first active layer 210, a first gate electrode 220, a first source electrode 230, and a first drain electrode 240, and a first gate insulating layer 500 and a first interlayer insulating layer 600 are sequentially stacked and covered on the first active layer 210. The oxide thin film transistor 300 includes a second active layer 310, a second gate electrode 320, and a second source electrode 330. Wherein the second active layer 310 may be disposed on a side of the first interlayer insulating layer 600 facing away from the first gate insulating layer 500. The second source electrode 330 and the second active layer 310 are disposed at the same layer, and the second gate insulating layer 700 and the second interlayer insulating layer 800 are sequentially stacked and covered on the second active layer 310. The pixel electrode 400 is connected to the second active layer 310 through a first via hole 1100, and the first via hole 1100 penetrates the second gate insulating layer 700 and the second interlayer insulating layer 800.
The display panel 10 according to the embodiment of the present application, which includes the low temperature polysilicon thin film transistor 200 and the oxide thin film transistor 300, is the display panel 10 using the LTPO technology. Specifically, in the display panel 10 of the embodiment of the present application, the second source electrode 330 of the oxide thin film transistor 300 and the second active layer 310 are disposed on the same layer, so that the second source electrode 330 can be directly connected to the second active layer 310 without connecting the second source electrode 330 to the second active layer 310 by providing a via hole as in the prior art. In addition, the pixel electrode 400 is connected to the second active layer 310 through the first via hole 1100, thereby eliminating the drain electrode of the oxide thin film transistor 300, and thus reducing the via hole connecting the drain electrode to the active layer of the oxide thin film transistor 300. Therefore, compared with the display panel 10 adopting the LTPO technology in the prior art, the display panel 10 in the embodiment of the present invention reduces the number of the via holes, so that the complexity of the manufacturing process of the product can be reduced, the manufacturing cost of the product can be reduced, and the yield of the product can be improved. In addition, since the pixel electrode 400 is usually made of transparent metal oxide, and the source and the drain of the oxide thin film transistor 300 are usually made of opaque metal, the pixel electrode 400 in this embodiment is directly connected to the second active layer 310 of the oxide thin film transistor 300, so as to replace the drain, which is also beneficial to improving the aperture ratio and the light transmittance of the display panel 10, and further improving the display effect of the product.
Further, the first active layer 210 is a low temperature polysilicon layer, and the second active layer 310 is an indium gallium zinc oxide layer.
In some embodiments of the present application, the planarization layer 1500 is disposed between the pixel electrode 400 and the second interlayer insulating layer 800, that is, the pixel electrode 400 may be formed on the planarization layer 1500. Further, the first via hole 1100 also penetrates through the planarization layer 1500, that is, the first via hole 1100 penetrates through the planarization layer 1500, the second interlayer insulating layer 800 and the second gate insulating layer 700 at the same time, so that the first via hole 1100 for connecting the pixel electrode 400 and the second active layer 310 can be formed through one hole processing procedure, which is beneficial to simplifying the product process.
In some embodiments of the present application, as shown in fig. 1, the second gate electrode 320 is disposed on a side of the second gate insulating layer 700 facing away from the second active layer 310, and the second interlayer insulating layer 800 covers the second gate electrode 320. In this case, the oxide thin film transistor 300 has a top gate structure. Further, based on the top gate structure of the oxide thin film transistor 300, a light shielding layer 900 is disposed on a side of the first gate insulating layer away from the substrate 100, and the light shielding layer 900 is disposed opposite to the second active layer 310 to shield the second active layer 310 from light.
In other embodiments of the present application, as shown in fig. 3, the second gate electrode 320 is disposed on a side of the first gate insulating layer facing away from the substrate 100, the second active layer 310 is disposed on a side of the first interlayer insulating layer 600 facing away from the first gate insulating layer, and the second gate electrode 320 and the second active layer 310 are disposed opposite to each other. In this case, the oxide thin film transistor 300 has a bottom gate structure. Since the gate of the oxide thin film transistor 300 is usually made of opaque metal, in the case that the oxide thin film transistor 300 adopts a bottom gate structure, the second gate 320 can function to block light from the second active layer 310, and thus the light blocking layer 900 can be omitted.
In some other embodiments of the present application, as shown in fig. 4, the second gate electrode 320 is disposed on a side of the first gate insulating layer facing away from the substrate 100, the second active layer 310 is disposed on a side of the first interlayer insulating layer 600 facing away from the first gate insulating layer, and the second gate electrode 320 and the second active layer 310 are disposed opposite to each other. The oxide thin film transistor 300 further comprises a third gate electrode 340, the third gate electrode 340 is disposed on a side of the second gate insulating layer facing away from the substrate 100, and the third gate electrode 340 is connected to the second gate electrode 320 through a second via 1200 passing through the first interlayer insulating layer 600 and the second gate insulating layer 700. In this case, the oxide thin film transistor 300 has a double gate structure (having both a top gate and a bottom gate). Since the gate of the oxide thin film transistor 300 is usually a non-light-transmissive metal, the second gate 320 can function to block light from the second active layer 310, and thus the light blocking layer 900 can be omitted.
In some embodiments of the present application, the first source electrode 230 and the first drain electrode 240 of the low temperature polysilicon thin film transistor 200 are disposed on a side of the first interlayer insulating layer 600 facing away from the first gate insulating layer 500, the first source electrode 230 is connected to the first active layer 210 through the third via 1300, the first drain electrode 240 is connected to the first active layer 210 through the fourth via 1400, and the first source electrode 230, the first drain electrode 240 and the second active layer 310 are disposed on the same layer. In the present embodiment, the first source electrode 230 and the first drain electrode 240 of the ltps tft 200 are disposed on the same layer as the second active layer 310 of the oxide tft 300, the first source electrode 230 is connected to the first active layer 210 through the third via 1300, and the first drain electrode 240 is connected to the first active layer 210 through the fourth via 1400, so that the third via 1300 and the fourth via 1400 penetrate through the first interlayer insulating layer 600 and the first gate insulating layer 500 without penetrating through the second gate insulating layer 700. In the display panel 10 using LTPO technology in the related art, the source and drain electrodes of the low temperature polysilicon tft 200 are mostly disposed on the second gate insulating layer 700. Therefore, in the display panel 10 of the present embodiment, the arrangement positions of the first source 230 and the first drain 240 of the low temperature polysilicon thin film transistor 200 are optimized, so that the number of layers of the layer structure penetrated by the third via 1300 and the fourth via 1400 can be reduced, and the complexity of the manufacturing process of the product is further reduced.
In some embodiments of the present application, the substrate 100 may include a glass substrate and a buffer layer disposed on the glass substrate.
In some embodiments of the present application, the first interlayer insulating layer 600 may be a layer including SiO2Layer, SiN layer and SiO2Three-layer stack of layers, in which the SiO of the bottom layer2The thickness of the layer is
The thickness of the SiN layer is
SiO of the top layer2The thickness of the layer is
In some embodiments of the present applicationIn (e), the second interlayer insulating layer 800 may be SiO2Layer of thickness
As shown in fig. 5 to 7, the embodiment of the second aspect of the present application proposes a display panel 10, which is different from the display panel 10 of the embodiment of the first aspect only in that the pixel electrode 400 is not directly connected to the second active layer 310 of the oxide thin film transistor 300, but is connected to the second active layer 310 of the oxide thin film transistor 300 through the via electrode 1000 made of transparent metal oxide.
Specifically, the display panel 10 in the embodiment of the second aspect includes a substrate 100, a low temperature polysilicon thin film transistor 200, an oxide thin film transistor 300, and a pixel electrode 400. The low temperature polysilicon thin film transistor 200 is disposed on the substrate 100, the low temperature polysilicon thin film transistor 200 includes a first active layer 210, a first gate 220, a first source 230, and a first drain 240, and a first gate insulating layer 500 and a first interlayer insulating layer 600 are sequentially stacked and covered on the first active layer 210. The oxide thin film transistor 300 includes a second active layer 310, a second gate electrode 320, and a second source electrode 330, the second source electrode 330 and the second active layer 310 are disposed in the same layer, and a second gate insulating layer 700 and a second interlayer insulating layer 800 are sequentially stacked and covered on the second active layer 310. The pixel electrode 400 is connected to the via electrode 1000, the via electrode 1000 is a transparent metal oxide, the via electrode 1000 is connected to the second active layer 310 through a first via hole 1100, and the first via hole 1100 penetrates through the second gate insulating layer 700 and the second interlayer insulating layer 800.
According to the display panel 10 of the embodiment of the present application, the second source electrode 330 of the oxide thin film transistor 300 and the second active layer 310 are disposed on the same layer, so that the second source electrode 330 can be directly connected to the second active layer 310 without connecting the second source electrode 330 to the second active layer 310 by providing a via hole as in the prior art. As can be seen, compared with the display panel 10 adopting the LTPO technology in the prior art, the display panel 10 in the embodiment of the present disclosure reduces the number of the via holes, so that the complexity of the manufacturing process of the product can be reduced, the manufacturing cost of the product can be reduced, and the yield of the product can be improved. In addition, the pixel electrode 400 is connected to the transfer electrode 1000 made of transparent metal oxide, and the transfer electrode 1000 is connected to the second active layer 310 through the first through hole, so that a drain electrode in the oxide thin film transistor 300 is eliminated, and since the drain electrode is usually an opaque metal, the present embodiment is advantageous to improve the aperture ratio and the light transmittance of the display panel 10 by replacing the drain electrode with the transfer electrode 1000, thereby improving the display effect of the product.
In some embodiments of the present application, the planarization layer 1500 is disposed between the pixel electrode 400 and the second interlayer insulating layer 800, that is, the pixel electrode 400 may be formed on the planarization layer 1500. Further, a fifth via 1600 is disposed on the planarization layer 1500, and the pixel electrode 400 is connected to the via electrode 1000 through the fifth via 1600.
In some embodiments of the present application, as shown in fig. 5, the second gate electrode 320 is disposed on a side of the second gate insulating layer 700 facing away from the second active layer 310, and the second interlayer insulating layer 800 covers the second gate electrode 320. In this case, the oxide thin film transistor 300 has a top gate structure. Further, based on the top gate structure of the oxide thin film transistor 300, a light shielding layer 900 is disposed on a side of the first gate insulating layer away from the substrate 100, and the light shielding layer 900 is disposed opposite to the second active layer 310 to shield the second active layer 310 from light.
In still other embodiments of the present application, as shown in fig. 6, the second gate electrode 320 is disposed on a side of the first gate insulating layer facing away from the substrate 100, the second active layer 310 is disposed on a side of the first interlayer insulating layer 600 facing away from the first gate insulating layer, and the second gate electrode 320 and the second active layer 310 are disposed opposite to each other. In this case, the oxide thin film transistor 300 has a bottom gate structure. Since the gate of the oxide thin film transistor 300 is usually made of opaque metal, in the case that the oxide thin film transistor 300 adopts a bottom gate structure, the second gate 320 can function to block light from the second active layer 310, and thus the light blocking layer 900 can be omitted.
In some other embodiments of the present application, as shown in fig. 7, the second gate electrode 320 is disposed on a side of the first gate insulating layer facing away from the substrate 100, the second active layer 310 is disposed on a side of the first interlayer insulating layer 600 facing away from the first gate insulating layer, and the second gate electrode 320 and the second active layer 310 are disposed opposite to each other. The oxide thin film transistor 300 further comprises a third gate electrode 340, the third gate electrode 340 is disposed on a side of the second gate insulating layer facing away from the substrate 100, and the third gate electrode 340 is connected to the second gate electrode 320 through a second via 1200 passing through the first interlayer insulating layer 600 and the second gate insulating layer 700. In this case, the oxide thin film transistor 300 has a double gate structure (having both a top gate and a bottom gate). Since the gate of the oxide thin film transistor 300 is usually a non-light-transmissive metal, the second gate 320 can function to block light from the second active layer 310, and thus the light blocking layer 900 can be omitted.
In some embodiments of the present application, the first source electrode 230 and the first drain electrode 240 of the low temperature polysilicon thin film transistor 200 are disposed on a side of the first interlayer insulating layer 600 facing away from the first gate insulating layer 500, the first source electrode 230 is connected to the first active layer 210 through the third via 1300, the first drain electrode 240 is connected to the first active layer 210 through the fourth via 1400, and the first source electrode 230, the first drain electrode 240 and the second active layer 310 are disposed on the same layer. In the present embodiment, the first source electrode 230 and the first drain electrode 240 of the ltps tft 200 are disposed on the same layer as the second active layer 310 of the oxide tft 300, the first source electrode 230 is connected to the first active layer 210 through the third via 1300, and the first drain electrode 240 is connected to the first active layer 210 through the fourth via 1400, so that the third via 1300 and the fourth via 1400 penetrate through the first interlayer insulating layer 600 and the first gate insulating layer 500 without penetrating through the second gate insulating layer 700. In the display panel 10 using LTPO technology in the related art, the source and drain electrodes of the low temperature polysilicon tft 200 are mostly disposed on the second gate insulating layer 700. Therefore, in the display panel 10 of the present embodiment, the arrangement positions of the first source 230 and the first drain 240 of the low temperature polysilicon thin film transistor 200 are optimized, so that the number of layers of the layer structure penetrated by the third via 1300 and the fourth via 1400 can be reduced, and the complexity of the manufacturing process of the product is further reduced.
Embodiments of the third aspect of the present application propose a display device including the display panel 10 in the embodiments of the first aspect described above.
According to the display device in the embodiment, since the same inventive concept as the display panel 10 in the embodiment of the first aspect, the display device in the embodiment of the present application can obtain all the advantageous effects of the display panel 10 in the embodiment of the first aspect.
An embodiment of a fourth aspect of the present application proposes a display device including the display panel 10 in the embodiment of the second aspect.
According to the display device in the embodiment, since the same inventive concept as the display panel 10 in the embodiment of the second aspect, the display device in the embodiment of the present application can obtain all the advantageous effects of the display panel 10 in the embodiment of the second aspect.
An embodiment of the fifth aspect of the present application provides a manufacturing method of a display panel 10, including the following steps:
forming a first active layer 210 of the low temperature polysilicon thin film transistor 200 on the substrate 100;
forming a first gate insulating layer 500 and a first interlayer insulating layer 600 on the first active layer 210;
processing a third via hole 1300 and a fourth via hole 1400 on the first interlayer insulating layer 600 and the first gate insulating layer 500, and forming a first source electrode 230 connected to the first active layer 210 through the third via hole 1300 and a first drain electrode 240 connected to the first active layer 210 through the fourth via hole 1400 on the first interlayer insulating layer 600;
forming a second active layer 310 of the oxide thin film transistor 300 and a second source electrode 330 connected to the second active layer 310 on the first interlayer insulating layer 600;
forming a second gate insulating layer 700 and a second interlayer insulating layer 800 on the second active layer 310 and the second source electrode 330;
forming a planarization layer 1500 on the second interlayer insulating layer 800;
processing a first via hole 1100 on the planarization layer 1500, the second interlayer insulating layer 800, and the second gate insulating layer 700;
the pixel electrode 400 connected to the second active layer 310 through the first via hole 1100 is formed on the planarization layer 1500.
According to the method for manufacturing the display panel 10 of the embodiment of the application, in the process of manufacturing the oxide thin film transistor 300, the second active layer 310 of the oxide thin film transistor 300 and the second source electrode 330 connected to the second active layer 310 are formed on the first interlayer insulating layer 600, so that a via hole for connecting the second source electrode 330 and the second active layer 310 does not need to be processed as in the prior art, thereby reducing the complexity of the manufacturing process of the display panel 10. In addition, the pixel electrode 400 formed by the manufacturing method in the embodiment of the present application is directly connected to the second active layer 310 through the first via 1100, so that the drain electrode in the oxide thin film transistor 300 is eliminated, and the via processing process for connecting the drain electrode to the active layer of the oxide thin film transistor 300 is omitted, thereby reducing the complexity of the manufacturing process of the display panel 10.
In some embodiments of the present application, the step of forming the first gate insulating layer 500 and the first interlayer insulating layer 600 on the first active layer 210 includes:
forming a first gate insulating layer 500 on the first active layer 210;
forming a first gate electrode 220 of the low temperature polysilicon thin film transistor 200 on the first gate insulating layer 500, and forming a light shielding layer 900 on the first gate insulating layer 500, the light shielding layer 900 being for shielding the second active layer 310 from light;
a first interlayer insulating layer 600 covering the first gate electrode 220 and the light blocking layer 900 is formed on the first gate insulating layer 500.
An embodiment of the sixth aspect of the present application provides a method for manufacturing a display panel 10, including:
forming a first active layer 210 of the low temperature polysilicon thin film transistor 200 on the substrate 100;
forming a first gate insulating layer 500 and a first interlayer insulating layer 600 on the first active layer 210;
processing a third via hole 1300 and a fourth via hole 1400 on the first interlayer insulating layer 600 and the first gate insulating layer 500, and forming a first source electrode 230 connected to the first active layer 210 through the third via hole 1300 and a first drain electrode 240 connected to the first active layer 210 through the fourth via hole 1400 on the first interlayer insulating layer 600;
forming a second active layer 310 of the oxide thin film transistor 300 and a second source electrode 330 connected to the second active layer 310 on the first interlayer insulating layer 600;
forming a second gate insulating layer 700 and a second interlayer insulating layer 800 on the second active layer 310 and the second source electrode 330;
processing a first via hole 1100 on the second interlayer insulating layer 800 and the second gate insulating layer 700;
forming a via electrode 1000 made of a transparent metal oxide connected to the second active layer 310 through the first via hole 1100 on the second interlayer insulating layer 800;
a planarization layer is formed on the second interlayer insulating layer 800 and the transfer electrode 1000;
processing a second via 1200 in the planarization layer 1500;
the pixel electrode 400 connected to the transfer electrode 1000 through the second via hole 1200 is formed on the planarization layer 1500.
According to the method for manufacturing the display panel 10 of the embodiment of the application, in the process of manufacturing the oxide thin film transistor 300, the second active layer 310 of the oxide thin film transistor 300 and the second source electrode 330 connected to the second active layer 310 are formed on the first interlayer insulating layer 600, so that a via hole for connecting the second source electrode 330 and the second active layer 310 does not need to be processed as in the prior art, thereby reducing the complexity of the manufacturing process of the display panel 10.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is only for the preferred embodiment of the present application and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application are included in the protection scope of the present application.
Claims (9)
1. A display panel, comprising:
a substrate;
the low-temperature polycrystalline silicon thin film transistor is arranged on the substrate and comprises a first active layer, a first grid electrode, a first source electrode and a first drain electrode, wherein a first grid electrode insulating layer and a first interlayer insulating layer are sequentially stacked and covered on the first active layer;
the oxide thin film transistor comprises a second active layer, a second grid electrode and a second source electrode, wherein the second source electrode and the second active layer are arranged on the same layer, and a second grid electrode insulating layer and a second interlayer insulating layer are sequentially stacked and covered on the second active layer;
and the pixel electrode is connected with the second active layer through a first through hole, and the first through hole penetrates through the second gate insulating layer and the second interlayer insulating layer.
2. The display panel according to claim 1, wherein a planarization layer is provided between the pixel electrode and the second interlayer insulating layer, and wherein the first via hole further penetrates the planarization layer.
3. A display panel, comprising:
a substrate;
the low-temperature polycrystalline silicon thin film transistor is arranged on the substrate and comprises a first active layer, a first grid electrode, a first source electrode and a first drain electrode, wherein a first grid electrode insulating layer and a first interlayer insulating layer are sequentially stacked and covered on the first active layer;
the oxide thin film transistor comprises a second active layer, a second grid electrode and a second source electrode, wherein the second source electrode and the second active layer are arranged on the same layer, and a second grid electrode insulating layer and a second interlayer insulating layer are sequentially stacked and covered on the second active layer;
the pixel electrode is connected with the switching electrode, the switching electrode is made of transparent metal oxide, the switching electrode is connected with the second active layer through a first through hole, and the first through hole penetrates through the second grid insulating layer and the second interlayer insulating layer.
4. The display panel according to claim 3, wherein a planarization layer is provided between the pixel electrode and the second interlayer insulating layer, wherein a second via hole is provided in the planarization layer, and wherein the pixel electrode is connected to the transfer electrode through the second via hole.
5. The display panel according to claim 1 or 3, wherein the second gate electrode is provided on a side of the second gate insulating layer facing away from the second active layer, and wherein the second interlayer insulating layer covers the second gate electrode;
and a light shielding layer is arranged on one side of the first gate insulating layer, which is far away from the substrate, and the light shielding layer is arranged opposite to the second active layer.
6. The display panel according to claim 1 or 3, wherein the second gate electrode is provided on a side of the first gate insulating layer facing away from the substrate, wherein the second active layer is provided on a side of the first interlayer insulating layer facing away from the first gate insulating layer, and wherein the second gate electrode and the second active layer are provided in opposition.
7. The display panel according to claim 1 or 3, wherein the second gate electrode is provided on a side of the first gate insulating layer facing away from the substrate, wherein the second active layer is provided on a side of the first interlayer insulating layer facing away from the first gate insulating layer, and wherein the second gate electrode and the second active layer are provided to face each other;
the oxide thin film transistor further comprises a third grid electrode, the third grid electrode is arranged on one side, away from the substrate, of the second grid insulation layer, and the third grid electrode is connected with the second grid electrode through a second through hole penetrating through the first interlayer insulation layer and the second grid insulation layer.
8. The display panel according to claim 1 or 3, wherein the first source electrode and the first drain electrode are provided on a side of the first interlayer insulating layer facing away from the first gate insulating layer, wherein the first source electrode is connected to the first active layer through a third via, wherein the first drain electrode is connected to the first active layer through a fourth via, and wherein the first source electrode, the first drain electrode, and the second active layer are provided on the same layer.
9. A display device characterized by comprising the display panel according to any one of claims 1 to 8.
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