CN217158190U - Pixel structure of low-resistance touch line - Google Patents
Pixel structure of low-resistance touch line Download PDFInfo
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- CN217158190U CN217158190U CN202220925806.1U CN202220925806U CN217158190U CN 217158190 U CN217158190 U CN 217158190U CN 202220925806 U CN202220925806 U CN 202220925806U CN 217158190 U CN217158190 U CN 217158190U
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Abstract
The utility model discloses a pixel structure of low resistance touch line, it includes first metal level, grid insulating layer, semiconductor layer, second metal level, first insulating layer, organic layer, third metal level, second insulating layer, pixel electrode, third insulating layer and common electrode from bottom to top on setting up the base plate; the first metal layer is used as a grid of the thin film transistor; the semiconductor layer is used as a semiconductor channel of the thin film transistor; the second metal layer is used as a touch line layer; the third metal layer is used as the other layer of the touch control line and is connected with the second metal layer through the connecting through hole on the first insulating layer to be used as the touch control line; and connecting through holes are formed in the vertical direction of the third insulating layer, the second insulating layer, the organic layer and the first insulating layer between the common electrode and the third metal layer, and the common electrode is connected with the third metal layer through the connecting through holes to realize the connection of the common electrode and the touch line. The utility model discloses utilize the mode of two-layer metal wiring to reduce resistance, the touch-control reaction is more sensitive.
Description
Technical Field
The utility model relates to a display panel technical field especially relates to a pixel structure of low resistance touch line.
Background
As shown in fig. 1, for a Dual Gate (DG) pixel structure, there are only 1 data line for 2 subpixels on average. As shown in fig. 2 or 3, the previous design is to design the data lines beside the sub-pixels, and since there are only 1 data line for 2 sub-pixels, Touch Panel (TP line for short) can be designed at the position where there is no data line in the sub-pixels. The touch control line can be made of the second metal layer or the third metal layer.
Taking 13.3 inches for example, with a resolution of 1920 x 1080, under the condition that the resolution of touch control is 64 x 36, one touch control square (sensor) can be controlled by at most one touch control line, and the touch control line is a second metal layer or a third metal layer. At this time, the touch resistance of one touch grid is larger.
Disclosure of Invention
An object of the utility model is to provide a pixel structure of low resistance touch line.
The utility model adopts the technical proposal that:
a pixel structure of a low-resistance touch line comprises a substrate, and a first metal layer, a grid electrode insulating layer, a semiconductor layer, a second metal layer, a first insulating layer, an organic layer, a third metal layer, a second insulating layer, a pixel electrode, a third insulating layer and a common electrode which are sequentially arranged on the substrate from bottom to top; the first metal layer covers part of the upper surface of the substrate and is used as a grid electrode of the thin film transistor; the grid insulation layer completely covers the first metal layer and a non-first metal layer covering area on the substrate; the semiconductor layer covers a partial area, corresponding to the first metal layer, on the grid electrode insulating layer, and the semiconductor layer is used as a semiconductor channel of the thin film transistor; the second metal layer partially covers the upper surface of the semiconductor layer to serve as a source electrode and a drain electrode of the thin film transistor, and the second metal layer partially directly covers the non-semiconductor layer covering area of the grid electrode insulating layer to serve as one layer of the touch control line; the first insulating layer is arranged on the second metal layer and isolates the second metal layer; the organic layer covers the upper surface of the first insulating layer; the third metal layer is arranged on the organic layer, corresponds to the area of the second metal layer and covers the partial area of the organic layer, the third metal layer is used as the other layer of the touch control line, and the third metal layer is connected with the part, used as the touch control line, in the second metal layer through a connecting through hole arranged on the first insulating layer to form a touch control line connecting area, so that the third metal layer and the second metal layer are matched in a common way to be used as the touch control line; the second insulating layer covers the upper surfaces of the third metal layer and the organic layer; the pixel electrode is arranged on the non-touch line connecting area on the upper surface of the second insulating layer; the third insulating layer is arranged on the pixel electrode and completely covers the pixel electrode and the non-pixel electrode covering area of the second insulating layer; and the third insulating layer, the second insulating layer, the organic layer and the first insulating layer which are positioned between the common electrode and the third metal layer are correspondingly provided with connecting through holes in the vertical direction, the common electrode covers the connecting through holes and is connected with the third metal layer through the connecting through holes, and the common electrode is connected with the touch control line.
Furthermore, the pixel electrode and the common electrode are both formed by indium tin oxide.
Further, the third insulating layer covers the second insulating layer corresponding to both side portions of the connecting through hole.
A preparation method of a pixel structure of a low-resistance touch line comprises the following steps:
and 11, manufacturing a common electrode in the connecting through hole of the third insulating layer, wherein the common electrode partially penetrates through the second insulating layer and the corresponding connecting through hole on the third insulating layer to be connected with the third metal layer, so that the common electrode is connected with the touch line.
Further, the size of the connection via of the first insulating layer in step 5 is not greater than the minimum width of the third metal layer.
Further, the size of the development exposure position on the organic layer in the step 6 is not less than the minimum width of the third metal layer.
The utility model adopts the above technical scheme, with the touch-control line second metal level or the third metal level processing procedure of the former case, change into second metal level and third metal level and regard as touch-control line jointly, utilize the mode that the line was walked to two-layer metal to reduce resistance. The second metal layer and the third metal layer are used together as a touch line, the capacitance is increased by 18% compared with the capacitance only with the third metal layer, but the resistance is reduced by 38%, the touch control is facilitated, and the touch control response is sensitive.
Drawings
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments;
FIG. 1 is a schematic diagram of a pixel architecture of the prior art;
FIG. 2 is a schematic top view of a single sub-pixel architecture of the prior art;
FIG. 3 is a cross-sectional view of a prior art single-layer metal touch line connected to a pixel electrode;
fig. 4 is a schematic structural diagram of a pixel structure of a low resistance touch line according to the present invention;
fig. 5 is a schematic top view of a single sub-pixel structure of a pixel structure with a low resistance touch line according to the present invention;
fig. 6 is a schematic cross-sectional view of the dual-layer metal touch line connected to the pixel electrode according to the present invention;
FIG. 7 is a schematic cross-sectional view of the junction between the pixel electrode and the drain of the TFT according to the present invention;
fig. 8 is a cross-sectional view of the junction between the pixel electrode and the drain electrode of the tft according to the present invention;
fig. 9 is a schematic cross-sectional view of a thin film transistor according to the present invention;
fig. 10 is a cross-sectional view of the thin film transistor according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
As shown in one of fig. 4 to 10, the present invention discloses a pixel structure of a low resistance touch line, which includes a substrate 14, and a first metal layer 2, a gate insulating layer 7, a semiconductor layer 3, a second metal layer (15, 16, 17), a first insulating layer 8, an organic layer 9, a third metal layer 10, a second insulating layer 11, a pixel electrode 4, a third insulating layer 12 and a common electrode 13, which are sequentially disposed on the substrate 14 from bottom to top; the first metal layer 2 covers partial area of the upper surface of the substrate 14, and the first metal layer 2 is used as a grid electrode of the thin film transistor; the gate insulating layer 7 completely covers the first metal layer 2 and the non-first metal layer 2 covering region on the substrate 14; the semiconductor layer 3 covers a partial area corresponding to the first metal layer 2 on the gate insulating layer 7, and the semiconductor layer 3 is used as a semiconductor channel of the thin film transistor; the second metal layer partially covers the upper surface of the semiconductor layer 3 to serve as a source electrode 16 and a drain electrode 17 of the thin film transistor, and the second metal layer partially directly covers the non-semiconductor layer covered area of the grid electrode insulating layer to serve as one layer of the touch control line 15; a first insulating layer 8 is arranged on the second metal layer (15, 16, 17) and isolates the second metal layer (15, 16, 17); the organic layer 9 covers the upper surface of the first insulating layer 8; the third metal layer 10 is arranged on the organic layer 9 corresponding to the second metal layer (15, 16, 17) area and covers partial area of the organic layer 9, the third metal layer 10 is used as the other layer of the touch control line, the third metal layer 10 is connected with the part of the second metal layer used as the touch control line 15 through a connecting through hole arranged on the first insulating layer to form a touch control line connecting area, and the third metal layer and the second metal layer are used as the touch control line in a common matching way; the second insulating layer 11 covers the upper surfaces of the third metal layer 10 and the organic layer 9; the pixel electrode 4 is arranged on the upper surface of the second insulating layer 11 in a non-touch line connection area; the third insulating layer 12 is arranged on the pixel electrode 4 and completely covers the pixel electrode 4 and the non-pixel electrode 4 covering area of the second insulating layer; and the third insulating layer 12, the second insulating layer 11, the organic layer 9 and the first insulating layer 8 which are positioned between the common electrode 13 and the third metal layer 10 are correspondingly provided with connecting through holes in the vertical direction, and the common electrode 13 covers the connecting through holes and is connected with the third metal layer 10 through the connecting through holes, so that the common electrode 13 is connected with the touch control lines.
Further, the pixel electrode 4 and the common electrode 13 are formed using indium tin oxide.
Further, both side portions of the third insulating layer 12 corresponding to the via-holes are covered on the second insulating layer 11.
A preparation method of a pixel structure of a low-resistance touch line comprises the following steps:
and 11, manufacturing a common electrode 13 in the connecting through hole of the third insulating layer 12, wherein the common electrode 13 partially penetrates through the second insulating layer 11 and the corresponding connecting through hole on the third insulating layer 12 to be connected with the third metal layer 10, so that the common electrode 13 is connected with the touch control line.
Further, the size of the connection via of the first insulating layer 8 in step 5 is not greater than the minimum width of the third metal layer 10.
Further, the size of the development exposure position on the organic layer 9 in step 6 is not less than the minimum width of the third metal layer 10.
The following is a detailed description of the specific principles of the present invention:
referring to fig. 4, 5 and 6, a manufacturing method of the thin film transistor liquid crystal display in this embodiment is shown, in which fig. 6 is a cross-sectional view of a region labeled as a "touch line connection point". As shown in fig. 6, this position is the connection of the contact line (the third metal layer 10 and the portion of the second metal layer connected as the contact line 15) to the common electrode 13.
As shown in fig. 4, a substrate 14 is first provided; a first metal layer 2 is arranged on the substrate and is used as a grid electrode of the thin film transistor; a gate insulating layer 7 on the first metal layer 2; as shown in fig. 5, a semiconductor layer 3 is further formed as a semiconductor channel of the thin film transistor, and since there is no semiconductor in the "touch line connection" region, there is no semiconductor 3 in fig. 6, and then a second metal layer (15, 16, 17) is formed, in which the portion of the second metal layer serving as the touch line 15 serves as one of the touch lines; a first insulating layer 8 is arranged; another organic layer 9 is coated; a third metal layer 10 is arranged on the first metal layer, the third metal layer 10 is used as the other layer of the touch control line, and the third metal layer 10 is partially connected with the second metal layer which is used as the touch control line 15 through the hole of the first insulating layer 8, so that the two layers of metal are shared as the touch control line; a second insulating layer 11 is arranged on the substrate; then, a layer of indium tin oxide is formed on the touch panel to serve as the pixel electrode 4, and since the pixel electrode 4 is not formed in the region of the touch line connection, no indium tin oxide is formed in fig. 6; as shown in fig. 6, a third insulating layer 12 is formed directly on the second insulating layer 11; finally, another layer of indium tin oxide is coated on the first metal layer as a common electrode 13, and the common electrode 13 is connected with the third metal layer 10 through the holes of the second insulating layer 11 and the third insulating layer 12, so that the common electrode 13 is connected with the touch control line.
The utility model adopts the above technical scheme, with as 15 parts of touch line or the 10 processes of third metal level in the touch line second metal level of the previous example, change into as 15 parts of touch line and the common touch line that is as of third metal level 10 in the second metal level, increased the thickness of touch line, utilize the mode reduction resistance that two-layer metal walked the line. The part of the second metal layer serving as the touch line 15 and the third metal layer 10 together serving as the touch line increase the capacitance by 18% compared with the third metal layer 10, but the resistance is reduced by 38%, which is more beneficial to touch control and more sensitive in touch control reaction.
It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. The embodiments and features of the embodiments in the present application may be combined with each other without conflict. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the detailed description of the embodiments of the present application is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Claims (6)
1. A pixel structure of low resistance touch line, its characterized in that: the pixel structure comprises a substrate, and a first metal layer, a grid electrode insulating layer, a semiconductor layer, a second metal layer, a first insulating layer, an organic layer, a third metal layer, a second insulating layer, a pixel electrode, a third insulating layer and a common electrode which are sequentially arranged on the substrate from bottom to top; the first metal layer covers part of the upper surface of the substrate and is used as a grid electrode of the thin film transistor; the grid insulation layer completely covers the first metal layer and a non-first metal layer covering area on the substrate; the semiconductor layer covers a partial area, corresponding to the first metal layer, on the grid electrode insulating layer, and the semiconductor layer is used as a semiconductor channel of the thin film transistor; the second metal layer partially covers the upper surface of the semiconductor layer to serve as a source electrode and a drain electrode of the thin film transistor, and the second metal layer partially directly covers the non-semiconductor layer covering area of the grid electrode insulating layer to serve as one layer of the touch control line; the first insulating layer is arranged on the second metal layer and isolates the second metal layer; the organic layer covers the upper surface of the first insulating layer; the third metal layer is arranged on the organic layer, corresponds to the area of the second metal layer and covers the partial area of the organic layer, the third metal layer is used as the other layer of the touch control line, and the third metal layer is connected with the part, used as the touch control line, in the second metal layer through a connecting through hole arranged on the first insulating layer to form a touch control line connecting area, so that the third metal layer and the second metal layer are matched in a common way to be used as the touch control line; the second insulating layer covers the upper surfaces of the third metal layer and the organic layer; the pixel electrode is arranged on the non-touch line connecting area on the upper surface of the second insulating layer; the third insulating layer is arranged on the pixel electrode and completely covers the pixel electrode and the non-pixel electrode covering area of the second insulating layer; and the third insulating layer, the second insulating layer, the organic layer and the first insulating layer which are positioned between the common electrode and the third metal layer are correspondingly provided with connecting through holes in the vertical direction, the common electrode covers the connecting through holes and is connected with the third metal layer through the connecting through holes, and the common electrode is connected with the touch control line.
2. The pixel structure of claim 1, wherein: the pixel electrode and the common electrode are both formed by indium tin oxide.
3. The pixel structure of claim 1, wherein: the grid insulating layer, the first insulating layer, the second insulating layer and the third insulating layer are all formed by adopting silicon nitride materials.
4. The pixel structure of claim 1, wherein: the two side parts of the third insulating layer corresponding to the connecting through holes are covered on the second insulating layer.
5. The pixel structure of claim 1, wherein: the size of the connection via of the first insulating layer is not greater than the minimum width of the third metal layer.
6. The pixel structure of claim 1, wherein: the size of the developing exposed position on the organic layer is not less than the minimum width of the third metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220925806.1U CN217158190U (en) | 2022-04-20 | 2022-04-20 | Pixel structure of low-resistance touch line |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220925806.1U CN217158190U (en) | 2022-04-20 | 2022-04-20 | Pixel structure of low-resistance touch line |
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| Publication Number | Publication Date |
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| CN217158190U true CN217158190U (en) | 2022-08-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202220925806.1U Active CN217158190U (en) | 2022-04-20 | 2022-04-20 | Pixel structure of low-resistance touch line |
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