CN212485329U - Display panel with fingerprint identification function - Google Patents

Abstract

The utility model provides a display panel with fingerprint identification function, which comprises a substrate, a fingerprint identification component, a thin film transistor and a transparent capacitor, wherein the thin film transistor and the transparent capacitor are arranged on one surface of the substrate, and the fingerprint identification component is arranged on the other surface of the substrate; the transparent capacitor is arranged on one side of the thin film transistor and is connected with source electrode metal or drain electrode metal of the thin film transistor, and the transparent capacitor is arranged on the area of the fingerprint identification component in the direction vertical to the substrate. According to the technical scheme, the transparent capacitor is arranged at the area of the fingerprint identification component, and the finger reflected light can penetrate through the fingerprint identification component below due to the transparent capacitor, so that an avoidance area without devices is not required to be specially arranged, and the integration of the high-resolution AMOLED and the fingerprint identification function is realized. The stability and yield of the display panel are controlled, and more manufacturing space can be made for other driving components and circuits.

Description

Display panel with fingerprint identification function

Technical Field

The utility model relates to a display panel technical field especially relates to a display panel with fingerprint identification function.

Background

AMOLED (Active-matrix organic light-emitting diode, or Active-matrix organic light-emitting diode) is more vivid in color, can self-emit light, and is superior to conventional LCD liquid crystal display in display power consumption. In recent years, the display screen has flexibility as a requirement of the design, and the AMOLED gradually occupies the middle-high-level market due to the flexible characteristic. Meanwhile, the screen occupation ratio has obvious promotion trend, such as disappearance of the Home key on the front surface and reduction of the upper and lower frames, so that the technical advantage of the flexible AMOLED is highlighted again. The disappearance of the Home key and the design optimization of the back appearance of the mobile phone generate a technical scheme for identifying the fingerprint under the screen, and the existing LCD display technology has higher difficulty in identifying the fingerprint under the screen and is still in a research and development stage.

Due to the self-luminous characteristic of the AMOLED, an avoidance area can be designed, so that finger reflected light penetrates through a screen to reach a fingerprint identification assembly (comprising a CMOS assembly) to realize fingerprint signal collection and reading, and the fingerprint identification function is realized. Often, in order to make the finger reflected light better penetrate through the screen and reach the fingerprint identification assembly, the avoiding area is provided with components such as a capacitor or a thin film transistor, and the structure is shown in fig. 1. Also, reference may be made to the patent application No. 201710418673.2. However, the arrangement of the avoiding region can reduce the arrangement area of the driving component and the circuit (for example, the size of the driving component is reduced, the line width and the line distance are reduced, and the like), and the yield and the stability can be influenced in the high-resolution AMOLED display.

SUMMERY OF THE UTILITY MODEL

Therefore, a display panel with a fingerprint identification function is needed to be provided, and the problem that the arrangement area of the driving components is small due to the fact that the avoidance area is arranged in the display panel is solved.

In order to achieve the above object, this embodiment provides a display panel with a fingerprint identification function, including a substrate, a fingerprint identification component, a thin film transistor, and a transparent capacitor, where the thin film transistor and the transparent capacitor are disposed on one side of the substrate, and the fingerprint identification component is disposed on the other side of the substrate;

the transparent capacitor is arranged on one side of the thin film transistor and is connected with source electrode metal or drain electrode metal of the thin film transistor, and the transparent capacitor is arranged in the area of the fingerprint identification component in the direction vertical to the substrate.

Further, the thin film transistor comprises a gate metal, a gate insulating layer, a semiconductor layer, an etching barrier layer, a source metal and a drain metal, wherein the gate metal is arranged on the substrate, the gate insulating layer is arranged on the gate metal, the semiconductor layer is arranged on the gate insulating layer of the gate metal, the etching barrier layer is arranged on the semiconductor layer, and the source metal and the drain metal are respectively connected with the semiconductor layer through holes in the etching barrier layer;

the transparent capacitor comprises a first electrode plate and a second electrode plate, wherein the first electrode plate is arranged on the upper surface of the grid insulating layer and positioned on one side of the semiconductor layer and connected with the source electrode metal or the drain electrode metal, and the second electrode plate has an overlapping area and a gap with the first electrode plate in the direction perpendicular to the substrate.

The passivation layer is arranged on the thin film transistor and the first electrode plate, and the second electrode plate is arranged on the upper surface of the passivation layer and is positioned right above the first electrode plate.

Furthermore, the etching barrier layer covers the first polar plate, and the second polar plate is arranged on the upper surface of the etching barrier layer and is positioned right above the first polar plate.

Furthermore, the second polar plate and the grid metal are arranged on the upper surface of the substrate, the second polar plate is positioned on one side of the grid metal, the grid insulating layer covers the second polar plate, and the second polar plate is positioned right below the first polar plate.

The second polar plate and the buffer layer are arranged on the surface of the substrate, the buffer layer covers the second polar plate, the grid metal and the grid insulating layer are arranged on the upper surface of the buffer layer, and the second polar plate is located right below the first polar plate.

Further, the first electrode plate or the second electrode plate is made of transparent oxide.

Further, the first polar plate is IGZO, and the first polar plate is of a conductor structure; or: and the second electrode plate is ITO, SnO2 or ZnO.

Further, the first electrode plate is formed by the semiconductor layer being made conductive.

Further, the display device also comprises a passivation layer, a flat layer, an anode, a pixel defining layer, an organic light emitting layer and a cathode;

a passivation layer is arranged on the thin film transistor;

a planarization layer is arranged on the passivation layer;

a hole communicated with the source electrode metal or the drain electrode metal is formed in the flat layer and penetrates through the passivation layer and the flat layer;

an anode is arranged on the flat layer and is connected with the source metal or the drain metal through a hole in the flat layer;

a pixel defining layer is arranged on the anode and the passivation layer, and a hole communicated with the anode is arranged on the pixel defining layer;

an organic light emitting layer is arranged at the hole communicated with the anode on the pixel defining layer;

a cathode is disposed on the organic light emitting layer and the pixel defining layer.

Different from the prior art, the transparent capacitor is arranged in the fingerprint identification component area, the finger reflected light can penetrate through the fingerprint identification component below due to the transparent capacitor, and therefore an avoidance area without devices is not required to be specially arranged, and integration of the high-resolution AMOLED and the fingerprint identification function is achieved. The stability and yield of the display panel are controlled, and more manufacturing space can be made for other driving components and circuits.

Drawings

FIG. 1 is a schematic cross-sectional view of a display panel according to the prior art;

FIG. 2 is a schematic cross-sectional view illustrating a display panel with a transparent capacitor according to an embodiment of the present invention;

FIG. 3 is a schematic cross-sectional view of a display panel with a transparent capacitor according to a second embodiment;

FIG. 4 is a schematic cross-sectional view of a display panel with a transparent capacitor according to a third embodiment of the present invention;

fig. 5 is a schematic cross-sectional view of a display panel with a transparent capacitor according to a fourth embodiment.

Description of reference numerals:

1. a substrate;

2. a thin film transistor;

21. a gate metal;

22. a gate insulating layer;

23. a semiconductor layer;

24. etching the barrier layer;

25. a source metal;

26. a drain metal;

3. a transparent capacitor;

31. a first polar plate;

32. a second polar plate;

4. a buffer layer;

5. a passivation layer;

6. a planarization layer;

7. an anode;

8. a pixel defining layer;

9. an organic light emitting layer;

10. a cathode;

11. a fingerprint identification component.

Detailed Description

To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.

Referring to fig. 1 to 5, in the present embodiment (embodiments one to four), a display panel with fingerprint identification function is provided, which includes a substrate 1, a fingerprint identification device 11, a thin film transistor 2 and a transparent capacitor 3. The substrate 1 is, for example, a glass substrate, a plastic substrate, a metal foil, or the like. The thin film transistor 2 and the transparent capacitor 3 are arranged on one surface of the substrate 1, and the fingerprint identification component 11 is arranged on the other surface of the substrate 1. The transparent capacitor 3 is arranged on one side of the thin film transistor 2 and is connected with the source electrode metal or the drain electrode metal of the thin film transistor 2. The transparent capacitor 3 is arranged in the area of the fingerprint recognition assembly 11 in the direction perpendicular to the substrate. Note that the fingerprint recognition component includes a CMOS component or the like for realizing a fingerprint recognition function.

In the prior art, a display panel has a self-luminous characteristic, an avoidance area can be designed, and a fingerprint identification assembly is arranged at the avoidance area, and the structure is shown in fig. 1. When the reflected light of the finger penetrates through the avoiding area of the screen, the fingerprint signal is collected and read in the CMOS assembly of the fingerprint identification assembly. The avoidance area is generally arranged without devices (namely, light transmission, no film layers such as thin film transistors or metals and the like), so that the fingerprint identification assembly can accurately receive the reflected light of the finger. However, the arrangement of the avoiding area can reduce the arrangement area of the driving component and the circuit, which is greatly not beneficial to the integration and the stability of the display panel. In the application, in the above technical scheme, by arranging the transparent capacitor, the existence of the transparent capacitor can enable the finger reflected light to penetrate through to the fingerprint identification component below, so that an avoidance area without a device is not particularly arranged, so as to realize the integration of the high-resolution AMOED and the fingerprint identification function, and the structure is as shown in fig. 2 to 5. The stability and yield of the display panel are controlled, and more manufacturing space can be made for other driving components and circuits.

In this embodiment, the display panel may be based on a thin film transistor 2 of a bottom gate structure. Referring to fig. 2 to 5, in particular, the thin film transistor 2 includes a gate metal 21, a gate insulating layer 22, a semiconductor layer 23, an etch stop layer 24, a source metal 25 and a drain metal 26. A gate metal 21 disposed on the substrate 1, the gate metal 21 having a gate insulating layer 22 disposed thereon; a semiconductor layer 23 is provided on the gate insulating layer 22 in the gate metal 21 region; an etching stopper layer 24 is provided on the semiconductor layer 23; the source metal 25 and the drain metal 26 are connected to the semiconductor layer 23 through holes in the etch stopper layer 24, respectively. The transparent capacitor 3 is disposed on one side of the thin film transistor 2, and a part of an insulating layer (e.g., a gate insulating layer or an etch stop layer) in the thin film transistor 2 or the like may serve as a dielectric layer of the transparent capacitor 3. The transparent capacitor 3 includes a first plate 31 and a second plate 32, the first plate 31 is disposed on the upper surface of the gate insulating layer 22 and on one side of the semiconductor layer 23, and is connected to the source metal 25 or the drain metal 26. Preferably, the first plate and the second plate are parallel to each other, so that the overlapping area is maximized.

The first invention of the present application is that the first electrode plate and the semiconductor layer are made of the same material (typically transparent oxide) and are in the same process, i.e. the first electrode plate is made together with the semiconductor layer. After the first electrode plate is formed, the first electrode plate is conducted in a conductive manner, such as doping (doping) or Plasma Treatment (Plasma Treatment), so that the first electrode plate becomes a conductive structure. Namely, the first electrode plate is made of a conductor of the semiconductor layer. The plate of the conductive structure has good conductive property and is used as one plate of the transparent capacitor. Another invention of the present application is that the second plate (plate two) of the transparent capacitor has an overlapping area and a gap with the first plate in a direction perpendicular to the substrate, the overlapping area specifically means that the plate two can be located at an upper film layer or a lower film layer of the first plate, and the gap means that a film layer is located between the plate two and the film layer, and the film layer is used as a dielectric layer of the transparent capacitor. In this regard, the present application contemplates four main embodiments for the location of plate two. The third invention of the present application is that the first electrode plate and the second electrode plate of the transparent capacitor are made of transparent materials, form a light-transmitting area, and are disposed above the fingerprint identification assembly. The distance between the first polar plate and the second polar plate is different, so that the capacitance value of the transparent capacitor is different. Different capacitance values of the transparent capacitor can be determined according to the actual capacitance value required by the compensation circuit, and only the second electrode plate is arranged on different film layers.

Referring to fig. 2, in the first embodiment, a passivation layer 5 is disposed on the tft, and the passivation layer 5 is used to prevent the tft 2 from contacting a film layer (such as an anode and a cathode) on the display panel, so as to avoid the performance of the display panel from being affected. The passivation layer 5 is disposed on the thin film transistor, and generally, the passivation layer 5 covers the source metal 25, the drain metal 26, and the etch stopper layer 24. In this structure, the second plate 32 is made of transparent oxide and has a conductive property, and is disposed on the upper surface of the passivation layer 5 and directly above the first plate 21. The distance between the first electrode plate 21 and the second electrode plate 22 is the thickness of the passivation layer and the thickness of the etching barrier layer between the first electrode plate and the second electrode plate, and the dielectric layer of the transparent capacitor 3 is also the passivation layer and the etching barrier layer between the first electrode plate and the second electrode plate. It should be noted that, because the second plate is disposed on the passivation layer, and the passivation layer and the etching stop layer are generally made of insulating materials, such as nitride (silicon nitride, etc.), oxide (silicon oxide, silicon dioxide), or other insulating materials, the etching stop layer may cover the first plate or not cover the first plate (i.e., is not located between the first plate and the second plate). The passivation layer and the etching barrier layer can be manufactured by a chemical vapor deposition method or a physical vapor deposition method.

In a further embodiment of the first embodiment, a planarization layer is disposed on the passivation layer for leveling the substrate at a height caused by a plurality of processes. Generally, the flat layer is also made of an insulating material, and the flat layer covers the second electrode plate, so that the second electrode plate can be protected, and other metals are prevented from being connected with the second electrode plate.

Referring to fig. 3, in the second embodiment, the etching stop layer 24 covers the first plate 31 and serves as a dielectric layer of the transparent capacitor 3. In this structure, the second plate 32 is disposed on the upper surface of the etching stop layer 24 and is located right above the first plate 31. The second electrode plate is made of transparent oxide and has a conductive characteristic. The etch stop layer is typically an insulating material such as nitride (silicon nitride, etc.), oxide (silicon oxide, silicon dioxide), or other insulating material, and may be formed by chemical vapor deposition or physical vapor deposition.

The fabrication process of the second embodiment is briefly described here: and manufacturing a semiconductor layer, manufacturing an etching barrier layer, simultaneously manufacturing a source electrode metal and a drain electrode metal, and manufacturing a second electrode plate, wherein the source electrode metal and the drain electrode metal are respectively connected with the semiconductor layer through holes in the etching barrier layer, the second electrode plate is positioned on the etching barrier layer and positioned above the area of the first electrode plate, and the manufacturing process of the source electrode metal and the second electrode plate can be replaced.

Referring to fig. 4, in the third embodiment, the second plate 32 and the gate metal 21 are disposed on the upper surface of the substrate 1, the second plate 32 is located on one side of the gate metal 21, the second plate 32 is covered by the gate insulating layer 22, and the second plate 32 is located right below the first plate 31. The dielectric layer of the transparent capacitor is a gate insulation layer 22 between the first electrode plate and the second electrode plate, and the materials and the manufacturing process of the gate insulation layer are the same as those of the insulation layer. The second electrode plate is made of transparent oxide and has a conductive characteristic.

The fabrication process of the third embodiment is briefly described here: manufacturing grid metal on one surface of the substrate; manufacturing a second polar plate; the polar plate is positioned on one side of the grid metal; and then manufacturing a grid insulation layer on the grid metal and the second electrode plate. And the manufacturing sequence of the grid metal and the second polar plate can be adjusted. The second electrode plate is made of transparent oxide and has a conductive characteristic. The grid insulating layer covers the grid and the second electrode plate, the grid insulating layer covers the grid to avoid contact between the grid and the semiconductor layer, and the grid insulating layer covering the second electrode plate is used as a dielectric layer of the transparent capacitor.

Referring to fig. 5, in the fourth embodiment, the second plate 32 and the buffer layer 4 are both disposed on the surface of the substrate 1, and the buffer layer 4 also covers the second plate 32. The buffer layer 4 may increase adhesion between the gate metal and the substrate, and may buffer an external force applied to the display panel. The buffer layer 4 is generally an insulating material, such as nitride (silicon nitride, etc.), oxide (silicon oxide, silicon dioxide), or other insulating material, and can be formed by chemical vapor deposition or physical vapor deposition. The gate metal 21 and the gate insulating layer 22 (still covering the gate) are disposed on the upper surface of the buffer layer, and the two electrode plates are disposed right below the one electrode plate. The dielectric layer of the transparent capacitor is a buffer layer and a grid insulating layer between the first electrode plate and the second electrode plate.

In this embodiment, the first electrode plate or the second electrode plate is a transparent oxide, such as Indium Gallium Zinc Oxide (IGZO), Indium Zinc Tin Oxide (IZTO), Indium Tin Oxide (ITO), tin oxide (SnO2), zinc oxide (ZnO), or other materials with similar characteristics. Preferably, the first electrode plate is IGZO, and the first electrode plate is of a conductive structure; and the second electrode plate is made of ITO, SnO2 or ZnO and the like. Or in some embodiments, the second plate is IGZO, and the second plate may also be a conductive structure. Or in some embodiments, the first electrode plate is made of ITO, SnO2 or ZnO, and is not in a conductive structure.

In the embodiment, the minimum compensation circuit (2T1C) required by the AM-OLED to realize the scanning display is included, and the 2T1C is formed by connecting two thin film transistors through a source metal or a drain metal and simultaneously connecting a capacitor. Or the compensation circuit further comprises 5T2C, 6T2C and the like, and a plurality of such compensation circuits are arranged in the display panel, and each compensation circuit is provided with a transparent capacitor 3. Namely, the transparent capacitors 3 are multiple, and the multiple transparent capacitors 3 are all arranged at the area of the fingerprint identification component in the direction vertical to the substrate.

It should be noted that the first electrode plate is connected to the source metal or the drain metal, and the second electrode plate is electrically connected to a specific node (different according to the compensation circuit) in a punching/routing manner, that is, the electrode plate of the capacitor needs to be given a potential through a via or a routing, and the cross-sectional view does not well show the lap joint condition of all nodes, and thus does not show the lap joint condition. In this embodiment, the display panel further includes a film layer disposed on the thin film transistor, such as a passivation layer 5, a planarization layer 6, an anode 7, a pixel defining layer 8, an organic light emitting layer 9, a cathode 10, and the like. A passivation layer 5 is arranged on the thin film transistor; a planarization layer 6 is disposed on the passivation layer; a hole communicating with the source metal 25 or the drain metal 26 is provided on the planarization layer 6, and the hole penetrates through the passivation layer and the planarization layer; an anode 7 is arranged on the flat layer, and the anode 7 is connected with the source metal or the drain metal through a hole on the flat layer so as to play a role of connecting the TFT; a pixel defining layer 8 is arranged on the anode 7 and the passivation layer, and a hole communicated with the anode 7 is arranged on the pixel defining layer 8; an organic light emitting layer 9 is disposed at the hole communicating with the anode 7 on the pixel defining layer 8; a cathode 10 is provided on the organic light emitting layer 9 and the pixel defining layer 8. Of course, a glass cover plate may be finally disposed on the cathode, and the display panel may be encapsulated.

In some embodiments, the display panel may also be based on a thin film transistor of a top gate structure. Specifically, the thin film transistor comprises a semiconductor layer, a gate protective layer, a gate metal, a gate insulating layer, a source metal and a drain metal. In this case, the semiconductor layer is provided on the substrate; a grid electrode protection layer is arranged on the semiconductor layer and used for isolating the grid electrode metal from the semiconductor layer; a gate metal is arranged on the gate protection layer of the semiconductor layer region; a grid electrode insulating layer is arranged on the grid electrode metal and is used for isolating the grid electrode metal from the source electrode metal/drain electrode metal; and a hole communicated with the semiconductor layer is formed in the gate insulating layer and is positioned outside the gate metal, and the source metal and the drain metal are respectively connected with the semiconductor layer through the hole in the gate insulating layer. Similarly, the first polar plate of the transparent capacitor is arranged on the substrate and positioned on one side of the semiconductor layer, and the first polar plate and the semiconductor layer are made of the same material and are positioned in the same process; the second electrode plate can be arranged on the grid protection layer, or the second electrode plate is arranged on the grid insulation layer, or the second electrode plate is arranged on a passivation layer covering the thin film transistor, or the second electrode plate is arranged on a buffer layer below the thin film transistor.

In the art, doping (doping): and injecting Al, In, Ga and the like into the oxide semiconductor by adopting an ion injection mode. Due to the injection of metal ions, the number of majority carriers in the transparent oxide film can be increased, the mobility of the majority carriers is improved, the resistivity is reduced, the conductor (or the conduction) is realized, and the conductive property is enhanced. Most of the carriers of the oxide semiconductor function as electrons, and the transport ability of electrons is higher than that of holes. Plasma treatment (plasma treatment): as one of the processing methods, plasma is generally used for surface treatment, such as NO2, O2, H2, etc., to increase the number of mobile electrons of the oxide semiconductor, decrease the resistivity of the film, and enhance the conductive property.

The embodiment provides a manufacturing method of a display panel with a fingerprint identification function, which comprises the following steps: a thin film transistor 2 and a transparent capacitor 3 are formed on one surface of a substrate 1 such as a glass substrate, a plastic substrate, or a metal foil. The transparent capacitor 3 is arranged on one side of the thin film transistor 2 and is connected with the source electrode metal or the drain electrode metal of the thin film transistor 2. After the thin film transistor 2 and the transparent capacitor 3 are manufactured, the upper fingerprint identification component 11 is arranged on the other side direction of the substrate, and the transparent capacitor 3 is arranged in the area of the fingerprint identification component 11 in the direction perpendicular to the substrate. Note that the fingerprint recognition component includes a CMOS component or the like for realizing a fingerprint recognition function.

In the present embodiment (embodiments one to four), the display panel may be based on the thin film transistor 2 with a bottom gate structure. Referring to fig. 2 to 5, in particular, the thin film transistor 2 includes a gate metal 21, a gate insulating layer 22, a semiconductor layer 23, an etch stop layer 24, a source metal 25 and a drain metal 26. The preparation method comprises the following steps: manufacturing a gate metal 21 on a substrate; a photoresist is coated on the substrate, and then the photoresist is patterned, that is, the photoresist is exposed and developed, so that the portion to be manufactured with the gate metal 21 is opened. Then plating a grid metal material, such as one or more of aluminum, molybdenum, titanium, nickel, copper, silver, chromium and other metals with excellent conductivity and alloys, forming grid metal on the substrate, and removing the photoresist after the grid metal is manufactured. Forming a gate insulating layer 22 on the gate metal 21; the gate insulating layer 22 is formed on the gate metal 21 by plating an insulating layer material, such as nitride (silicon nitride, etc.), oxide (silicon oxide, silicon dioxide), or other insulating material, by a chemical vapor deposition method or a physical vapor deposition method, so as to protect the gate metal 21.

Referring to fig. 5, in the fourth embodiment, before the gate metal 21 is fabricated, a second electrode plate 32 of the transparent capacitor 3 is fabricated on the substrate, and the second electrode plate is made of a transparent oxide (ITO, SnO2, ZnO, or the like). And then, an insulating layer material, such as nitride (silicon nitride and the like), oxide (silicon oxide, silicon dioxide) or other insulating materials, is plated by a chemical vapor deposition method or a physical vapor deposition method, so that the buffer layer 4 is formed on the second polar plate 32 and the substrate, and the buffer layer 4 also covers the second polar plate 32. The buffer layer 4 may increase adhesion between the gate metal and the substrate, and may buffer an external force applied to the display panel. And then manufacturing a thin film transistor on the buffer layer.

Referring to fig. 4, in the third embodiment, after the gate metal is fabricated and before the gate insulating layer is fabricated, a second electrode plate 32 is fabricated, that is, the second electrode plate and the gate metal are located on the substrate. And then the gate insulating layer 22 covers the second electrode plate 32, and the second electrode plate 32 is located right below the first electrode plate 31. The dielectric layer of the transparent capacitor is a gate insulation layer 22 between a first electrode plate and a second electrode plate, and the second electrode plate is made of transparent oxide and has a conductive property. Of course, the manufacturing sequence of the gate metal and the second electrode plate can be replaced.

Simultaneously manufacturing a semiconductor layer 23 and a first electrode plate 31 of the transparent capacitor 3 on the gate insulating layer 22; generally, the material of the semiconductor layer is a transparent oxide, such as Indium Gallium Zinc Oxide (IGZO), Indium Zinc Tin Oxide (IZTO), Indium Tin Oxide (ITO), or other materials with similar characteristics. The first plate is made of the same material as the semiconductor layer (typically a transparent oxide) and is in the same process. After the first electrode plate is formed, the first electrode plate is conducted in a conductive manner, such as doping (doping) or Plasma Treatment (Plasma Treatment), so that the first electrode plate becomes a conductive structure. The plate of the conductive structure has good conductive property and is used as one plate of the transparent capacitor.

In the art, doping (doping): and injecting Al, In, Ga and the like into the oxide semiconductor by adopting an ion injection mode. Due to the injection of metal ions, the number of majority carriers in the transparent oxide film can be increased, the mobility of the majority carriers is improved, the resistivity is reduced, the conductor (or the conduction) is realized, and the conductive property is enhanced. Most of the carriers of the oxide semiconductor function as electrons, and the transport ability of electrons is higher than that of holes. Plasma treatment (plasma treatment): as one of the processing methods, plasma is generally used for surface treatment, such as NO2, O2, H2, etc., to increase the number of mobile electrons of the oxide semiconductor, decrease the resistivity of the film, and enhance the conductive property.

Then, an etching barrier layer 24 is formed on the semiconductor layer 23, and the etching barrier layer can protect the conductive channel portion of the semiconductor layer 23 from being damaged by subsequent processes; similarly, an etching barrier layer 24 is formed on the semiconductor layer 23 by plating an insulating layer material, such as nitride (silicon nitride, etc.), oxide (silicon oxide, silicon dioxide), or other insulating material, by a chemical vapor deposition method or a physical vapor deposition method, so as to protect the semiconductor layer 23. If the etch stop layer 24 is to be used as a dielectric layer of the transparent capacitor 3, the etch stop layer may cover the plate, or if the etch stop layer 24 is not to be used as a dielectric layer of the transparent capacitor 3, the plate may not be covered. After the etching stopper layer 24 is formed, the etching stopper layer 24 is etched to form holes communicating with the semiconductor layer as connection points of the source metal 25, the drain metal 26, and the semiconductor layer.

A source metal 25 and a drain metal 26 are formed on the semiconductor layer, and the source metal 25 and the drain metal 26 are connected to the semiconductor layer 23 through holes in the etch stopper layer 24, respectively.

Referring to fig. 3, in the second embodiment, after the source metal 25 and the drain metal 26 are fabricated, a second electrode plate 32 is fabricated, that is, the second electrode plate, the source metal 25 and the drain metal 26 are located on the etching stop layer. Of course, the etch stop layer 24 first covers the first plate 31 as the dielectric layer of the transparent capacitor 3. The second electrode plate 32 is located right above the first electrode plate 31, and the material of the second electrode plate is transparent oxide and has a conductive property. Of course, the order of manufacturing the source metal 25, the drain metal 26 and the second plate can be changed.

Referring to fig. 2, in the first embodiment, after the thin film transistor is manufactured, a passivation layer is manufactured to protect the thin film transistor; similarly, the passivation layer 5 is formed on the source metal 25, the drain metal 26 and the etching barrier layer 24 by plating an insulating layer material, such as nitride (silicon nitride, etc.), oxide (silicon oxide, silicon dioxide) or other insulating materials, by a chemical vapor deposition method or a physical vapor deposition method, so as to protect the thin film transistor 2. After the passivation layer is manufactured, a second electrode plate is manufactured on the passivation layer in the first electrode plate area, the second electrode plate is similar to transparent oxide and has a conductive characteristic, and the dielectric layer of the transparent capacitor is the passivation layer and the etching barrier layer between the first electrode plate and the second electrode plate (whether the etching barrier layer is used as the dielectric layer depends on whether the etching barrier layer is positioned between the two electrode plates).

In this embodiment, the first electrode plate or the second electrode plate is a transparent oxide, such as Indium Gallium Zinc Oxide (IGZO), Indium Zinc Tin Oxide (IZTO), Indium Tin Oxide (ITO), tin oxide (SnO2), zinc oxide (ZnO), or other materials with similar characteristics. Preferably, the first electrode plate is IGZO, and the first electrode plate is of a conductive structure; and the second electrode plate is made of ITO, SnO2 or ZnO and the like. Or in some embodiments, the second plate is IGZO, and the second plate may also be a conductive structure. Or in some embodiments, the first electrode plate is made of ITO, SnO2 or ZnO, and is not in a conductive structure.

In the embodiment, the minimum compensation circuit (2T1C) required by the AM-OLED to realize the scanning display is included, and the 2T1C is formed by connecting two thin film transistors through a source metal or a drain metal and simultaneously connecting a capacitor. Or the compensation circuit further comprises 5T2C, 6T2C and the like, and a plurality of such compensation circuits are arranged in the display panel, and each compensation circuit is provided with a transparent capacitor 3. Namely, the transparent capacitors 3 are multiple, and the multiple transparent capacitors 3 are all arranged at the area of the fingerprint identification component in the direction vertical to the substrate.

It should be noted that the first electrode plate is connected to the source metal or the drain metal, and the second electrode plate is electrically connected to a specific node (different according to the compensation circuit) in a punching/routing manner, that is, the electrode plate of the capacitor needs to be given a potential through a via or a routing, and the cross-sectional view does not well show the lap joint condition of all nodes, and thus does not show the lap joint condition.

In the present embodiment, the display panel further includes other layers, such as a passivation layer 5, a planarization layer 6, an anode 7, a pixel defining layer 8, an organic light emitting layer 9, a cathode 10, etc., fabricated on the thin film transistor. Manufacturing a passivation layer 5 on the thin film transistor; a flat layer 6 is manufactured on the passivation layer, and the organic flat layer covers the passivation layer and is used for paving the high and low positions of the substrate caused by a plurality of manufacturing processes; making a hole communicating with the source metal 25 or the drain metal 26 on the planarization layer 6, the hole penetrating through the passivation layer and the planarization layer; manufacturing an anode 7 on the flat layer, wherein the anode 7 is connected with the source metal or the drain metal through a hole on the flat layer so as to play a role of connecting the TFT; forming a pixel defining layer 8 on the anode 7 and the passivation layer, and forming a hole communicating with the anode 7 on the pixel defining layer 8; forming an organic light emitting layer 9 at the hole communicating with the anode 7 on the pixel defining layer 8; a cathode 10 is formed on the organic light emitting layer 9 and the pixel defining layer 8. Of course, a glass cover plate may be finally disposed on the cathode, and the display panel may be encapsulated.

In some embodiments, the display panel may also be based on a thin film transistor of a top gate structure. Specifically, the thin film transistor comprises a semiconductor layer, a gate protective layer, a gate metal, a gate insulating layer, a source metal and a drain metal. In this case, the semiconductor layer is provided on the substrate; a grid electrode protection layer is arranged on the semiconductor layer and used for isolating the grid electrode metal from the semiconductor layer; a gate metal is arranged on the gate protection layer of the semiconductor layer region; a grid electrode insulating layer is arranged on the grid electrode metal and is used for isolating the grid electrode metal from the source electrode metal/drain electrode metal; and a hole communicated with the semiconductor layer is formed in the gate insulating layer and is positioned outside the gate metal, and the source metal and the drain metal are respectively connected with the semiconductor layer through the hole in the gate insulating layer. Similarly, the first polar plate of the transparent capacitor is arranged on the substrate and positioned on one side of the semiconductor layer, and the first polar plate and the semiconductor layer are made of the same material and are positioned in the same process; the second electrode plate can be arranged on the grid protection layer, or the second electrode plate is arranged on the grid insulation layer, or the second electrode plate is arranged on a passivation layer covering the thin film transistor, or the second electrode plate is arranged on a buffer layer below the thin film transistor.

It should be noted that, although the above embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, the changes and modifications of the embodiments described herein, or the equivalent structure or equivalent process changes made by the contents of the specification and the drawings of the present invention, directly or indirectly apply the above technical solutions to other related technical fields, all included in the scope of the present invention.

Claims (10)

1. A display panel with a fingerprint identification function is characterized by comprising a substrate, a fingerprint identification component, a thin film transistor and a transparent capacitor, wherein the thin film transistor and the transparent capacitor are arranged on one surface of the substrate, and the fingerprint identification component is arranged on the other surface of the substrate;

the transparent capacitor is arranged on one side of the thin film transistor and is connected with source electrode metal or drain electrode metal of the thin film transistor, and the transparent capacitor is arranged in the area of the fingerprint identification component in the direction vertical to the substrate.

2. The display panel with the fingerprint identification function of claim 1, wherein the thin film transistor comprises a gate metal, a gate insulating layer, a semiconductor layer, an etching barrier layer, a source metal and a drain metal, the gate metal is disposed on the substrate, the gate insulating layer is disposed on the gate metal, the semiconductor layer is disposed on the gate insulating layer of the gate metal, the etching barrier layer is disposed on the semiconductor layer, and the source metal and the drain metal are respectively connected to the semiconductor layer through holes in the etching barrier layer;

the transparent capacitor comprises a first electrode plate and a second electrode plate, wherein the first electrode plate is arranged on the upper surface of the grid insulating layer and positioned on one side of the semiconductor layer and connected with the source electrode metal or the drain electrode metal, and the second electrode plate has an overlapping area and a gap with the first electrode plate in the direction perpendicular to the substrate.

3. The display panel with fingerprint identification function of claim 2, further comprising a passivation layer, wherein the passivation layer is disposed on the thin film transistor and the first electrode plate, and the second electrode plate is disposed on the upper surface of the passivation layer and directly above the first electrode plate.

4. The display panel with fingerprint identification function of claim 2, wherein the etching barrier layer covers the first electrode plate, and the second electrode plate is disposed on the upper surface of the etching barrier layer and is located right above the first electrode plate.

5. The display panel with fingerprint identification function of claim 2, wherein the second plate and the gate metal are disposed on the upper surface of the substrate, the second plate is located on one side of the gate metal, the gate insulating layer covers the second plate, and the second plate is located right below the first plate.

6. The display panel with the fingerprint identification function of claim 2, further comprising a buffer layer, wherein the second polar plate and the buffer layer are both disposed on the surface of the substrate, the buffer layer covers the second polar plate, the gate metal and the gate insulating layer are disposed on the upper surface of the buffer layer, and the second polar plate is disposed right below the first polar plate.

7. The display panel with fingerprint identification function of claim 2, wherein the first or second plate is a transparent oxide.

8. The display panel with fingerprint identification function of claim 7, wherein said first plate is IGZO and said first plate is of a conductive structure; or: and the second electrode plate is ITO, SnO2 or ZnO.

9. The display panel with fingerprint identification function of claim 2 wherein said first electrode plate is made of a conductor of said semiconductor layer.

10. The display panel with fingerprint identification function of claim 2, further comprising a passivation layer, a planarization layer, an anode, a pixel defining layer, an organic light emitting layer, a cathode;

a passivation layer is arranged on the thin film transistor;

a planarization layer is arranged on the passivation layer;

a hole communicated with the source electrode metal or the drain electrode metal is formed in the flat layer and penetrates through the passivation layer and the flat layer;

an anode is arranged on the flat layer and is connected with the source metal or the drain metal through a hole in the flat layer;

a pixel defining layer is arranged on the anode and the passivation layer, and a hole communicated with the anode is arranged on the pixel defining layer;

an organic light emitting layer is arranged at the hole communicated with the anode on the pixel defining layer;

a cathode is disposed on the organic light emitting layer and the pixel defining layer.

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