JP2001325102A - Computing element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the necessity of processing time for branching processing out of the processing of a computing element and to secure the flexibility of processing contents. SOLUTION: An adder 135 adds a leading address stored in leading address storage parts 111, 112 or 113 and selected by a selector 131 to contents (relative address) stored in a program counter 134 and outputs a current performance instruction address. An operation part 138 performs an instruction of the address stored in a program storage part 137. A comparison part 136 compares the leading address with an end address stored in end address storage parts 121, 122 or 123 and selected by a selector 132, and when both the addresses coincide with each other, the selectors 131, 132 are switched and the counter 134 is reset, so that branching can be carried out without requiring an instruction cycle. The contents of the leading address storage parts 111 to 113 are suitably rewritten by a master processor 151.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit for executing an instruction stored in a memory, and more particularly, to speeding up a branch process for transferring control to an instruction stored in a non-contiguous address area in a memory. It is about.

[0002]

2. Description of the Related Art In general, an arithmetic unit is configured to fetch and execute an instruction stored in an area of a memory at an address indicated by a program counter. The address held in the program counter is automatically counted up by an operation of hardware accompanying instruction fetch. As a result, instructions stored in areas of consecutive addresses in the memory are sequentially executed. On the other hand, a branch process for transferring control to an instruction stored in a non-contiguous address area according to a predetermined condition or unconditionally is normally held in a program counter by software (execution of a branch instruction). This is done by rewriting the address. That is,
Each time a branch operation is performed, an instruction cycle of a branch instruction occurs, and more than one clock cycle is spent.

[0003] In the field of device control and the like, some relatively short program modules (arithmetic processes) are often repeatedly processed. In particular,
For example, when servo control is performed, it is necessary to repeatedly monitor the control amount and control the operation amount at a high speed.
In addition, since the control content may be changed depending on whether the control amount exceeds a predetermined threshold, for example, some of the dozens of types of program modules having about ten and several steps per module are selectively used. The processing is repeated while the processing order is appropriately changed. In other words, by modularizing the program into small units, high speed and flexibility of control processing are ensured.

[0004]

However, when a relatively short program module is repeatedly executed,
Since the branch instruction is executed at least once for each processing of each program module, the ratio of the execution time of the branch instruction to the entire processing time of the program module increases, and the total processing time tends to be long. Therefore, the conventional arithmetic unit has a problem that it is difficult to apply it to a control system or the like that requires particularly high speed.

In view of the above problems, the present invention can suppress an increase in processing time due to branch processing even when an arithmetic unit sequentially switches a plurality of program modules and repeats processing. It is an object to flexibly change processing contents according to conditions.

[0006]

Means for Solving the Problems To solve the above-mentioned problems, a solution taken by the present invention is an instruction executing means for executing an instruction stored in a storage means, and an instruction execution means for executing the instruction stored in the storage means. An execution instruction address output means for outputting an execution instruction address which is an address of an area where an instruction to be executed by the execution means is stored. Detecting means for detecting the last instruction of the operation processing before the branch, and the execution instruction address output means for performing the operation after the branch when the detection of the last instruction is performed by the detection means. About processing,
It is characterized in that it is configured to output a head address which is an address of an area in the storage means where the first instruction is stored. According to the above configuration, when the last instruction is detected by the detection means, the start address for the arithmetic processing after the branch is output from the execution instruction address output means, so that the branch instruction is executed by the instruction execution means. No instruction cycle is required and the first instruction after the branch can be executed following execution of the last instruction before the branch. Therefore, arithmetic processing that requires branching can be performed at high speed, and the total arithmetic processing time can be shortened. Specifically, the execution instruction address output means includes, for example, a start address holding means for holding a start address for each of a plurality of arithmetic processing in the storage means, and a detection of the last instruction by the detection means. A head address selecting means for sequentially switching and selecting the head address held in the head address holding means each time the operation is performed, and executing the execution based on the head address selected by the head address selecting means. It can be configured to output an instruction address. Thus, for example, the arithmetic unit can easily switch the plurality of arithmetic processes sequentially and repeat the process, and can suppress an increase in the processing time due to the branching process at the time of the switching. Further, for the detection of the last instruction by the detection means,
An end address holding means for holding an end address which is an address of an area where a plurality of last instructions for each of the plurality of arithmetic processings is stored in the storage means, and the detection means detects the last instruction. End address selection means for sequentially switching and selecting the end address held in the end address holding means, and the detecting means outputs the execution instruction address output from the execution instruction address output means. And detecting the last instruction based on the end address selected by the end address selecting means. Thus, for example, when the arithmetic unit sequentially switches a plurality of arithmetic processes and repeats the process, it is easy to sequentially detect the last instruction of each arithmetic process. Further, the end address holding means as described above,
And a processing length holding means for holding a processing length which is a relative address of an end address with respect to a start address in each of a plurality of arithmetic processings in the storage means in place of the selection means; A processing length selection means for sequentially switching and selecting the processing length held in the processing length holding means each time the detection of While adding the start address and the relative address of the execution instruction address to the start address to generate the execution instruction address,
The detection means may be configured to detect the last instruction based on the relative address and the processing length selected by the processing length selection means. Thus, for example, when the arithmetic unit sequentially switches a plurality of arithmetic processing and repeats the processing, it is easy to sequentially detect the last instruction of each arithmetic processing. In addition, since the processing length, which is a relative address, has a smaller amount of data (the number of bits) than the end address, which is an absolute address, the hardware scale of the processing length holding means, processing length selection means, and detection means can be reduced. . Further, as still another configuration for detecting the last instruction by the detection means, the detection means stores the information in the storage means in association with information indicating the content of the instruction executed by the instruction execution means. The last instruction may be detected based on information indicating that the instruction is the last instruction. As a result, the last instruction can be detected without providing an end address holding unit, a processing length holding unit, or the like, so that the hardware scale can be further reduced. Further, the head address holding means, the end address holding means, or the processing length holding means includes a plurality of registers each holding the head address and the like, and the head address selection means, the end address selection means, or The processing length selection means may be configured to include a selector for selecting any of the plurality of registers. This makes it possible to easily configure the head address holding means, the head address selection means, and the like, and to easily hold and output the head address and the like. The head address holding means, the end address holding means, or the processing length holding means includes a memory for holding the head address or the like, and the head address selecting means, the end address selecting means, or the processing length. The selecting means may be configured to include an address specifying means for specifying an address of an area in the memory where the head address and the like are held. As a result, for example, the head address holding means and the like can be configured by using (and sharing) a part of the memory in which programs and data are stored, and the hardware scale can be reduced. Further, the start address held in the start address holding means, the end address holding means, or the processing length holding means is set by a host processor which controls the execution of an instruction by the instruction execution means or the operation of a computing unit. It may be constituted so that it can be performed. Thus, the arithmetic processing performed after the branch can be controlled by the instruction execution means and the upper processor, so that the processing content can be flexibly changed according to various conditions. When the arithmetic processing includes an instruction for setting a head address or the like as described above, the arithmetic processing involves an instruction cycle for executing the instruction, but does not include such an instruction. As for the arithmetic processing, since the high-speed processing is performed as described above, the total arithmetic processing time can be shortened. In the case where the top address and the like can be set by the host processor as described above,
A high-order processor start address holding means, a high-order processor end address holding means, or a high-order processor processing length holding means for holding a high-order address output from the high-order processor; The held start address or the like may be configured to be written to the start address holding means or the like at a predetermined timing. By providing the head address holding means for the upper processor as described above, at the time when the head address or the like is held in such holding means, there is no effect on the arithmetic processing during processing, so the upper processor is It is possible to cause the processor start address holding means or the like to hold the start address or the like at an arbitrary timing. In addition, since the rewriting of the head address and the like held in the head address holding means and the like is performed at a predetermined timing, it is possible to appropriately control the arithmetic processing performed after the branch. Here, the predetermined timing is, for example, a timing at which the head address or the like held in the head address holding means or the like is not used for the arithmetic processing during processing. More specifically, this is the case after the last instruction is detected, or when another arithmetic processing is being processed. At such a timing, even if the head address or the like is rewritten, the detection of the last instruction and the arithmetic processing are not affected. Therefore,
Appropriate control of arithmetic processing is guaranteed, and the flexibility of the timing of setting the start address and the like by the upper processor makes it possible to prevent waiting and interruption from occurring in the upper processor. Simplification and improvement in processing efficiency can be achieved.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) An arithmetic unit according to Embodiment 1 of the present invention is executed by a program module (arithmetic processing) ending address, which is an absolute address, and a program module. When the instruction address (hereinafter, referred to as “current execution instruction address”) matches, the control is transferred to the next program module. As a result, a branch can be made without executing a branch instruction, and high-speed processing can be performed. The next program module is managed by, for example, an upper processor, so that the combination of the program modules to be processed and the processing order can be flexibly controlled. Hereinafter, a specific description will be given with reference to FIG.

FIG. 1 is a block diagram showing the configuration of the arithmetic unit. In FIG. 1, an address storage device 100 holds a start address and an end address (both absolute addresses) of each program module to be processed. More specifically, the address storage device 100 includes start address storage units 111 to 11 for holding start addresses.
3 and the respective head address storage units 111 to 113
End address storage units 121 to 123 (end address holding means) for storing end addresses corresponding to the (start address holding means). The address storage unit 11
Are specifically configured using, for example, a register, but may also be configured using a memory as described later (Embodiment 4).

Selector 131 (head address selecting means)
Is to select and output the head address held in any of the head address storage units 111 to 113.

Selector 132 (end address selecting means)
Is for selecting and outputting the end address stored in any of the end address storage units 121 to 123.

The read select control unit 133 stores the address storage units 111 to 11 in the selectors 131 and 132.
3. A read select signal is output to indicate which of the addresses 121.123 and 123 is to be selected and read. More specifically, the read select control unit 133 is configured using, for example, a ring counter, and as described later, every time an end address match signal is output from the comparison unit 136, * 1 → * 2 → * 3 → * 1 → * 2 → * 3 → * 1 → ...
, And outputs a read select signal to the selectors 131 and 132 so that the start address storage units 111 to 113 and the end address storage units 121 to 123 are selected in this order.

The program counter 134 holds a relative address of an instruction to be executed with respect to a start address of a program module being processed. The held relative address is counted up every clock cycle, and is reset when an end address coincidence signal is output from the comparing unit 136.

The adder 135 adds the start address of the program module being processed, which is selected and output by the selector 131, and the relative address output from the program counter 134, and adds the current execution instruction address (absolute address). ) Is output. (The head address storage units 111 to 113, the selector 131, the program counter 134, and the adder 135 act as an instruction address output unit.) The comparison unit 136 (detection unit) outputs the current execution output from the adder 135. The instruction address is compared with the end address of the program module being processed, which is selected and output by the selector 132. If the two addresses match, the read select control unit 133, the program counter 13
4, and outputs an end address match signal to the upper processor 151.

The program storage 137 (storage means)
Stores the program module to be processed.
The instruction to be executed is output according to the absolute address output from the adder 135.

The operation unit 138 (instruction execution means) executes various instructions output from the program storage unit 137. The arithmetic unit 138 is also capable of executing an instruction (hereinafter, referred to as a “rewrite instruction”) for rewriting the contents (a start address and an end address) held in the address storage units 111. When the rewrite instruction is executed, the arithmetic unit 138 outputs a write select signal indicating which of the address storage units 111... An address is to be written to the address storage device 100, and outputs the write select signal via a selector 152 described later. ,
The write address is output to the address storage device 100. As a result, the start address and the end address held in the address storage device 100 can be rewritten, and when the processing of a certain program module is completed, the next program module to be processed can be flexibly changed. The operation unit 138 may be configured to execute a conditional branch instruction or an unconditional branch instruction for rewriting a value held in the program counter 134, similarly to a normal arithmetic unit.

The host processor 151 controls the entire system including this arithmetic unit. Regarding the branch control of the arithmetic unit, the upper processor 151 outputs a write select signal to the address storage device 100 and, via the selector 152, the address storage device 100.
The write address is output to. As a result, the start address and the end address held in the address storage device 100 can be rewritten, and the program module to be processed next can be flexibly changed when the processing of a certain program module is completed. . In addition, when the head address and the end address are rewritten by the upper processor 151 as described above, an instruction cycle for the operation of the arithmetic unit 138 is not required, so that the arithmetic unit can process the program module at high speed. Can be. It should be noted here that, in principle, the start address and end address of the program module being processed cannot be rewritten. Therefore, the upper processor 1
An end address match signal is input to the comparison unit 136 from the comparison unit 136, and the upper processor 151 rewrites the address by interrupt processing at the timing when the end address match signal is input. In addition,
A register is provided in which a flag indicating that address rewriting is permitted (that is, the program module is not being processed) in accordance with the end address match signal output from the comparing unit 136 is provided.
The 51 may monitor the flag at a predetermined timing, and rewrite the address when the flag is set.

The selector 152 selects a write address output from the arithmetic unit 138 or the host processor 151 and outputs it to the address storage device 100.

Next, the operation of the arithmetic unit configured as described above will be described with reference to FIG. FIG. 2 is a flowchart showing the operation of the arithmetic unit.

(Step ST11) First, when the processing of the first program module is started, the address storage device 1 is controlled by, for example, the host processor 151.
00, the read select control unit 133 and the program counter 134 are initialized. More specifically, the start address and the end address of each program module to be sequentially processed are stored in the address storage device 100. The read selection control unit 133 sets the selectors 131 and 132 so as to select the start address storage unit 111 or the end address storage unit 121 that holds the start address or the end address of the program module to be processed first. Is done. Further, the program counter 134 is reset.

(Step ST12) The start address held in any of the start address storage units 111 to 113 selected by the selector 131 and the relative address held in the program counter 134 are loaded into the adder 135. You.

(Step ST13) The adder 135
The loaded start address and the relative address are added, and the obtained current execution instruction address is output to the comparison unit 136 and the program storage unit 137. Thereafter, the processing after (step ST14) (performed by the comparing unit 136 and the like) and the processing after (step ST19) (the calculating unit 13)
8 is performed in parallel.

(Step ST14) The comparing section 136
The current execution instruction address output from the adder 135 and the end address storage unit 12 selected by the selector 132
A comparison is made with the end address held in any one of 1 to 123.

(Step ST15) The above (Step S15)
If the current execution instruction address and the end address do not match in T14), the program counter 134 is counted up, and the processing from (ST12) is repeated.

(Step ST16) On the other hand, if the current execution instruction address and the end address match in the above (Step ST14), the comparing section 136 reads out the end address match signal, and selects the control section 133, the program counter 134, And outputs it to the host processor 151.

(Step ST17) When the end address coincidence signal is input to the read select control unit 133, the read select control unit 133 sets the start address and the end address of the next program module to be processed. Read select signals for selecting the storage units 111.
Output to When the end address match signal is input to the program counter 134, the program counter 1
34 is reset. After that, (step ST12)
Subsequent processing is repeated. That is, when the last instruction of a certain program module is executed, regardless of the content of the instruction, the selection of the address storage units 111 is automatically switched, so that an instruction cycle for branching is required. In the next instruction cycle, the instruction of the next program module can be executed.

(Step ST18) When the end address match signal is input to the upper processor 151 as an interrupt signal, the upper processor 151 determines whether or not the start address and the end address need to be rewritten. If any, any of the address storage units 111 ...
A write select signal indicating whether an address is to be written to the address storage device 100 is output to the address storage device 100, and a write address is output to the address storage device 100 via the selector 152. This flexibly changes the program module that is processed immediately after or when the currently executed instruction address matches the end address. Here, whether or not the address rewriting is necessary is determined, for example, by the execution result of the instruction by the arithmetic unit 138, the state of each unit of the system including the arithmetic unit, which program module is being processed, The start / end address of the program module is stored in the address storage unit 11.
.. (Selectors 131 and 13)
2 selects which address storage unit 111 ...)
And so on.

(Step ST19) On the other hand, when the current execution instruction address output from the adder 135 in the above (Step ST13) is input to the program storage unit 137,
The instruction stored at that address is fetched by the operation unit 138.

(Step ST20) The operation unit 138 executes the fetched instruction. Here, if the instruction to be executed is a rewrite instruction for rewriting the content held in the address storage units 111..., The arithmetic unit 138 performs a write select indicating which of the address storage units 111. A signal is output to the address storage device 100, and a write address is output to the address storage device 100 via the selector 152. In this case, the program module to be processed can be flexibly changed without depending on the host processor 151.

Next, the specific storage contents of the address storage device 100 when the above operation is performed will be described.

(1) For example, as shown in FIG. 3, the address in the program storage unit 137 is (0100 to
(0110), (0120 to 0130),... (Hexadecimal notation) store four program modules 1, 2,..., And these program modules are sequentially and repeatedly processed. In this case, at the time of the initialization processing (step ST11), the address storage units 111 of the address storage device 100 are connected.
Next, as shown in FIG.
3 are stored. In addition, the read select control unit 133 includes, for example, the selector 131.1
32 is set to select the address storage units 111 and 121.

(2) In the first instruction cycle, the adder 135 outputs the start address (0100) of the program module 1 output from the start address storage unit 111 selected by the selector 131 and the program counter 134. The relative address (0000) is added, and the absolute address (0100) of the addition result is output to the program storage unit 137. Therefore, the instruction stored in the area of the absolute address (0100) in the program storage unit 137 is fetched by the arithmetic unit 138 and executed. At this time, since the end address stored in the end address storage unit 121 is (0110), the comparison unit 1
The end address coincidence signal is not output from 36, and the relative address held in the program counter 134 is counted up to (0101), for example.

(3) In the next instruction cycle, the instruction in the area of the absolute address (0101) output from the adder 135 in the program storage unit 137 is executed by the arithmetic unit 138 in the same manner as in (2). At the same time, the relative address held in the program counter 134 is further counted up.

(4) Thereafter, the same operation is performed, and when the relative address held in the program counter 134 becomes (0010), the absolute address output from the adder 135 becomes (0110). The corresponding instruction is executed by the arithmetic unit 138, and the absolute address matches the end address stored in the end address storage unit 121. Therefore, the comparison unit 136 reads the read select control unit 133, the program counter 13
4, and an end address match signal is output to the upper processor 151. Then, the selector 131 and the selector 132 are switched so as to select the start address storage unit 112 or the end address storage unit 122, and the program counter 134 is reset.

(5) Then, in the next instruction cycle and thereafter, the instruction (program module 2) in the area of the program storage unit 137 whose absolute address is (0120) or later is executed.

(6) The same operation is repeated until the absolute address in the program storage unit 137 becomes (015)
When the last instruction of the program module 3 stored in the area (0) is executed, the selector 131 and the selector 132 are switched again to select the start address storage unit 111 or the end address storage unit 121, and , The program counter 134 is reset. At this time, the upper processor 151 rewrites the contents stored in the address storage units 111... As shown in FIG. 4B according to the end address match signal input from the comparison unit 136. (Note that the address storage unit 1
11 and 121 and the address storage units 112 and 122 may be rewritten after the processing of the program modules 1 and 2 ends and before the processing of the program module 3 ends. Therefore, in the next instruction cycle, the processing of the program module 4 is started. Hereinafter, similarly, by switching the selection by the selectors 131 and 132 and rewriting the address storage device 100, the program modules 1 to 4
Are sequentially and repeatedly performed.

The program modules 1 to 4 as described above
Another method for performing the repetition processing of the address storage device 1 is as follows.
In this method, the rewriting of 00 is performed by the execution of the rewriting instruction by the arithmetic unit 138, instead of being controlled by the upper processor 151. That is, for example, by executing a rewrite instruction during the processing of each program module, the start / end address of the next program module to be processed is stored in the address storage unit 111. If you store it,
Again, the processing of each program module can be performed sequentially.

However, when the number of program modules to be processed is the same as the number of head address storage units 111..., The selectors 131 and 132 sequentially store addresses without rewriting the storage contents of the address storage device 100. By simply selecting the unit 111, the processing of each program module is automatically repeated. When the number of program modules to be processed is smaller than the number of head address storage units 111 (for example, two), for example, as shown in FIGS. The contents stored in the address storage device 100 may be sequentially rewritten in the same manner as in the first case, but the read select control unit 133 may be reset when the last instruction of the program module 2 is executed, or the read select control may be performed. The number of stages of the unit 133 may be set to two.

The upper processor 151 and the operation unit 13
8 evaluates the state of each part of the system including the arithmetic unit, and stores the start / end address according to the evaluation result in the address storage unit 111... The order can be changed, and processing of another program module can be performed.

As described above, when the address storage device 100 holds the start / end address of each program module and the current execution instruction address becomes equal to the end address by hardware (without executing a branch instruction). By switching the selection of the start / end address, the processing of each program module can be sequentially performed without requiring an instruction cycle for branching, so that the total operation processing time can be reduced.

In the above example, the address storage device 1
00, three start address storage units 111 to 11
3, and an example in which the end address storage units 121 to 123 are provided. However, the present invention is not limited to this, and any number of storage units may be provided. If the start / end address is rewritten each time the program ends, the program module to be processed can be switched without executing the branch instruction.

In the above example, the program counter 1
Although the example in which the relative address is held in the memory 34 is shown, the absolute address may be held. Specifically, the head address (absolute address) output from the selector 131 is preloaded into the program counter 134 at the timing of resetting the program counter 134, and the output of the program counter 134 is directly stored in the program storage unit 137. You just need to enter it.
In this case, the bit length of the program counter 134 needs to be increased, but the adder 135 does not need to be provided. (Embodiment 2) As Embodiment 2 of the present invention, in order to detect the end of processing of each program module, instead of the end address which is an absolute address, the processing length which is the length of each program module, that is, An example of an arithmetic unit using the relative address of the last part with respect to the head of each program module will be described. In the following embodiments, components having the same functions as those in the first embodiment and the like will be assigned the same reference numerals and descriptions thereof will be omitted.

The main difference between the arithmetic unit according to the second embodiment and the arithmetic unit according to the first embodiment is that, as shown in FIG. An address / processing length storage device 200 having a small number of processing length storage units 221 to 223 (processing length holding means) is provided. Accordingly, the selector 23
2 (processing length selection means) and the comparison unit 236 having a smaller number of bits than in the first embodiment. Further, the current execution instruction address (absolute address of the instruction to be executed) output from the adder 135 is not input to the comparison unit 236, but the program counter 13
4, ie, the relative address from the beginning of the program module in the current execution instruction is input.

In the operation of the arithmetic unit configured as described above, as shown in FIG. 7, in step ST14 of the first embodiment (FIG. 2), the adder 1 is added by the comparing unit 136.
The current execution instruction address output from the selector 35 and the selector 13
2 is compared with the end address selected in step ST2, whereas in step ST24, the comparing unit 236
The relative address held in the program counter 134 is compared with the processing length selected by the selector 232. The other operations are the same as those of the first embodiment. Therefore, the processing of each program module can be sequentially performed without requiring an instruction cycle for branching. Can be shortened. In addition, since a processing length with a small amount of data (number of bits) is used instead of the end address which is an absolute address (real address), the hardware scale for holding, selecting, and comparing data is reduced. Can be suppressed. (Third Embodiment) As a third embodiment of the present invention, a buffer for holding a write address output from the upper processor 151 is provided, so that the upper processor 151 can execute processing of the program module at an arbitrary timing. Describes an example of an arithmetic unit that can output a write address asynchronously.

As shown in FIG. 8, the arithmetic unit according to the third embodiment is provided with an address storage device 300 for holding a write address output from the host processor 151. More specifically, the address storage device 300
, Like the address storage device 100, correspond to the start address storage units 311 to 313 (start address holding means for the upper processor) for holding the start address and the respective start address storage units 311 to 313, and hold the end address. Ending address storage units 321 to 323 (end address holding means for upper processor). The address storage device 300 is also configured using, for example, a register as described for the address storage device 100 in the first embodiment, but may be configured using a memory.

Each of the address storage units 311 to 313.3
The write addresses output from 21 to 323 are input to selectors 331 to 336 together with the write address output from operation unit 138.
That is, the selector 331 to 336 selects the write address output from the upper processor 151 and the write address output from the arithmetic unit 138 by executing the rewrite instruction stored in the program storage unit 137. ing. The selectors 331 to 331
336 are address storage units 111 to 113.
121 to 123 are connected.

Further, the arithmetic unit is provided with a timing control section 361 for controlling the timing of writing the address held in the start address storage sections 311 to the start address storage sections 111. More specifically, the timing control unit 361 includes a start address storage unit 111.
Is the address to be written to the head address storage unit 31
Are held at the timing when the end address coincidence signal is output from the comparison unit 136, that is, at the timing when writing to the start address storage units 111 is possible, the start address storage unit 311 by the selectors 331 to 336 is used. ... and the start address storage unit 111 ...
Are output to the selectors 331 to 336 and the address storage device 100, indicating a selection of one or more start address storage units 111 to which an address is to be written.

Next, the operation of the arithmetic unit configured as described above will be described with reference to FIG. FIG. 9 is an explanatory diagram showing the write timing of the start / end address.

The writing of the start / end address to the address storage device 300 by the upper processor 151 is performed at arbitrary timings A1 and A2 regardless of the processing timing of the program module. That is, since the processing of the program module is not affected only by writing the address to the address storage device 300, the upper processor 151 waits for the processing of the program module being processed to be completed, or There is no need to perform an interrupt process, and the address can be output at a timing according to the process of the host processor 151 itself.

On the other hand, the rewriting of the start / end address stored in the address storage device 300 into the address storage device 100 is controlled by the timing control unit 361, for example, at the timing B0 every time the processing of three program modules is completed. The program modules that are executed in B1 and B2 and are sequentially processed are changed. (Note that, in FIG. 9, a gap is drawn for each of the three program modules for convenience, but a waiting time does not actually occur.) By controlling the rewriting timing in this way, for example, a certain program During the processing of the module, a malfunction due to a change in the start / end address held in the end address storage units 121... Corresponding to the program module is prevented.

As described above, the address storage device 100
The branch control based on the start / end address held in the first embodiment is the same as in the first embodiment,
Again, the processing of each program module is performed sequentially without requiring an instruction cycle for branching, so that the total operation processing time can be reduced. In addition, since the address output from the upper processor 151 is temporarily stored in the address storage device 300 as described above, appropriate processing of the program module is guaranteed, and the waiting for writing by the upper processor 151 is eliminated.
The processing efficiency of the host processor 151 can be improved.

In the above example, the address storage device 3
00, three start address storage units 311 to 31 respectively.
3, and an example in which the end address storage units 321 to 323 are provided, but the number is not limited to three as described for the address storage device 100 in the first embodiment. Also, the number may not be the same as that of the head address storage units 111 of the address storage device 100.

FIG. 9 shows an example in which the start / end addresses are rewritten for each of the three program modules. However, the present invention is not limited to this, and the rewrite may be performed for each program module at a different timing. .

Also in the third embodiment, the processing length may be used instead of the end address, as in the second embodiment.

Also, as described above, the address storage device 30
0, instead of between the address storage device 100 and the selectors 131 and 132 or the selectors 131 and 1.
A buffer may be provided between 32 and the adder 135 / comparator 136. In this case, if the writing of the address to the buffer is controlled by the timing control unit 361 as in the above case, the address storage device 10
Writing to 0 can be performed at any timing. (Embodiment 4) As Embodiment 4 of the present invention, an example of an arithmetic unit using a memory as an address storage device will be described. In this arithmetic unit, the end of the processing of the program module is detected by an end flag included in the instruction. Hereinafter, a specific description will be given with reference to FIG.

In FIG. 10, an address storage device 400
Is provided with a memory 410. Memory 4 above
Reference numeral 10 indicates that a predetermined storage area functions as start address storage sections 411 to 413 in which start addresses of respective program modules to be processed are stored. The selection of the head address stored in the head address storage units 411 to 413 to be output to the adder 135 depends on the address of the head address storage unit 411 to 413 in which the head address to be output is stored. Is controlled by an address register 433 (address designating means) for storing (The memory 410 also has the same function as the selector 131 of the first embodiment.) As the address register 433, specifically, for example, an end flag detection signal is output from an end flag detection unit 436 described later. For each, the start address storage unit 411
A counter that sequentially outputs addresses corresponding to .about.413 is used.

The head address held in the address storage device 400 is rewritten by the upper processor 151 via the address storage device 470. The address storage device 470 is provided with one head address storage unit 471, and the head address storage unit 471 includes the head address and the head address storage unit 41 to which the head address is to be written.
The configuration is the same as 300 of the third embodiment (FIG. 8) except that any one of addresses 1 to 413 is held. Note that a plurality of head address storage units 471 may be provided as in the third embodiment. However, in this case, writing to the head address storage units 411 to 413 cannot be performed at the same time. Also, the address storage device 470 may be configured using a memory, similarly to the address storage device 400.

The timing of writing the head address from the address storage device 470 to the address storage device 400 is the same as that of the third embodiment.
61. That is, when a dual-port SRAM or the like is used as the address storage device 400, a new address can be physically written at the same time even when the stored head address or the like is being read. As described in the first embodiment, the timing control unit 361 controls the write timing so that the start address and the end address of the program module being processed are not rewritten in principle. On the other hand, since such control is performed, the host processor 151 can write the head address into the address storage device 470 at an arbitrary timing.

The program storage section 137 is provided in the first embodiment.
Is stored in the program storage unit 137. The instruction stored in the program storage unit 137 has a plurality of bits indicating the content of the instruction, and the flag bit is set so that the last instruction of the program module is set. Is provided. (Note that whether a bit string including the end flag bit is referred to as an instruction as described above, or whether only a bit string indicating the content of the instruction is referred to as an instruction,
Not an essential matter. That is, for example, the operation unit 138
However, the actual operation is the same between fetching the former as an “instruction” and executing it ignoring the end flag bit thereof, and fetching and executing only the latter as an “instruction”. . The end flag detection unit 436 checks whether or not the end flag bit is set when the arithmetic unit 138 fetches an instruction from the program storage unit 137. Address register 433, program counter 13
4, and outputs an end flag detection signal to the timing control section 361.

Next, the operation of the arithmetic unit configured as described above will be described with reference to FIG. FIG. 11 is a flowchart showing the operation of the arithmetic unit.

(Step ST 31) First, when the processing of the first program module is started, the address storage device 4 is controlled by, for example, the host processor 151.
00, the address register 433, and the program counter 134 are initialized. More specifically, the head address of each program module to be sequentially processed is stored in a predetermined address area in the address storage device 400. The address register 433 is preloaded with an address of an area in the address storage device 400 in which a start address or an end address of a program module to be processed first is held. further,
The program counter 134 is reset.

(Step ST32) In the address storage device 400, the head address held in the area indicated by the address register 433 and the relative address held in the program counter 134 are
It is loaded into the adder 135.

(Step ST33) The adder 135
The loaded head address and the relative address are added, and the obtained current execution instruction address (absolute address of the instruction to be executed) is output to the program storage unit 137.

(Step ST34) The current execution instruction address output from the adder 135 is stored in the program storage unit 13.
7, the instruction stored at that address is fetched by the operation unit 138. Thereafter, (Step S
T35) and subsequent processes (performed by the end flag detector 436 and the like) and (step ST39) (performed by the calculator 138) are performed in parallel.

(Step ST35) The end flag detection section 436 checks whether or not the end flag bit of the instruction fetched by the operation section 138 is set.

(Step ST36) The above (Step S36)
If the end flag bit is not set in T35), the program counter 134 is counted up, and then the processing after (step ST32) is repeated.

(Step ST37) On the other hand, if the end flag bit is set in the above (Step ST35), the end flag detection section 436 outputs the end flag detection signal to the address register 433, the program counter 134,
And to the timing controller 361.

(Step ST38) When the end flag detection signal is input to the address register 433, the address register 433 stores the held address in the address storage device 400 as the start address of the next program module to be processed. Is updated to the address of the area where is stored. When the end flag detection signal is input to the program counter 134, the program counter 134 is reset. Further, if the start address to be written to the memory 410 is held in the address storage device 470, the timing control unit 361 instructs the address storage device 400 to fetch the start address. Thereafter, the processing of (Step ST32) and subsequent steps are repeated. That is, when the last instruction of a certain program module is executed, the selection of the start address storage units 411 is automatically switched regardless of the content of the instruction, so that an instruction cycle for branching is required. However, in the next instruction cycle, the instruction of the next program module can be executed.

(Step ST39) On the other hand, the instruction fetched in the above (Step ST34) is
Performed by

As described above, the end of the processing of each program module is detected by the end flag bit,
By switching the selection of the end address, the processing of each program module can be sequentially performed without requiring an instruction cycle for branching, and the total operation processing time can be reduced. Also, as in the third embodiment, the address output from the upper processor 151 is temporarily stored in the address storage device 470, so that appropriate processing of the program module is guaranteed, and the writing by the upper processor 151 is awaited. Thus, the processing efficiency of the host processor 151 can be improved. In addition, since only the head address needs to be stored in the address storage device 400, the hardware scale can be reduced. In addition, the components of each of the above embodiments and modifications may be variously combined.

Specifically, for example, the first to third embodiments
A memory may be applied to the address storage device 100 and the like of FIGS. 1, 6, and 8 similarly to the address storage device 400 of the fourth embodiment (FIG. 10). A register may be applied to the address storage device 400.
Further, a memory may be applied to the address storage device 300 or the address storage device 470 of the third and fourth embodiments instead of the register.

As in the third embodiment, the head address storage section 4 is stored in the address storage device 470 of the fourth embodiment.
11 and a plurality of head address storage units 471
May be provided. Thus, each head address storage unit 47
1 and the start address storage units 411... Are predetermined, the start address storage units 471.
It is not always necessary to store information indicating the start address storage units 411 to which the start address is to be written (along with the start address).

In the address storage device 300 as a buffer according to the third embodiment (FIG. 8), instead of the end address storage units 321..., The processing length is set as in the processing length storage units 221. It is also possible to provide a processing length storage unit (processing length holding means for upper processor) for holding.

The configuration for detecting the last instruction by the end flag as in the fourth embodiment may be applied to the arithmetic units of the first to third embodiments.

In the fourth embodiment as well, the head address may be rewritten not only by the upper processor 151 but also by the execution of the instruction by the arithmetic unit 138 or only by the execution of the instruction. , In another embodiment, the upper processor 15
1 or the operation unit 138 may be rewritten. Further, the head address or the like may be substantially rewritten by another method, and the fixed branch processing can be performed at high speed without necessarily rewriting. As a configuration in which the head address or the like is rewritten by the other method described above, for example, the end address of the program module and the head address of the next module are stored in a predetermined area such as a work area at the head of the program module. For example, a transfer mechanism may be provided to store the end address and the like to the start / end address storage unit or the like during processing of the program module.

In the fourth embodiment, as in the first and third embodiments, the address storage device 470 and the timing control unit 361 are not provided, and the upper processor 151 controls the write timing of the head address. Good.

In addition, the following modifications are also possible.

In the above example, the read select control unit 1
33 and the address register 433, when the last instruction is detected, automatically select the start address and the like of the next operation processing in sequence, but the selection is performed by the upper processor 151 or the operation unit 138. May be controlled. In this case, the processing order of the program modules whose head addresses and the like are already stored in the address storage device 100 or the like can be changed without changing the contents stored in the address storage device 100 or the like.

Although the start address and end address have been described as absolute addresses, it is easy to use a relative address from the address of the last instruction before branching or a relative address for modifying a predetermined base address. it can.

In the above example, the branch destination when the last instruction is detected is uniquely determined. However, the present invention is not limited to this. For example, a plurality of address storage devices are provided, and a state such as a zero flag is set. One of the address storage devices may be selected accordingly. In this way, as in the case of executing a conditional branch instruction, the program module to be processed can be changed according to the operation result, the state of the device, and the like. In this case, as described above, the branch condition (for example, a mask indicating which flag of the flag register is used as the branch condition) and the start address of a program module to be processed when the branch condition is satisfied are also stored in the program. It may be stored at the head of the module or the like.

[0080]

As described above, according to the present invention, without executing a branch instruction, that is, without requiring an instruction cycle of a branch instruction, detection of the last instruction of the arithmetic processing by hardware allows the next arithmetic processing to be performed. Since branching can be performed, arithmetic processing that requires branching can be performed at high speed, and the total arithmetic processing time can be shortened. Also,
The operation processing at the branch destination can be controlled by execution of an instruction or an upper processor, so that the processing content can be flexibly changed according to various conditions.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an arithmetic unit according to Embodiment 1 of the present invention.

FIG. 2 is a flowchart showing the operation of the arithmetic unit.

FIG. 3 is an explanatory diagram showing an example of a storage state of a program module processed by the arithmetic unit.

FIG. 4 is an explanatory diagram showing an example of contents stored in an address storage device 100 of the arithmetic unit.

FIG. 5 is an explanatory diagram showing another example of the storage content of the address storage device 100 of the arithmetic unit.

FIG. 6 is a block diagram illustrating a configuration of an arithmetic unit according to Embodiment 2 of the present invention.

FIG. 7 is a flowchart showing the operation of the arithmetic unit.

FIG. 8 is a block diagram illustrating a configuration of an arithmetic unit according to Embodiment 3 of the present invention.

FIG. 9 is an explanatory diagram showing an example of a write timing of a start / end address of the arithmetic unit.

FIG. 10 is a block diagram illustrating a configuration of an arithmetic unit according to a fourth embodiment of the present invention.

FIG. 11 is a flowchart showing the operation of the arithmetic unit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 address storage device 111-113 start address storage unit 121-123 end address storage unit 131/132 selector 133 read select control unit 134 program counter 135 adder 136 comparison unit 137 program storage unit 138 arithmetic unit 151 high-order processor 152 selector 200 address Processing length storage devices 221 to 223 Processing length storage unit 232 selector 236 comparison unit 300 address storage device 311 to 313 start address storage unit 321 to 323 end address storage unit 331 to 336 selector 361 timing control unit 400 address storage device 410 memory 411 413 Start address storage unit 433 Address register 436 End flag detection unit 470 Address storage unit 471 Start address storage unit

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Takeharu Yamamoto 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. F-term (reference) 5B033 AA02 CA02 CA08 5B060 AB05 BA15

Claims (20)

[Claims] An instruction execution means for executing an instruction stored in a storage means, and an execution instruction address which is an address of an area in the storage means in which the instruction executed by the instruction execution means is stored. An execution instruction address output means for executing the instruction, further comprising: an instruction executed by the instruction execution means;
Detecting means for detecting the last instruction of the arithmetic processing before the branch; and executing instruction address output means, when the last instruction is detected by the detecting means, the arithmetic processing after the branch. A computing unit configured to output a head address which is an address of an area in the storage means in which the first instruction is stored for the first instruction. 2. The arithmetic unit according to claim 1, wherein said execution instruction address output means comprises: a start address holding means for holding a start address for each of a plurality of arithmetic processing in said storage means; And a head address selecting means for sequentially switching and selecting the head address held in the head address holding means each time the last instruction is detected by the head address selecting means. An arithmetic unit configured to output the execution instruction address based on a start address. 3. The arithmetic unit according to claim 1, further comprising: an end address for holding an end address which is an address of an area in the storage means in which a last instruction for each of the plurality of arithmetic processes is stored. Holding means, and end address selecting means for sequentially switching and selecting the end addresses held in the end address holding means each time the last instruction is detected by the detecting means. The means is configured to detect the last instruction based on the execution instruction address output from the execution instruction address output means and the end address selected by the end address selection means. A computing unit characterized in that: 4. The processing unit according to claim 1, further comprising: a processing length holding means for holding a processing length, which is a relative address of an end address to a start address, for each of the plurality of arithmetic processings in said storage means. And a processing length selection means for sequentially switching and selecting the processing length held in the processing length holding means each time the last instruction is detected by the detection means, The output unit generates the execution instruction address by adding the start address of the arithmetic process being processed and the relative address of the execution instruction address with respect to the start address, while the detection unit outputs the relative address, It is configured to detect the last instruction based on the processing length selected by the processing length selection means. An arithmetic unit, characterized in that: 5. The arithmetic unit according to claim 1, wherein said detecting means is stored in said storage means in correspondence with information indicating contents of an instruction executed by said instruction executing means. An arithmetic unit configured to detect the last instruction based on information indicating that the instruction is an instruction. 6. The arithmetic unit according to claim 2, wherein said starting address holding means includes a plurality of registers each holding said starting address, and said starting address selecting means includes: An arithmetic unit comprising a selector for selecting any one of them. 7. The arithmetic unit according to claim 2, wherein said head address holding means includes a memory holding said head address, and said head address selecting means holds said head address in said memory. An arithmetic unit comprising an address designating means for designating an address of an area in which the data is stored. 8. The arithmetic unit according to claim 2, wherein the start address held in said start address holding means can be set by execution of an instruction by said instruction execution means. Arithmetic unit. 9. The arithmetic unit according to claim 2, wherein the head address held by said head address holding means can be set by a host processor controlling the operation of the arithmetic unit. Arithmetic unit. 10. The arithmetic unit according to claim 9, further comprising a head address holding means for the upper processor for holding a head address output from the upper processor, wherein the head address is held by the head address holding means for the upper processor. An arithmetic unit configured to write the start address to the start address holding means at a predetermined timing. 11. The arithmetic unit according to claim 3, wherein said end address holding means includes a plurality of registers each holding said end address, and said end address selection means comprises: An arithmetic unit comprising a selector for selecting any one of them. 12. The arithmetic unit according to claim 3, wherein said end address holding means includes a memory holding said end address, and said end address selecting means holds said end address in said memory. An arithmetic unit comprising an address designating means for designating an address of an area in which the data is stored. 13. The arithmetic unit according to claim 3, wherein an end address held in said end address holding means can be set by execution of an instruction by said instruction execution means. Arithmetic unit. 14. An arithmetic unit according to claim 3, wherein the end address held by said end address holding means can be set by an upper processor controlling the operation of the arithmetic unit. Arithmetic unit. 15. The arithmetic unit according to claim 14, further comprising: an upper processor end address holding unit for holding an end address output from said upper processor, wherein said end unit is held by said upper processor end address holding unit. An arithmetic unit configured to write the ending address to the ending address holding means at a predetermined timing. 16. The arithmetic unit according to claim 4, wherein said processing length holding means includes a plurality of registers each of which holds said processing length, and said processing length selection means includes: An arithmetic unit comprising a selector for selecting any one of them. 17. The arithmetic unit according to claim 4, wherein said processing length holding means includes a memory for storing said processing length, and said processing length selecting means for storing said processing length in said memory. An arithmetic unit comprising an address designating means for designating an address of an area in which the data is stored. 18. The arithmetic unit according to claim 4, wherein the processing length held in said processing length holding means can be set by execution of an instruction by said instruction execution means. Arithmetic unit. 19. The arithmetic unit according to claim 4, wherein the processing length held by said processing length holding means can be set by a host processor controlling the operation of the arithmetic unit. Arithmetic unit. 20. The arithmetic unit according to claim 19, further comprising: a processing length holding unit for a high-order processor for holding a processing length output from the high-order processor, wherein the processing length is held by the processing length holding unit for the high-order processor. Processing length is
An arithmetic unit configured to be written to the processing length holding means at a predetermined timing.