JPH01156850A - Information processor - Google Patents

Abstract

PURPOSE:To increase the processing speed for update processing of program state words due to the fetch of an instruction by supplying an effective memory protection key to an arithmetic register from a selector and at the same time holding the program state word via the arithmetic register after the effective memory protection key supplied from a program state word register is excluded. CONSTITUTION:An effective memory protection key which is updated in response to a fact that an instruction control part 14 takes out an instruction is outputted to an arithmetic register 5 from a selector 13. At the same time, a program state word excluding the effective memory protection key is outputted to the register 5 from a program state word register 8. Then the program state word including the updated effective memory protection key is held by the register 5. Thus a step where the replacement is instructed for the program state word is omitted together with a step where the program state word including the updated effective memory protection key is kept waiting for its holding state at the register 8. As a result, the update processing speed is increased for the program state word.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention has a pipeline, a microprogram controls operations, and a register for holding a program state word on the pipe below the operation execution unit. It relates to an information processing device.

(Prior Art) FIG. 4 is a block diagram of the main parts of a conventional example of this type of information processing device.

The instruction control unit 20 includes a 64-bit operation code register 1 that holds an operation code retrieved by instruction fetch, a decoder 2 that decodes the operation code, and a main memory that stores instruction operands based on the output of the decoder 2. It consists of an address generation circuit 3 that generates an address within the memory, and an operand extraction circuit 4 that extracts an operand from the main memory based on the address. The microprogram control unit 15 has a capacity of 65536 words and 16 bytes per word.
A control memory 9 having a capacity of 4096 words stores a part of a microprogram having a 6-bit micro logical address, and a control memory 9 which holds the address of the control memory 9 supplied from the decoder 2 and which is subsequently executed. It consists of a 16-bit control address register lO, which holds the address in the control memory 9 of the microprogram supplied from the control memory 9, and a 64-bit microprogram register 11, which holds the microprogram read out from the control memory 9. . Program status word register 8
6 is a register that holds and displays the system state related to the currently running program, including the execution memory protection key.
It is composed of 4 bits, and the 3 bits 13 to 15 hold an effective storage protection key indicating permission/prohibition regarding reading, storing, and executing reference information of an execution program. The arithmetic execution unit 16 includes a program state word held in the program state word register 8, a plurality of 64-bit arithmetic registers 5 that hold operands taken out from the operand takeout circuit 4, and a program state word held in the microprogram register 11. An arithmetic circuit 6 with 64-bit input and 64-bit output that inputs data held in an arithmetic register 5 and performs arithmetic operations (logical, arithmetic, and comparison operations) under the control of a microprogram that operates, and holds the arithmetic results. , a 64-bit write register 7 that writes to the program status word register 8. Note that the arithmetic circuit 6 is capable of performing separate arithmetic operations for each 32 bits.

FIG. 5 is a flowchart of a microprogram that executes an instruction to read out a program status word updated by extracting an instruction in the information processing device of FIG. 4, change it, and then update it as a new program status word;
FIG. 6 is a time chart of each step of the microprogram executed on each pipeline of the information processing apparatus shown in FIG.

First, at time To, a microprogram for a program status word update instruction is held in the microprogram register 11, and the instruction is issued (step 51). Time TsS5
Then, at time T2, a microprogram instructing to wait for update of the program status word in the program status word register 8 is held in the microprogram register 11, and the instruction is issued (steps 52 and 53). At time T3, a microprogram with an instruction to fetch the updated program status word held in the program status word register 8 and operand data from the operand fetching circuit 4 is held in the microprogram register 11, and the instruction is is carried out (step 53). At time T3, the instruction of step 54 is executed in operation register 5, and at time T4, the updated program status word and operand data are held in operation register 5. Also, at time T4, the updated program status word and operand data held in the arithmetic register 5 for the arithmetic circuit 6 are manually inputted into the microprogram register 11 to instruct the arithmetic addition and logical product operations, and to write the result of the arithmetic operation. The microprogram for holding the write register 7 is held in the microprogram register 11, and the instruction is issued (step 55). As a result, the calculation of step 55 is executed in the calculation circuit 6, and the calculation result of step 55 is held in the write register 7 at time T. Also at time T5,
A microprogram for instructing the program state word register 8 to take in the output of the write register 7 as a new program state word is held in the microprogram register 11, and the instruction is issued (step 56). As a result, the output of this write register is held in the program state word register 8 as a new program state word at time T6.

[Problem that the invention seeks to solve]

In the conventional information processing device described above, a microprogram corresponding to an instruction fetched by an instruction control section is executed by a microprogram control section, and a program state word to be updated is generated by fetching an instruction. The execution unit was instructed to change the program status word to , and the program status word register was controlled to hold the operation result of the execution unit as a new program status word, so it was updated by fetching the own instruction. In order to execute an instruction to fetch and change a program state word and then update it as a new program state word, the microprogram must first use the effective memory protection key that has been updated by fetching its own instruction, as shown in Figure 5. A program state word update instruction is issued to obtain the instruction, and the updated program state word is fixed in the program state word register that holds the program state word existing on the pipe below the operation end. Control is performed at the timing shown in Figure 6, such as waiting until the end of the program, extracting the program status word, changing it, and then updating it as a new program status word, resulting in a decrease in instruction execution performance and an increase in the capacity of the microprogram. There is a drawback.

[Means for solving problems]

The information processing device of the present invention has an effective storage protection key register that holds an effective storage protection key retrieved from the main storage by an instruction control unit fetching an instruction, and an effective storage protection key register that holds an effective storage protection key retrieved from the main storage by an instruction control unit, and an a selector that selects an effective memory protection key held in a memory protection key register or an effective memory protection key included in a program state word currently held in a program state word register, and outputs the selected effective memory protection key to an arithmetic execution unit; It has means for outputting other parts of the program state word held by the program state word register, excluding the effective storage protection key, to the arithmetic execution section. (Function) When the instruction control unit retrieves an instruction, the selector outputs the updated effective memory protection key to the calculation register, and at the same time, the program status word excluding the effective storage protection key is calculated. The program state word containing the updated effective memory protection key output from the program state word register is held in the arithmetic register.
The step of instructing to update the program state word and the step of waiting for the program state word containing the effective protection key updated by the instruction to be held in the program state word register are eliminated.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a main part of an embodiment of an information processing device of the present invention, and FIG. 2 shows a program state word updated by fetching an instruction in the information processing device of FIG. 1 and modified. FIG. 3 is a time chart of each step of the microprogram executed on each pipeline of the information processing device shown in FIG. 1. be.

This embodiment is a 3-bit effective storage protection key register 12, 122, 12 that holds an effective storage protection key retrieved by instruction fetch in the conventional example shown in FIG.
3 on the pipe where the operation code register 1 of the instruction control unit 14 is located, the pipe where the address generation circuit 3 is located, and the pipe where the operand extraction circuit 4 is located. Holds and outputs 1-bit data specifying whether to use the effective memory protection key held in the effective memory protection key register 123 or the effective memory protection key held in the program status word register 8. Specified data register 17. , 172 on the pipe where the address generation circuit 3 is located and the pipe where the operand extraction circuit 4 is located, and also selects the effective storage protection key according to the specification of the designated data register 172 and supplies it to the arithmetic register 5. It has a container 13.

In this embodiment, from the program state word held in the program state word register 8, only the effective memory protection key is outputted to the selector 13 and the rest directly to the calculation register 5 by reading the microprogram.

Next, the operation of this embodiment will be explained using a specific example.

Now, the program status word register 8 is hexadecimal “lFF”.
The program state word 8100001012000'''("represents a hexadecimal number) is held, and the operation code register 1 reads the program state word updated by reading the instruction, changes it, and stores the new program state word. "AFO5C" which is an instruction to update as "AFO5C"
OOO" is held, and the effective memory protection register 12t on the pipe where the operation code register 1 exists contains the effective memory protection key "001"12 obtained by extracting the instruction "AFO5 (:000"). It is assumed that ``(2) represents a binary number) is held.

The instruction "AFO5 (:00G') held in the operation code register 1 is decoded by the decoder 2, and the information of "C000" of bits 16 to 31 of the operation code necessary for address generation is supplied to the address generation circuit 3. At this time, the effective memory protection key "001", 2) is supplied to the effective memory protection key 122 on the pipe where the address generation circuit 3 is located, and the selector 13 supplies the effective memory protection key register to the specified data register 17. 12
A two-way "l" (2) is supplied from the decoder 2, which instructs to select "O old" (2) held by No. 3. On the other hand, the address generation circuit 3 is supplied with bits 16 to 16 of the operation code necessary for address generation, which is supplied from the decoder 2.
A real address is generated using the information of "cooo" in hexadecimal number 31 and "0101300G" is obtained.

In addition, the control memory address register 10 includes a decoder 2.
Therefore, the micro logical address "0604" which is the first step of the first micro program corresponding to the instruction ``AFO5COOO'''' is supplied and held.

The operand retrieval circuit 4 accesses the main memory using the real address "01013000" generated by the address generation circuit 3, and retrieves the operand data "FFFF8000" stored at the real address "01013000".
The byte is taken out and supplied to the arithmetic register 5. At this time, the effective storage protection key "001" (2) is supplied to the effective storage protection key register 123 existing on the pipe where the operand extraction circuit 4 is located. In addition, the selector 13 inputs the effective storage protection key "001" held by the effective storage/protection key register 123 into the specified data register 172.
Bit “l” (2) indicating to select “(2,”
is supplied, and the selector 13 selects the instructed "001" (2).
is selected and supplied to the calculation register 5. The control memory 9 transfers the contents of the microprogram stored in the micro logical address "0604" held by the control memory address register IO to the microprogram register 11.
Output to. This microprogram is executed by being held in the microprogram register 11, and at time T shown in FIG. step old). As a result, the selector 13 selects the effective memory protection key register 123 and supplies the effective memory protection key "001" (2) to the calculation register 5, while the program status word "1FF810000101200"
0' minus the effective storage protection key is input to the calculation register 5. Also, the control memory address register l
O holds the micro logical address "0620" of the second micro program supplied from the control memory 9.

At the next time T, the program state word "lFF91000" containing the updated effective memory protection key is stored in the operation register 5.
01012000”Tooheran F”FFFF8000
” is held, the microprogram register 11 holds the contents of the microprogram stored at the address “0620” of the control memory 9, and the arithmetic circuit 6 stores the updated program status word held in the arithmetic register 5. An instruction to input operand data and perform an arithmetic calculation and an AND operation, and an instruction to hold the operation result in the write register 7 are issued (step 22).As a result, the program status word 'lFF91000010120
For “01012000” of “00”, the command “AF
An arithmetic addition operation is performed to add the instruction length ``4'' of ``O5COOO'', and the instruction ``4'' is added to ``lFF91000''.
AF05COOO@ operand datago FFF800
0'' is performed and the operation result is supplied to the write register 7.The control memory address register 1G is supplied with the micro logic address "062F" of the microprogram from the control memory 9 and holds it.At the next time T2 The write register 7 receives the calculation result “1FF90000” which should become a new program status word supplied from the calculation circuit 6.
01012004” is held, and the microprogram register 11 holds the address “062” of the control memory 9.
The contents of the microprogram stored in 1'' are held, and an instruction is given to take the output of the write register 7 into the program status word register 8 (step 23).

This creates a new program status word "lFF9000".
001012004” is provided from write register 7 to program status word register 8.

At the next time T3, the program state word register 8 contains a new program state word "lFF9000001012004".
hold.

(Effects of the Invention) As explained above, in the present invention, when the instruction control unit takes out an instruction, the selector supplies the updated effective storage key to the operation register, and the program is programmed at the same time. By storing the effective memory protection key supplied from the status word register in the removed program state word and operation register, the step of program state word update instruction and the program state including the effective memory protection key updated by fetching the instruction are performed. This eliminates the need for the step of waiting for the word to be held in the program state word register, which has the effect of increasing the speed of program state word update processing by fetching instructions and reducing the capacity of the microprogram.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a main part of an embodiment of an information processing device of the present invention, and FIG. 2 shows a program state word updated by fetching an instruction in the information processing device of FIG. 1 and modified. 3 is a flowchart of a microprogram that executes an instruction to update the program status word to a new program state word; FIG. 3 is a time chart of each step of the microprogram executed on each pipeline of the information processing device of FIG. 1; FIG. 4 is a block diagram of the main part of a conventional example of an information processing device, and FIG. 5 is a block diagram of a main part of a conventional example of an information processing device, and FIG. FIG. 6 is a flowchart of a microprogram that executes an instruction to update as a status word, and FIG. 6 is a time chart of each step of the microprogram executed on each pipeline of the information processing apparatus of FIG. 1----Operation code register, 2----
--Decoder, 3-----Address generation circuit, 4...-Operand extraction circuit, 5.--Arithmetic register, 6--------Arithmetic circuit, 7
--------Write register, 8---Program status word register, 9--Control memory, 10--Control memory address register, 11-----
Microprogram register, 12, #123---
--- Effective memory protection key register, 13 --- Selector, 14 - one instruction control section, 15 --- Micro program control section, 16 --- Operation execution section, 17 Otori, 17 , --- one designated data register.

Claims (1)

[Scope of Claims] An instruction control unit that has a pipeline and retrieves an operation code and effective storage protection key by fetching instructions, decodes the operation code, generates an address, and retrieves an operand, and an instruction supplied from the instruction control unit. A new program state of the program state word updated by controlling the arithmetic execution unit by executing a predetermined microprogram according to instructions from the instruction control unit and extracting the operation code. The program status word is located on the pipe below the microprogram control unit that instructs updates to the program, and the program status word that maintains and displays the system status related to the currently running program, including the effective memory protection key. In an information processing device having a program state word register that holds a program status word register, an effective memory protection key register that holds an effective memory protection key retrieved from a main memory by an instruction control unit fetching an instruction, and an instruction from a decoder or a microprogram. Under the control of , the effective memory protection key held in the effective memory protection key register or the effective memory protection key contained in the program state word currently held in the program state word register is selected and output to the calculation execution unit. An information processing device comprising: a selector for outputting a program state word held in a program state word register, excluding an effective storage protection key, to an arithmetic execution unit.