JPS6226485B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in microprogram controlled computers.

In microprogram controlled calculators,
An execution routine consisting of a microprogram is provided corresponding to each user instruction forming a user program, and the function of the user instruction is realized by executing this execution routine. Therefore, processing speed can be improved by reducing the number of steps in the execution routine.

Incidentally, a register (CCR) is generally provided to store a condition code (CC) for decision branching of a user program. The condition code indicates the state of the operation result based on the user's instruction. Similarly, a register (FLGR) is provided to store a flag (FLG) for decision branching of microinstructions in an execution routine. The flag indicates the state of the operation result of the microinstruction. Then, the user instruction execution routine that changes the condition code value according to the operation result generates this new CC value in the flag register (FLGR), and in its final step, executes the user instruction.
The value of FLG was moved to the condition code register (CCR). That is, in a user instruction execution routine that involves a change in condition code, a microinstruction for transferring the contents of the FLGR to the CCR is required as the final microstep.

An object of the present invention is to provide a microprogram-controlled computer that improves processing speed by omitting such a transfer step.

The present invention configures the value of the flag in the last microinstruction of the execution routine that implements the function defined in each user instruction (corresponding to the microinstruction of the penultimate step of the execution routine in the prior art). The code is configured so that it can be transferred to the code register. Generally, the last microinstruction differs depending on the execution routine. Therefore, in the present invention, in addition to a first field that specifies the operation content and a second field that specifies the operation target as at least some microinstructions constituting the execution routine, a third field that specifies the extended function is provided. The one with the following is used. If a specific code indicating that this is the last microinstruction of the execution routine is added to this third field, the above-described transfer operation is performed in addition to the original function of that microinstruction.

The final microinstruction of the execution routine is
There are cases in which the flag changes and cases in which it does not occur.If the flag does not change, the value already stored in the flag register is transferred to the condition code register. If the last microinstruction in the execution routine involves a flag change, the value of the flag generated by the execution of this microinstruction is directly set in the condition code register.

FIG. 1 shows a block diagram of an embodiment of the present invention. In the figure, 1 is the main memory (MM) that stores user programs, etc., 2 is the memory address register (MAR) that holds the address of MM1, 3 is the instruction register (IR) that holds the user instructions to be executed, and 4 is the A decoder (DE) decodes the operation code of the user instruction and outputs the start address of the execution routine. 5 is a control memory (CROM) that stores the execution routine consisting of a group of microinstructions corresponding to the user instruction. 6 is the CROM 5. Address register (RAR) that holds addresses; 7 is microinstruction register (MIR) that holds microinstructions to be executed; 8 is decoder (DEC) that decodes microinstructions and generates various control signals; 9 is arithmetic unit (ALU), 10 is a register group (RF) that holds data to be calculated, 11 is a flag generator (FG) that generates a flag (FLG) based on the calculation result of ALU9, 12 is FLG generated by FG11 13 is a selection circuit (SEL), and 14 is a condition code register (CCR) that holds a condition code (CC) indicating the state of the operation result of the user instruction.

Each user instruction constituting the user program in MM1 is sequentially read out according to the designation of MAR2 and set in IR3. The function specified by each user command can be distinguished by its operation code. This operation code is
Supplied to DE4. DE4 RARs the start address of the execution routine corresponding to the user instruction in IR3
Output to 6. As a result, execution of the execution routine corresponding to the user command in the IR 3 stored in the CROM 5 is started. First, the microinstruction corresponding to the start address is taken out from CROM5 and set in MIR7. Microinstructions in MIR7 are decoded by DEC8, ALU9, RF10
etc., the operation specified by this microinstruction is performed. When this operation is completed, the next microinstruction is taken out from the CROM 5, set in the MIR 7, and executed. Similarly, when the execution routine ends, the next user instruction is fetched from MM1 to IR3.

By the way, when a branch instruction, for example, is taken out from the user program to the IR 3, the condition code (CC) in the CCR 14 is checked, and it is determined whether or not to branch depending on whether the value matches the branch condition. If the branch condition is met, the branch destination address of the branch instruction is set to MAR2, and MM
The branch destination user instruction is extracted from 1 and processing proceeds.

Similarly, in the execution routine, for example, when a micro branch instruction is taken out by MIR7, a mechanism not shown in the figure checks the flag (FLG) in FLGR12, and it is determined whether or not to branch depending on whether the value matches the branch condition. be done. If the branch condition is met, RAR the branch destination address of the micro branch instruction.
6, fetch the branch destination microinstruction from CROM 5, and proceed with the process.

There are various types of microinstructions that make up the execution routine in CROM5, but the typical
The format of the Register to Register type is shown in Figure 2a. In the figure, the microinstruction consists of 20 bits, including a 6-bit OP field, a 5-bit D field, a 5-bit S field, and a 4-bit extension field. OP
The field specifies the content of the operation that the ALU 9 should perform. The operation contents include logical operations, arithmetic operations, shifts, etc. The D field and the S field designate a register in the RF 10 as an operation target. And a microinstruction like this
When set to MIR7, its OP field is
Signals that are decoded by DEC8 and control ALU9 and others are generated, and D and S fields are
After the data in the respective designated registers is supplied to the RF9 and is supplied to the ALU9, the ALU9 executes the designated operation. This calculation result is RF9's D
Stored in the register specified by the field.
At this time, depending on the content of the calculation, there may be a change in the FLG. Whether the microinstruction involves changing the FLG is specified by the OP field. OP
When the field is decoded by _DEC81 and it is detected that it specifies an FLG change, the control line 15
FG11 occurred according to the calculation result of ALU9
Set FLG to FLGR12 and SEL13
is controlled to select the output of FG11.
When _DEC81 detects that the OP field of the microinstruction does not specify an FLG change,
SEL13 is controlled to select the output of FLGR12.

Next, the E field of a microinstruction modifies and expands the function of this microinstruction, and in the present invention, this E field contains a specific code,
The presence of END or ENDC indicates that the microinstruction is the last microinstruction in the execution routine. When the E field of the microinstruction of MIR7 is detected to be ENDC by _DEC82 , it is sent to CCR by control line 16.
14 is set to the value selected by SEL13.
Thereafter, the contents of FLGR 12 are cleared by a mechanism not shown. Note that when the E field is END, the contents of the FLGR 12 are cleared by a mechanism not shown, but the FLG is not transferred to the CCR 14.

Figure 3 shows an example of FLG (CC). This FLG
consists of 4 bits, C is 1 if there is a carry in the operation result of ALU9, V is 1 if there is an overflow in the operation result, G is I if the operation result is positive,
L becomes 1 if the operation result is negative. Note that depending on the microinstruction, it may be used with a different meaning.

In such a configuration, several user instruction execution routines can complete their processing with one microinstruction. For example, an addition instruction (user instruction) is realized by one microinstruction shown in FIG. 2b. When the add instruction is set in IR3, the microinstruction shown in FIG. 2b is set in MIR7 as described above. This OP field ADDF is
Addition with FLG change is specified. YD and YS of the D and S fields specify the first and second operands specified by the addition instruction in IR3 as operands of the operation. Therefore, the corresponding operand is supplied from RF9 to ALU9.
When ALU9 executes addition, the result of the operation is the first one.
Stored in the register specified by the operand. The FG11 generates FLG according to the calculation result.
At this time, _DEC81 detects that FLG change is specified, and SEL13 changes to FG11 by control line 15.
Select the FLG where this occurred. On the other hand, the DEC ₈₂ detects the presence of the ENDC code in the E field and sets the output of the FG 11 selected by the SEL 13 to the CCR 14 via the control line 16. Like this ENDC
CC is updated by specifying .

Also, as shown in Figure 2c, the OP field is
ADD specifies addition without FLG change. In this case, SEL13 selects the output of FLG12, so by specifying ENDC, FLGR12 has already been selected.
The FLG that was set to is transferred to the CCR14. This occurs when the execution routine consists of two or more microinstructions, and the new CC value is created by a microinstruction other than the last one in the execution routine, and FLGR1
Used when left in 2.

For microinstructions that are not the last in an execution routine,
ENDC cannot be specified. In this case, only if the microinstruction specifies an FLG change.
The value of FLGR12 is updated. The updated FLG is used for normal purposes in microroutines.

As described above, according to the present invention, the FLG→CC transfer step required at the end of an execution routine is not performed by an independent microinstruction, and an arbitrary microinstruction that specifies the final arithmetic operation of the execution routine can be used. It can be realized when executing an instruction.

Therefore, the number of steps in the execution routine can be reduced and the processing speed can be improved. At its extreme, an execution routine consisting of one microinstruction per user instruction is also possible.

In addition, in the field that specifies the calculation content,
Although it is possible to distinguish between updating FLG and updating CC, the number of codes required for that field and the bit length of the instruction are shorter than in this case.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
Figures a to c and Figure 3 are diagrams for explaining one embodiment of the present invention. 1...Main memory (MM), 5...Control memory (CROM), 7...Micro instruction register (MIR), 8, 8 ₁ , 8 ₂ ...Decoder (DEC),
9... Arithmetic unit (ALU), 10... Register group (RF), 11... Flag generator (FG), 12...
Flag register (FLGR), 13...Selection circuit (SEL), 14...Condition code register (CCR).

Claims (1)

[Claims] 1 Accommodates a group of microinstructions that include as part of them microinstructions that have at least a first field that specifies the content of the operation, a second field that specifies the object of the operation, and a third field that specifies the extended function. a storage device, a microinstruction register for storing microinstructions to be executed sequentially retrieved from the storage device in response to user instructions, a decoder for decoding the contents of the microinstruction register, and a first field of the microinstruction. an arithmetic circuit that performs the arithmetic operation specified by the arithmetic operation circuit; a flag generation circuit that generates a flag indicating the status of the operation result of the microinstruction based on the arithmetic result of the arithmetic circuit; a flag register that stores this flag; and a flag register that stores the flag; and a selection circuit for selecting either the output of the flag generation circuit or the contents of the flag register; sets the output of the flag generator to the flag register when detecting that the first field of the microinstruction to be executed specifies a flag change;
A microprogram characterized in that upon detecting that a third field of a microinstruction to be executed specifies a change in condition code, the selection circuit sets the selected output in the condition code register. Controlled electronic computer.