JP2001308107A - Gate-insulation-type semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method of a gate-insulation-type semiconductor device with high-energy resistance by forming a high-concentration diffusion region for reducing the resistance value of a channel region at the lower part of a source region by the same mask as the source and channel regions using the self-alignment method. SOLUTION: This manufacturing method includes a process that deposits polysilicon 3 or the like as a gate oxide film 2 and a gate electrode at a drain region that is a semiconductor substrate 1, partially etches the polysilicon by masking, and allows a channel region 4 to be partially subjected to ion plantation and thermal diffusion for forming with the polysilicon 3 as the mask; a process that forms a high- concentration ion implantation region by the high-concentration ion implantation in the channel region 4 with the polysilicon 3 as the mask; a process that diffuses the high-concentration ion implantation region by the thermal diffusion to form a heavily doped region 6; a process that isotropically etches 50% of the thickness in the polysilicon 3; and a process that forms a source region 7 by the ion implantation and annealing from a state where one part of the opening part of the polysilicon 3 is masked by resist with the polysilicon 3 that is isotropically etched as the mask.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate semiconductor device and a method of manufacturing the same, and more particularly to a power MOSF.
ET, insulated gate bipolar transistor (hereinafter I
Vertical insulated gate field effect transistor such as GBT).

[0002]

2. Description of the Related Art A power MOSFET has a structure incorporating a parasitic bipolar transistor having a source region as an emitter, a channel region as a base, and a drain region as a collector. Therefore, when an avalanche current of a certain value or more flows due to the breakdown of the PN junction formed between the drain region and the channel region due to the high voltage generated when the current in the inductive load is turned off,
The voltage value, which is the product of the resistance of the channel region immediately below the source region and the avalanche current, turns on the PN junction formed by the channel region and the source region, and the built-in parasitic bipolar transistor turns on, causing a phenomenon of destruction. . This phenomenon is called avalanche destruction.

Further, in the IGBT, there is a problem that the energy withstand capability of the IGBT is reduced every time the trade-off relationship between the collector-emitter ON voltage and the switching time is improved. This mechanism is called latch-up destruction. The mechanism is the same as that of a MOSFET. When a current of a certain value or more flows, a voltage value that is the product of the resistance and current of the channel region immediately below the source region is formed in the channel region and the source region. This turns on the PN junction and turns on the built-in parasitic PNPN thyristor, leading to destruction.

As described above, avalanche destruction in a MOSFET and latch-up destruction in an IGBT cause a voltage value, which is a product of resistance and current in a channel region immediately below a source region, to turn on a PN junction formed between the channel region and the source region. Therefore, a method of reducing the resistance value of the channel region below the source region, making it difficult to turn on the PN junction formed between the source region and the channel region, and improving the breakdown strength has been taken.

Heretofore, as disclosed in Japanese Patent Application Laid-Open No. Hei 5-121747, there has been known a method of reducing the resistance value of the channel region by setting the highest concentration region below the source region in the diffusion profile of the channel region. I have.

However, in this method, the channel region is a region for determining the threshold voltage of the MOSFET and the IGBT. Therefore, as described in Japanese Patent Application Laid-Open No. 5-121747, the concentration of the channel region below the source region is reduced. Even if a profile is set such that the maximum concentration of the channel region is below the source region, it is at most 10
Only about ¹⁷ can do it. At this concentration, the resistance under the source region cannot be sufficiently reduced, so that a device with a high breakdown energy withstand in a small device area cannot be realized, and a low cost and high energy withstand device required by the market is realized. It was impossible at all.

In order to satisfy the needs of the market, the concentration of the channel region below the source region must be 10 ¹⁷ or more. A high-concentration diffusion region of the same conductivity type as the channel region is formed separately from the channel region by the following manufacturing method.

A conventional manufacturing method will be described below with reference to the drawings. 6 to 9 are cross-sectional views showing the steps of manufacturing a conventional insulated gate semiconductor device.

As shown in FIG. 6, first, a gate oxide film 2 and, for example, polysilicon 3 are deposited as a gate electrode in a drain region, which is a semiconductor substrate 1, and the polysilicon 3 is partially etched by masking. Using polysilicon 3 as a mask, channel region 4 is partially formed by ion implantation and thermal diffusion. Next, as shown in FIG. 7, a resist 8 is applied, and a window opening step is performed to perform high-concentration ion implantation by a new masking step. Using the resist 8 as a mask, high-concentration ion implantation (arrows) is performed in the channel region 4. ) To form a high-concentration ion implantation region 5.
Next, as shown in FIG. 8, the high concentration ion region 5 is diffused by thermal diffusion to form a high concentration diffusion region 6. Next, as shown in FIG. 9, a source region 7 is formed by ion implantation and annealing in a state where a part of the opening of the polysilicon 3 is masked with a resist using the polysilicon 3 as a mask. In such a process, the high concentration diffusion region 6 is formed in the channel region 4 below the source region 7.

[0010]

However, in the above-mentioned conventional manufacturing method, the alignment accuracy of the mask aligner when forming the pattern of the resist 8 serving as an ion implantation mask for forming the high-concentration ion implantation region 5 is highly required. If a mask shift occurs, a difference occurs in the resistance value below the source region 7 on the left and right sides of the cell pattern, and the resistance value of the polysilicon 3 whose dimension from the end increases becomes higher. In addition, there is a problem that the parasitic bipolar transistor is turned on and is destroyed at an energy value lower than a design value. In addition, the source region 7 due to mask misalignment
, The high concentration diffusion region 6 diffuses in the lateral direction, the threshold voltage value determined by the channel region 4 becomes higher than the original value, and the variation in the production of the threshold voltage between wafers occurs. There was a problem of doing so.

That is, in the conventional manufacturing method, in order to prevent a reduction in yield due to manufacturing variations in threshold voltage, window opening size variations in the polysilicon 3, window opening size variations in the pattern of the resist 8, and the high-concentration ion-implanted region 5. It is necessary to consider the diffusion depth variation of the high concentration diffusion region 6 formed by thermal diffusion, and the pattern of the resist 8 serving as the ion implantation mask of the high concentration ion implantation region 5 is The design dimensions had to be made larger than originally required.

For this reason, in order to form the high-concentration diffusion region 6 near the end of the polysilicon 3 under the source region 7, it is necessary to increase the diffusion depth. The high-concentration diffusion region 6 near the end of the polysilicon 3 is formed by the side diffusion portion during the thermal diffusion of the high-concentration ion-implanted region 5, so that the sufficient high-concentration required from the design cannot be achieved. It had a very low breakdown energy resistance.

Therefore, in order to realize a high breakdown energy withstand capability, it is necessary to form a high-concentration diffusion region as close as possible to the polysilicon end below the source region.

Therefore, according to the present invention, an ion implantation step for forming a high concentration diffusion region below a source region is performed using polysilicon or tungsten silicide as a mask, and both the channel region and the source region are formed using polysilicon or tungsten silicide as a mask. The self-aligned formation makes it possible to reduce the size of the polysilicon window, the size of the resist pattern used as the ion implantation mask for the high-concentration diffusion region, and the problem of forming the resist pattern. It is an object of the present invention to provide a method of manufacturing a vertical insulated gate field effect transistor having a high energy tolerance and a small variation in the threshold voltage value without depending on the mask aligner accuracy.

[0015]

In order to achieve the above object, the present invention provides a method for forming a high-concentration diffusion region of the same conductivity type as that of a channel region, for example, using polysilicon or tungsten silicide as a mask as a gate electrode. Polysilicon or tungsten silicide isotropically etched to form polysilicon or tungsten silicide.
The side surface of the silicide is side-etched, and thereafter, the source region is formed in the channel region and the high concentration region using the polysilicon or tungsten silicide as a mask.

[0016]

According to the present invention, the channel region, the high-concentration diffusion region and the source region are all formed by self-alignment using polysilicon or tungsten silicide as a mask by the above-mentioned method, so that a low resistance is formed under the source region. The high-concentration diffusion region can be formed at the high concentration as designed in the entire lower part of the source region without passing over the channel region with high accuracy. It is possible to provide a small number of vertical insulated gate field effect transistors.

An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1 to 5 are sectional views showing steps of manufacturing an insulated gate semiconductor device according to an embodiment of the present invention.

First, as shown in FIG. 1, a gate oxide film 2 and, for example, polysilicon 3 as a gate electrode are deposited in a thickness of 2 μm on a drain region which is a semiconductor substrate 1 and the polysilicon is partially etched by masking. Using silicon 3 as a mask, channel region 4 is partially formed by ion implantation and thermal diffusion. Next, as shown in FIG. 2, using the same polysilicon 3 as a mask, a high-concentration ion implantation region 5 is formed in the channel region 4 by high-concentration ion implantation. Next, as shown in FIG. 3, the high-concentration ion implantation region 5 is diffused by thermal diffusion to form a high-concentration diffusion region 6. Next, as shown in FIG.
50% of thickness isotropically with mixed gas of F ₆ and CHClF ₂
1.0 μm (dotted line in FIG. 4). Next, as shown in FIG. 5, a source region 7 is formed by ion implantation and annealing from a state in which a portion of the opening of the polysilicon 3 is masked with a resist using the isotropically etched polysilicon 3 as a mask.

According to the above embodiment, the channel region 4, the high-concentration diffusion region 6 and the source region 7 are all formed by a self-alignment process using polysilicon 3 serving as a gate electrode as a mask material. Unlike the case where the resist 8 (see FIG. 7) formed in the dark room process is used as a mask by ion implantation and thermal diffusion, the high concentration diffusion region 6 is formed in the channel region 4 and the source region 7 in the dark room process. By making the variation and the high-concentration diffusion region shallower than the diffusion depth in the conventional method, the diffusion region is formed below the source region 7 without being affected by manufacturing variations in the depth direction.

In addition to using polysilicon 3 as a mask material and using tungsten silicide, for example, as another electrode material, the same operation as that of polysilicon described above with reference to FIGS. The effect is obtained.

According to the self-alignment process, the ion implantation of the high-concentration ion implantation region 5 is performed at, for example, 180 keV so that the peak concentration of the high-concentration diffusion region 6 is located below the source region 7.
By simply setting these conditions, it is possible to easily form the high-concentration diffusion region 6 under the source region 7 at a higher concentration without adding a special process. When polysilicon or tungsten silicide is used as a mask material, a gate insulating semiconductor device in which the concentration of the high concentration diffusion region 6 below the source region 7 is 10 ¹⁷ or more can be obtained.

[0023]

As described above, the method of manufacturing a gate insulating semiconductor device according to the present invention forms a high-concentration diffusion region inside a channel region below a source region with high precision by a self-alignment process. An insulated gate semiconductor device in which the lower channel region resistance can be sufficiently reduced as compared with the conventional method, the low energy demanded by the market, the manufacturing variability is small, and the threshold voltage value has less manufacturing variability. It is possible to obtain.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of an insulated gate semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of the insulated gate semiconductor device according to the embodiment of the present invention;

FIG. 3 is a sectional view showing a manufacturing process of the insulated gate semiconductor device according to the embodiment of the present invention;

FIG. 4 is a sectional view showing a manufacturing process of the insulated gate semiconductor device according to the embodiment of the present invention;

FIG. 5 is a sectional view showing a manufacturing process of the insulated gate semiconductor device according to the embodiment of the present invention;

FIG. 6 is a sectional view showing a manufacturing process of a conventional insulated gate semiconductor device.

FIG. 7 is a sectional view showing a manufacturing process of a conventional insulated gate semiconductor device.

FIG. 8 is a sectional view showing a manufacturing process of a conventional insulated gate semiconductor device.

FIG. 9 is a sectional view showing a manufacturing process of a conventional insulated gate semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate (drain region) 2 gate oxide film 3 polysilicon (gate electrode) 4 channel region 5 high-concentration ion implantation region 6 high-concentration diffusion region 7 source region 8 resist

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Tsutsuya Otsuji 1-1, Komachi, Takatsuki-shi, Osaka Matsushita Electronics Co., Ltd. F-term (reference) 4M104 BB01 BB28 CC05 DD02 DD65 DD91 GG18 GG20 HH14

Claims (6)

[Claims] 1. A step of selectively forming an oxide film and a mask material formed in a drain region of one conductivity type on a semiconductor substrate, and a step of partially forming a channel region of an opposite conductivity type by a mask material. Forming a diffusion region of the opposite conductivity type having a higher concentration than the channel region in the channel region of the opposite conductivity type by using the mask material as a mask; A step of etching isotropically until the end of the diffusion region of the opposite conductivity type is exceeded, and a step of forming the source region using the mask material as a mask after etching the mask material. Of manufacturing a semiconductor device. 2. The method according to claim 1, wherein polysilicon is used as the mask material. 3. The method according to claim 1, wherein tungsten silicide is used as the mask material. 4. A gate insulating semiconductor device formed by the manufacturing method according to claim 1, wherein the concentration of the high concentration opposite conductivity type diffusion region below the source region is 10 ¹⁷ or more. 5. A gate insulating semiconductor device formed by the manufacturing method according to claim 2, wherein the concentration of the high concentration opposite conductivity type diffusion region below the source region is 10 ¹⁷ or more. 6. A gate-insulated semiconductor device, wherein the concentration of the high-concentration opposite-conductivity-type diffusion region below the source region formed by the manufacturing method according to claim 3 is 10 ¹⁷ or more.