JP2001291784A - Non-volatile semiconductor memory and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve writing gate disturb characteristics in an FN writing/FN deletion flash memory. SOLUTION: A tunnel insulating film 4, a floating gate electrode 5, an inter- layer insulating film 6, and a control electrode 7 are successively formed on a channel area interposed between a drain area and a source area on the surface of a semiconductor substrate in a non-volatile semiconductor memory. A drain diffusion area 10 is formed with high concentration impurity so as to be faced through the tunnel insulating film 4 to the floating gate electrode 5. On the other hand, a source diffusion area 12 is formed with low concentration impurity so as to be faced through the tunnel insulating film 4 to the floating gate electrode 5. At the time of the writing operation of the memory cell, a depletion layer is spread in the source diffusion layer 12 so that any high electric field can be prevented from being generated in the tunnel insulating film 4. Thus, it is possible to reduce the leakage of electrons to the source diffusion layer 12 in a non-selective memory cell, and to improve writing gate disturb characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device, and more particularly to a FN (Fowler-Nordheid).
m) Improvement of write gate disturb characteristics of a flash memory characterized by current write / erase operations.

[0002]

2. Description of the Related Art FIG. 14 is a sectional view showing the structure of a conventional typical FN writing / erasing flash memory. In the figure, 1 is a p-type silicon substrate, 2 is an element isolation region,
3 is a p-type well, 4 is a tunnel oxide film, 5 is a floating gate electrode, 6 is an ONO film, 7 is a control gate electrode, 8 is a stacked gate, 13 is a side wall, and 15 is BPSG.
A film, 16 is a bit line, and 19 is an n + type source / drain diffusion layer.

In a write operation of the memory cell, a predetermined voltage is applied to each of the control gate electrode 7 (word line) and the drain region (bit line 16), and the floating gate electrode 5 This is performed by drawing out the electrons into the drain region.

[0004]

However, in the above-mentioned conventional configuration, in the write operation of the memory cell (the extraction of the electrons in the floating gate electrode 5 by the FN current),
Since the write voltage is applied to the control gate electrodes 7 of all the memory cells connected to the selected word line, the write operation is not performed (that is, the write voltage is not applied to the bit line). A relatively large (8 MV / cm or more) electric field is generated, thereby causing a so-called write gate disturbance in which electrons in the floating gate electrode 5 are extracted to the semiconductor substrate. Extraction of electrons by the write gate disturb is dominant in the high-concentration source / drain diffusion layer 19 facing the floating gate electrode 5 via the tunnel oxide film 4, and particularly, ion implantation during the formation of the source / drain diffusion layer 19. Is promoted by defects in the tunnel oxide film 4 caused by the above.

[0005] In view of the above problems, the present invention has as its object:
It is an object of the present invention to provide a nonvolatile semiconductor memory device with improved write gate disturb characteristics in a FN write / FN erase flash memory and a method of manufacturing the same.

Further, according to the present invention, in a FN write / FN erase flash memory, in addition to the improvement of the write gate disturb characteristic, the defect near the drain and the source of the tunnel oxide film is reduced, thereby improving the reliability of the memory transistor. It is also an object of the present invention to provide a nonvolatile semiconductor memory device realizing the above and a method for manufacturing the same.

[0007]

In order to solve the above-mentioned problems, according to the present invention, in a write operation of a memory cell,
Ensuring the flow of electrons from the floating gate electrode to the drain region and improving the write disturb characteristics by suppressing the flow of electrons from the floating gate electrode to the source region in unselected memory cells while performing good writing. I do.

Further, according to the present invention, in improving the write disturb characteristic, the generation of defects in the tunnel oxide film is suppressed or even if the defects occur, the defects are eliminated, thereby improving the reliability of the memory transistor.

That is, a nonvolatile semiconductor memory device according to the present invention comprises a semiconductor substrate of a first conductivity type, a drain region and a source region of a second conductivity type formed on a surface of the semiconductor substrate, and a surface of the semiconductor substrate. A channel region sandwiched between the drain region and the source region; a tunnel insulating film formed on the channel region; a floating gate electrode facing the channel region via the tunnel insulating film; An interlayer insulating film covering a part of the gate electrode; and a control gate electrode facing the floating gate electrode with the interlayer insulating film interposed therebetween, wherein the drain region has a high concentration of a second conductive type impurity. A diffusion layer is opposed to the floating gate electrode via the tunnel insulating film, and the source region has a lower concentration of the second conductive layer than the drain diffusion layer. A source diffusion layer of a type impurity is opposed to the floating gate electrode via the tunnel insulating film, and applies a predetermined voltage to each of the control gate electrode and the drain region to form a source diffusion layer in the floating gate electrode. Information is stored by extracting electrons to the drain region.

According to a second aspect of the present invention, in the nonvolatile semiconductor memory device according to the first aspect, the concentration of the second conductivity type impurity is 5.0E19 / cm ^{3 in the} drain diffusion layer.
As described above, in the source diffusion layer, the concentration of the second conductivity type impurity is 1.0E19 / cm ³ or less.

Further, according to a third aspect of the present invention, in the nonvolatile semiconductor memory device, a semiconductor substrate of a first conductivity type; a drain region and a source region of a second conductivity type formed on a surface of the semiconductor substrate; A channel region sandwiched between the drain region and the source region on the surface of the semiconductor substrate; a tunnel insulating film formed on the channel region; and a floating gate electrode opposed to the channel region via the tunnel insulating film An interlayer insulating film that covers a part of the floating gate electrode; and a control gate electrode that faces the floating gate electrode with the interlayer insulating film interposed therebetween. A drain diffusion layer of a p-type impurity is opposed to the floating gate electrode via the tunnel insulating film, and the source region is a source opposed to the floating gate electrode. The tunnel insulating film has a film thickness at a portion located above the source diffusion layer is thicker than a film thickness at a portion located above the channel region; Information is stored by applying a predetermined voltage to the electrode and the drain region, and extracting electrons in the floating gate electrode to the drain region.

In addition, a method of manufacturing a non-volatile semiconductor memory device according to a fourth aspect of the present invention includes a step of forming an element isolation region and a memory transistor region comprising a first conductivity type semiconductor layer on a semiconductor substrate. Forming a stacked gate in which a tunnel insulating film, a floating gate electrode electrically insulated for each of the memory transistors, an interlayer insulating film, and a control gate electrode are stacked so as to cover a portion to be a channel region of the memory transistor; Performing at least one step in a portion to be a drain region of the memory transistor.
Performing a first ion implantation including a second type of impurity ions of a second conductivity type to form a high-concentration drain diffusion layer so as to face a part of the floating gate electrode via the tunnel insulating film; Forming a source diffusion layer having a concentration lower than that of the drain diffusion layer by performing a second ion implantation including at least one kind of second conductivity type impurity ions in a portion to be a source region of the memory transistor; And characterized in that:

According to a fifth aspect of the present invention, in the method for manufacturing a nonvolatile semiconductor memory device according to the fourth aspect, the first ion implantation is performed using an arsenic (As +) having an implantation amount of 1.0E15 / cm ² or more. It is characterized by two injections of an injection and an injection of phosphorus (P +) at an injection amount of 1.0E15 / cm ² or more.

Further, according to a sixth aspect of the present invention, in the method for manufacturing a nonvolatile semiconductor memory device according to the fourth aspect, the second ion implantation is performed by using a phosphorous having an implantation amount of 1.0E15 / cm ² or less.
(P +) injection.

In addition, a method of manufacturing a non-volatile semiconductor memory device according to the present invention includes a step of forming an element isolation region and a memory transistor region comprising a first conductivity type semiconductor layer on a semiconductor substrate. A stack having a structure in which a tunnel insulating film, a floating gate electrode electrically insulated for each memory transistor, an interlayer insulating film, and a control gate electrode are stacked so as to cover a portion to be a channel region of the memory transistor. Forming a type gate, and performing a first ion implantation including at least one type of second conductivity type impurity ion in a portion to be a drain region of the memory transistor, and forming the floating gate electrode through the tunnel insulating film. Forming a high-concentration drain diffusion layer so as to face a part of the memory transistor; and forming a source region of the memory transistor. The site, at least one second
Forming a source diffusion layer by performing second ion implantation including conductive impurity ions; and increasing a thickness of the tunnel insulating film in a region where the floating gate electrode and the source diffusion layer face each other. It is characterized by.

According to an eighth aspect of the present invention, in the method of manufacturing a nonvolatile semiconductor memory device according to the seventh aspect, the tunnel insulating film is thickened in a region where the floating gate electrode and the source diffusion layer face each other. Process is 80
It is characterized by thermal oxidation at 0 ° C. or higher.

As described above, according to the first and fourth aspects of the present invention, the high concentration impurity drain diffusion layer is opposed to the floating gate electrode via the tunnel insulating film, while the low concentration impurity source diffusion layer is tunneling. It faces the floating gate electrode via the insulating film. Therefore, at the time of the write operation of the memory cell, an electric field necessary to extract electrons in the floating gate electrode to the drain region is secured by the FN tunnel current, while a depletion layer spreads in the source region of the low concentration impurity in the source region. As a result, a high electric field is not generated in the tunnel insulating film, so that in a non-selected memory cell, the leakage of electrons from the floating gate electrode to the source region is effectively suppressed, and the write gate disturb characteristic is effectively improved.

According to the second aspect of the present invention, the high impurity concentration of the drain diffusion layer is 5.0E19 / cm ³ or more and the low impurity concentration of the source diffusion layer is 1.0E19 / cm ³ or less. , A high-concentration drain diffusion layer necessary for the writing operation (extraction of electrons in the floating gate electrode 5 by the FN current) is obtained, and the low-diffusion level is low enough to suppress the leakage of the electrons to the source region in the non-selected memory cells. A source diffusion layer having a high concentration is obtained.

Further, according to the third and seventh aspects of the present invention, the high concentration impurity drain diffusion layer faces the floating gate electrode via the tunnel insulating film, while the source region is
The tunnel insulating film is opposed to the floating gate electrode through a thick portion. Therefore, at the time of the write operation of the memory cell, an electric field necessary for extracting electrons in the floating gate electrode to the drain region by the FN tunnel current is satisfactorily secured. Further, since the source region and the floating gate electrode are opposed to each other by the relatively thick tunnel insulating film, a high electric field such that an FN tunnel current flows in the source region does not occur in the write operation of the memory cell. Therefore, in the unselected memory cells, the leakage of electrons to the source region is effectively suppressed, and the write gate disturb characteristic is improved. In addition, since sufficient insulation between the source region and the floating gate electrode is ensured, the reliability of the memory cell is improved in terms of read gate disturbance and retention.

In addition, according to the fifth aspect of the present invention, when forming the high concentration drain diffusion layer by the first ion implantation including the second conductivity type impurity ions, the first ion implantation is performed at an implantation amount of 1.0E15 / implantation of arsenic (As +) over cm ²
Since the injection is performed twice with the implantation of phosphorus (P +) at an implantation amount of 1.0E15 / cm ² or more, a drain diffusion layer having a sufficiently high concentration and a high withstand voltage for a memory cell write operation can be obtained.

Further, in the invention according to claim 6, when the low concentration source diffusion layer is formed by the second ion implantation including the second conductivity type impurity ions, the second ion implantation is performed at an implantation amount of 1.0E15 / cm 2. Since the structure is formed by implantation of phosphorus (P +) of ² or less, the implantation defect in the tunnel oxide film generated near the source can be effectively reduced by reducing the implantation amount.

Further, in the invention according to claim 8, the step of thickening the tunnel insulating film in the region where the floating gate electrode and the source diffusion layer face each other is performed by thermal oxidation at 800 ° C. or more. Defects in the tunnel oxide film generated by ion implantation or the like are effectively eliminated by the thermal oxidation at 800 ° C. or higher. Therefore, the reliability of the memory cell is improved in terms of read gate disturb and retention.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional structural view of the nonvolatile semiconductor memory device according to the present embodiment, and FIGS. 2 to 6 are sectional views showing steps in a method for manufacturing the nonvolatile semiconductor memory device according to the present embodiment. 1 to 6, reference numeral 1 denotes a p-type silicon substrate (a semiconductor substrate of the first conductivity type), 2 denotes an element isolation region, 3 denotes a p-type well, and 10 denotes an n + -type (second conductivity type) drain diffusion layer. And is formed as a drain region on the surface of the silicon substrate 1. Reference numeral 12 denotes an n − type (second conductivity type) source diffusion layer, which is formed as a source region on the surface of the silicon substrate 1.

Reference numeral 4 denotes a tunnel oxide film (tunnel insulating film) which is formed in a channel region sandwiched between the n + type drain diffusion layer 10 and the n − type source diffusion layer 12. 5 is a floating gate electrode formed on the tunnel oxide film 4, 6 is an ONO film formed on the floating gate electrode 5, 7 is a control gate electrode formed on the ONO film 6, 8 Is a stack type gate, which comprises the tunnel oxide film 4, the floating gate electrode 5, the ONO film 6, and the control gate electrode 7. 9 and 11 are resists,
13 is a side wall, 14 is an n + type source / drain diffusion layer, 15 is a BPSG film, and 16 is a bit line.

Next, the nonvolatile semiconductor memory device of the present embodiment will be described with reference to FIG.

The nonvolatile semiconductor memory device shown in FIG.
It has an asymmetric structure having a drain diffusion layer 10 and an n − source diffusion layer 12.

The write operation is performed by applying the -8 V, n + -type drain diffusion layer 1 to the control gate electrode 7 (word line) of the selected memory cell.
When + 6V is applied to 0 (bit line), 1
This is performed by generating a high electric field of 2 MV / cm or more and extracting electrons in the floating gate electrode 5 to the n + -type drain diffusion layer 10.

In the case of non-selected memory cells connected to the same word line, the control gate electrode 7 is set to -8V, and the n + type drain diffusion layer 10 and the n- type source diffusion layer 12 are set to 0V. In the overlap region between the n + type drain diffusion layer 10 and the floating gate electrode 5, an electric field of about 8 MV / cm is generated in the tunnel oxide film 4 and an FN tunnel current flows.
In the overlap region between the − type source diffusion layer 12 and the floating gate electrode 5, the surface of the n − type source diffusion layer 12 is depleted, so that no electric field is generated in the tunnel oxide film 4 such that an FN tunnel current flows. Therefore, the speed of extracting electrons from the floating gate electrode 5 in the unselected memory cell is reduced by half, so that the write gate disturb can be improved.

Next, a method of manufacturing the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 2, an element isolation region 2 is formed on a p-type silicon substrate 1 by a LOCOS method (local oxidation method).
Then, boron ions (B +, B ++) are implanted to form a p-type well 3.

Next, on the top surface of the p-type well 3, a tunnel oxide film 4 (thickness 9n) is formed by thermal oxidation in a steam atmosphere at 900 ° C.
m), a floating gate electrode 5 (200 nm thick) made of an n-type polycrystalline silicon film, an ONO film 6 (15 nm thick in terms of a silicon oxide film), and a control gate electrode 7 made of an n-type polycrystalline silicon film. The stack type gate 8 having a laminated structure (thickness: 300 nm) is patterned as shown in FIG. 3 by using a photolithography process and dry etching. At this time, the floating gate electrode 5 is divided in advance so as to be electrically insulated between adjacent memory cells, the ONO film 6 is formed so as to cover the floating gate electrode 5, and the control gate electrode 7 is It is arranged as a word line that connects memory cells arranged in the direction in series, and is capacitively coupled to each floating gate electrode 5 arranged in the gate direction via the ONO film 6 (not shown).

Subsequently, as shown in FIG. 4, the resist 9 is used as a mask, the implantation amount is 2E15 / cm ² , and the implantation energy is 50 keV.
Arsenic ions (As +) and phosphorus ions (P +) with an implantation amount of 5E15 / cm ² and an implantation energy of 50 keV (first ion implantation) are sequentially performed, and the implantation is performed twice to thereby obtain the tunnel oxide film 4. The second gate is opposed to the floating gate electrode 5 via
An n + type drain diffusion layer 10 having a conductivity type impurity concentration of 5.0E19 / cm ³ or more is formed. At this time, arsenic ions and phosphorus ions of 1E15 / cm ² or more are implanted at a predetermined implantation energy, so that a high concentration necessary for a memory cell write operation (extraction of electrons in the floating gate electrode 5 by FN current) is obtained. In addition, the n + -type drain diffusion layer 10 having a high breakdown voltage can be obtained, and a sufficient gate-drain overlap can be secured.

Further, as shown in FIG. 5, using the resist 11 as a mask, the implantation amount is 5E14 / cm ² and the implantation energy is 20 keV.
Of phosphorus ions (P +) (second ion implantation)
An n-type source diffusion layer 12 having an n-type impurity concentration lower than that of the + -type drain diffusion layer 10 and an impurity concentration of 1.0E19 / cm ³ or less is formed. At this time, since the implantation amount of phosphorus ions in the source region is relatively small (1E15 / cm ² or less), the number of implantation defects generated in the tunnel oxide film 4 is extremely small, and does not substantially affect the reliability of the memory cell. .

Subsequently, after the formation of the sidewalls 13, an n + type source / drain diffusion layer 14 is formed by arsenic ion (As +) implantation to reduce parasitic resistance, and a BPSG film 15 is deposited by normal pressure CVD. Then, as shown in FIG. 6, electrical connection between elements is made by wiring such as the bit line 16.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described.
An embodiment will be described with reference to the drawings.

FIG. 7 is a sectional structural view of the nonvolatile semiconductor memory device according to the present embodiment, and FIGS. 8 to 10 are sectional views showing steps of a method for manufacturing the nonvolatile semiconductor memory device according to the present embodiment.

7 to 13, 1 is a p-type silicon substrate, 2 is an element isolation region, 3 is a p-type well, 4 is a tunnel oxide film, 5 is a floating gate electrode, 6 is an ONO film, 7 is a control gate. Electrode, 8 is a stacked gate, 9 is resist,
10 is an n + -type drain diffusion layer, 11 is a resist, 12 is an n-type source diffusion layer, 13 is a side wall, and 14 is n +
Reference numeral 15 denotes a BPSG film, 16 denotes a bit line, and 17 denotes a gate bird's beak.

Next, a nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIG.

The nonvolatile semiconductor memory device shown in FIG.
It has an asymmetric structure having a drain diffusion layer 10 and an n-type source diffusion layer 12. Also, Gate Birds Beak 1
7, the end of the tunnel oxide film 4 is made thicker. In the overlap region between the n + -type drain diffusion layer 10 and the floating gate electrode 5, the n + -type drain diffusion layer 10 extends beyond the gate bird's beak 17 and overlaps with the tunnel oxide film 4. The overlap region between the diffusion layer 12 and the floating gate electrode 5 is limited to the region where the gate bird's beak 17 extends.

In an unselected memory cell connected to the same word line as the write memory cell, an electric field of about 8 MV / cm is applied to the tunnel oxide film 4 in the overlap region between the n + type drain diffusion layer 10 and the floating gate electrode 5. Occurs,
Although the FN tunnel current flows, an electric field that causes the FN tunnel current to flow does not occur because the overlap region between the n-type source diffusion layer 12 and the floating gate electrode 5 is thickened by the gate bird's beak 17. Therefore, the speed of extracting electrons from the floating gate electrode 5 in the unselected memory cell is reduced by half, so that the write gate disturb can be improved.

Next, a method of manufacturing the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 8, an element isolation region 2 is formed on a p-type silicon substrate 1 by a LOCOS method (local oxidation method).
After forming a memory transistor region sandwiched between the two element isolation regions 2 by the element isolation region 2, boron ions (B +, B ++) are implanted to form a p-type well 3.

Next, a tunnel oxide film 4 (9 nm thick) is formed on the upper surface of the p-type well 3 by thermal oxidation in a steam atmosphere at 900 ° C.
m), a floating gate electrode 5 (200 nm thick) made of an n-type polycrystalline silicon film, an ONO film 6 (15 nm thick in terms of a silicon oxide film), and a control gate electrode 7 made of an n-type polycrystalline silicon film. The stack type gate 8 having a laminated structure (thickness: 300 nm) is patterned as shown in FIG. 9 by using a photolithography process and dry etching. At this time, the floating gate electrode 5 is divided in advance so as to be electrically insulated between adjacent memory cells, the ONO film 6 is formed so as to cover the floating gate electrode 5, and the control gate electrode 7 is It is arranged as a word line that connects memory cells arranged in the direction in series, and is capacitively coupled to each floating gate electrode 5 arranged in the gate direction via the ONO film 6 (not shown).

Subsequently, as shown in FIG.
Using as a mask, the injection amount 2E15 / cm^Two, Injection energy 50
Arsenic ion (As +) with keV and implantation dose 5E15 / cm^Two, Injection energy
50 keV phosphorus ions (P +)
N + so as to face floating gate electrode 5 with oxide film 4 interposed therebetween.
The drain diffusion layer 10 is formed. At this time, 1E15 / cm ^Two
The above arsenic ions and phosphorus ions are implanted at a predetermined implantation energy.
The write operation of the memory cell
(Extraction of electrons in floating gate electrode 5 by FN current
N + type drain diffusion layer with high concentration and high breakdown voltage required for
And sufficient gate-drain overlap
Can be secured.

Further, as shown in FIG.
Is used as a mask, the implantation amount is 1E15 / cm ² , and the implantation energy is 20.
The n-type source diffusion layer 12 is formed by applying phosphorus ions (P +) of keV. At this time, the implantation amount of the source region is 1E14 / cm ² ~
Although about 1E15 / cm ² is appropriate, the larger the injection amount, the lower the parasitic resistance of the source diffusion layer.

Subsequently, a temperature of 800 ° C. or more, for example, 900 ° C., 20 ° C.
Thermal oxidation (particularly dry oxidation)
As shown in FIG. 12, a gate bird's beak 17 is formed at the end of the tunnel oxide film 4 to make the end of the tunnel oxide film 4 thicker. At this time, the overlap region between the n + -type drain diffusion layer 10 and the floating gate electrode 5 extends beyond the gate bird's beak 17 to ensure capacitive coupling with the tunnel oxide film 4. Further, since the n-type source diffusion layer 12 is formed shallowly, an overlap region with the floating gate electrode 5 is occupied by the gate bird's beak 17. Furthermore,
Dry oxidation at 900 ° C. for 20 minutes eliminates defects in the tunnel oxide film 4 generated by ion implantation or the like, and thus has the effect of improving the reliability of the memory cell. afterwards,
The side wall 13 is formed.

Then, as shown in FIG. 13, an n + type source / drain diffusion layer 14 is formed by arsenic ion (As +) implantation to reduce parasitic resistance.
An SG film 15 is deposited, and electrical connection between elements is performed by wiring such as a bit line 16.

[0049]

As described above, according to the first, second, fourth and fifth aspects of the present invention, the drain diffusion layer is formed with high concentration impurities, and the source diffusion layer is formed with low concentration. Since it is formed with impurities, during the write operation of the memory cell, it is necessary to ensure that the electric field necessary to extract the electrons in the floating gate electrode to the drain region is good and that a high electric field is not generated in the tunnel insulating film in the source region. Therefore, it is possible to effectively suppress the leakage of electrons from the floating gate electrode to the source region in the unselected memory cells, and to effectively improve the write gate disturb characteristic.

According to the third and seventh aspects of the present invention, the drain diffusion layer is formed of high-concentration impurities, and the source region is connected to the floating gate electrode via a portion where the thickness of the tunnel insulating film is large. Since they are opposed to each other, at the time of a write operation of the memory cell, a high electric field such as an FN tunnel current flows in the source region is not generated in the source region, while ensuring an electric field necessary for extracting electrons in the floating gate electrode to the drain region. In this manner, the leakage of electrons to the source region in the unselected memory cells can be effectively suppressed, and the write gate disturb characteristics can be improved. Further, since the tunnel insulating film is sufficiently insulated between the source region and the floating gate electrode with a large thickness of the tunnel insulating film, the reliability of the memory cell can be improved in terms of read gate disturbance and retention.

Further, according to the invention of claim 6, when forming a low concentration source diffusion layer, since the amount of ion implantation is small, defects due to implantation in the tunnel oxide film generated near the source are effectively reduced. it can.

In addition, according to the present invention, the step of thickening the tunnel insulating film in the region where the floating gate electrode and the source diffusion layer face each other is performed by thermal oxidation at 800 ° C. or more. In addition, defects in the tunnel oxide film generated by ion implantation of the drain and the like can be effectively eliminated by the thermal oxidation at 800 ° C. or higher. Therefore, the reliability of the memory cell can be improved in terms of read gate disturb and retention.

[Brief description of the drawings]

FIG. 1 is a sectional structural view of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing steps of a method for manufacturing the same nonvolatile semiconductor memory device.

FIG. 3 is a diagram showing steps of a method for manufacturing the same nonvolatile semiconductor memory device.

FIG. 4 is a diagram showing a step of a method for manufacturing the same nonvolatile semiconductor memory device.

FIG. 5 is a view showing a step of a method for manufacturing the nonvolatile semiconductor memory device.

FIG. 6 is a diagram showing a step of a method for manufacturing the nonvolatile semiconductor memory device.

FIG. 7 is a sectional structural view of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 8 is a diagram showing a step of a method for manufacturing the nonvolatile semiconductor memory device.

FIG. 9 is a view showing a step of a method of manufacturing the nonvolatile semiconductor memory device.

FIG. 10 is a view showing a step of a method of manufacturing the nonvolatile semiconductor memory device.

FIG. 11 is a view showing a step of a method for manufacturing the nonvolatile semiconductor memory device.

FIG. 12 is a view showing a step of a method for manufacturing the nonvolatile semiconductor memory device.

FIG. 13 is a view showing a step of a method of manufacturing the nonvolatile semiconductor memory device.

FIG. 14 is a sectional structural view of a conventional FN write / FN erase flash memory.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 p-type silicon substrate 2 element isolation region 3 p-type well 4 tunnel oxide film (tunnel insulating film) 5 floating gate electrode 6 ONO film 7 control gate electrode 8 stacked gate 9 resist 10 n + -type drain diffusion layer 11 resist 12 n -Type source diffusion layer 13 sidewall 14 n + type source / drain diffusion layer 15 BPSG film 16 bit line 17 gate bird's beak 19 n + type source / drain diffusion layer

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F001 AA21 AA43 AB08 AD15 AD16 AD17 AD61 AE02 AG02 AG12 5F083 EP03 EP23 EP48 EP55 EP62 EP63 EP67 EP68 ER22 GA12 JA04 PR12 PR36 5F101 BA03 BB05 BD05 BD06 BD07 BD36 BE05 BH03 BH09

Claims (8)

[Claims] 1. A semiconductor substrate of a first conductivity type, a drain region and a source region of a second conductivity type formed on a surface of the semiconductor substrate, and the drain region and the source region on a surface of the semiconductor substrate. A sandwiched channel region, a tunnel insulating film formed on the channel region, a floating gate electrode facing the channel region via the tunnel insulating film, and an interlayer insulating film covering a part of the floating gate electrode. And a control gate electrode opposed to the floating gate electrode with the interlayer insulating film interposed therebetween, wherein the drain region has a high-concentration second-conductivity-type impurity drain diffusion layer with the tunnel insulating film interposed therebetween. The source region includes a source diffusion layer of a second conductivity type impurity having a lower concentration than that of the drain diffusion layer. Information is stored by applying a predetermined voltage to each of the control gate electrode and the drain region to extract electrons in the floating gate electrode to the drain region. A non-volatile semiconductor memory device. 2. In the drain diffusion layer, the concentration of the second conductivity type impurity is 5.0E19 / cm ³ or more, and in the source diffusion layer, the concentration of the second conductivity type impurity is 1.0E19 / cm ^3.
2. The non-volatile semiconductor memory device according to claim 1, wherein the density is 19 / cm ³ or less. 3. A semiconductor substrate of a first conductivity type, a drain region and a source region of a second conductivity type formed on a surface of the semiconductor substrate, and the drain region and the source region on a surface of the semiconductor substrate. A sandwiched channel region, a tunnel insulating film formed on the channel region, a floating gate electrode facing the channel region via the tunnel insulating film, and an interlayer insulating film covering a part of the floating gate electrode. And a control gate electrode opposed to the floating gate electrode with the interlayer insulating film interposed therebetween, wherein the drain region has a high-concentration second-conductivity-type impurity drain diffusion layer with the tunnel insulating film interposed therebetween. The source region includes a source diffusion layer facing the floating gate electrode; and the tunnel insulating film includes the source diffusion layer. A film thickness at a portion located above the diffusion layer is thicker than a film thickness at a portion located above the channel region, and a predetermined voltage is applied to the control gate electrode and the drain region. And storing information by extracting electrons in the floating gate electrode to the drain region. 4. An element isolation region on a semiconductor substrate;
Forming a memory transistor region made of a conductive semiconductor layer; and a tunnel insulating film, a floating gate electrode electrically insulated for each memory transistor, and an interlayer, so as to cover a portion to be a channel region of the memory transistor. Forming a stacked gate in which an insulating film and a control gate electrode are stacked; and
First containing at least one kind of second conductivity type impurity ions
Performing ion implantation to form a high-concentration drain diffusion layer so as to face a part of the floating gate electrode via the tunnel insulating film; and forming at least one part in a portion serving as a source region of the memory transistor. Forming a source diffusion layer having a concentration lower than that of the drain diffusion layer by performing a second ion implantation including a second type of impurity ions of the second conductivity type. Device manufacturing method. 5. The method according to claim 5, wherein the first ion implantation is performed by implanting arsenic (As +) at an implantation amount of 1.0E15 / cm ² or more,
5. The method for manufacturing a nonvolatile semiconductor memory device according to claim 4, wherein the implantation is performed twice with phosphorus (P +) implantation of E15 / cm ² or more. 6. The method according to claim 4, wherein the second ion implantation is an implantation of phosphorus (P +) at an implantation amount of 1.0E15 / cm ² or less. 7. An element isolation region on a semiconductor substrate;
Forming a memory transistor region made of a conductive semiconductor layer; and a tunnel insulating film, a floating gate electrode electrically insulated for each memory transistor, and an interlayer, so as to cover a portion to be a channel region of the memory transistor. Forming a stacked gate having a structure in which an insulating film and a control gate electrode are stacked; and
First containing at least one kind of second conductivity type impurity ions
Performing ion implantation to form a high-concentration drain diffusion layer so as to face a part of the floating gate electrode via the tunnel insulating film; and forming at least one part in a portion serving as a source region of the memory transistor. A step of forming a source diffusion layer by performing a second ion implantation including a type of second conductivity type impurity ions; and a step of thickening the tunnel insulating film in a region where the floating gate electrode and the source diffusion layer face each other. And a method for manufacturing a nonvolatile semiconductor memory device. 8. The non-volatile semiconductor device according to claim 7, wherein the step of thickening the tunnel insulating film in a region where the floating gate electrode and the source diffusion layer face each other is thermal oxidation at 800 ° C. or more. A method for manufacturing a memory device.