CN101599461B - Semiconductor memory device and manufacturing method thereof - Google Patents
Semiconductor memory device and manufacturing method thereof Download PDFInfo
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- CN101599461B CN101599461B CN2009101508015A CN200910150801A CN101599461B CN 101599461 B CN101599461 B CN 101599461B CN 2009101508015 A CN2009101508015 A CN 2009101508015A CN 200910150801 A CN200910150801 A CN 200910150801A CN 101599461 B CN101599461 B CN 101599461B
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Abstract
A semiconductor memory device includes: a semiconductor substrate; a first impurity region; a second impurity region; a channel region; a first gate formed on a main surface on a side of the first impurity region; a second gate formed on the main surface on a side of the second impurity region, with a second insulating film being interposed; and a third insulating film formed on a side surface of the first gate. An interface between the third insulating film and the semiconductor substrate directly under the third insulating film is located above an interface between the second insulating film and the main surface of the semiconductor substrate directly under the second insulating film. The total number of steps can thus be reduced, and lower cost is achieved.
Description
The application is dividing an application of following application, application number: 200610067668.3, and denomination of invention: semiconductor storage and manufacture method thereof, the applying date: on March 23rd, 2006.
Technical field
The present invention relates to semiconductor storage and manufacture method thereof.
Background technology
Usually, the known conductor integrated circuit device of people (semiconductor storage) has the memory cell region that forms a plurality of memory cell transistors and forms the transistorized peripheral circuit regions of a plurality of peripheral circuits (opening the 2004-228571 communique with reference to the spy).For example, open the spy and put down in writing the conductor integrated circuit device that on Semiconductor substrate, has memory cell transistor and its access circuit in the 2003-309193 communique.
This conductor integrated circuit device has memory cell region and outer peripheral areas on the first type surface of Semiconductor substrate, formed a plurality of memory cell transistors on memory cell region.In addition, form peripheral circuit transistors such as supply voltage system's MOS transistor and high withstand voltage nmos pass transistor in outer peripheral areas.When making the conductor integrated circuit device that constitutes like this, form after the memory cell transistor, form the peripheral circuit transistor.Like this, in the manufacture method of the semiconductor periphery circuit devices of prior art, forming memory cell transistor and the transistorized step of peripheral circuit is diverse two steps.
But, open in the manufacture method of the conductor integrated circuit device of putting down in writing in the 2003-309193 communique the spy, because forming the step of memory cell transistor and forming the transistorized step of peripheral circuit is diverse two steps, so there is the problem that total number of steps is long, cost is high.
Summary of the invention
The present invention carries out in view of above-mentioned problem, and its purpose is to reduce total number of steps of conductor integrated circuit device (semiconductor storage), and reduces cost.
The manufacture method of semiconductor storage of the present invention is a kind of like this manufacture method of semiconductor storage, this semiconductor storage has: the peripheral circuit region that forms the peripheral circuit of the memory cell region of memory cell transistor and the action control that memory cell transistor is carried out in formation, wherein, have following steps: on the first type surface of Semiconductor substrate, form the 1st dielectric film; On the 1st dielectric film, form the 1st conducting film; The 1st conducting film is carried out composition, form conductive pattern, this conductive pattern is to form the zone in memory cell transistor source region by the figure of opening; The 1st conductive pattern as mask, is formed the source region of memory cell transistor; Form the 2nd dielectric film in the mode that covers conductive pattern; On the 2nd dielectric film, form the 2nd conducting film; The 2nd dielectric film, the 2nd conducting film are carried out etching, form the storage grid of memory cell transistor; Conductive pattern is carried out composition, form the grid and the transistorized grid that is formed on peripheral circuit region of memory cell transistor; Form the drain region of memory cell transistor and transistorized source region and the drain region that is formed on peripheral circuit region.
Semiconductor storage of the present invention has: Semiconductor substrate; The area of isolation that on the upper surface of Semiconductor substrate, optionally forms; By area of isolation regulation, via the 1st, the 2nd adjacent zone of this area of isolation; Be formed on the 1st extrinsic region on the 1st zone; Be formed on the 2nd extrinsic region on the 1st zone; Be formed on the 3rd extrinsic region on the 2nd zone; Be formed on the 4th extrinsic region on the 2nd zone; Be formed on the 1st channel region between the 1st extrinsic region and the 2nd extrinsic region; Be formed on the 2nd channel region between the 3rd extrinsic region and the 4th extrinsic region; On the first type surface in the first type surface of the Semiconductor substrate at the 1st channel region place, that be positioned at the 1st extrinsic region side via formed the 1st grid of the 1st dielectric film; The 2nd grid that forms via the 2nd dielectric film that can accumulate electric charge on the first type surface in the first type surface of the Semiconductor substrate at the 1st channel region place, that be positioned at the 2nd extrinsic region side; The 3rd grid that forms via the 3rd dielectric film on the first type surface in the first type surface of the Semiconductor substrate at the 2nd channel region place, that be positioned at the 3rd extrinsic region side; The 4th grid that forms via the 4th dielectric film that can accumulate electric charge on the first type surface in the first type surface of the Semiconductor substrate at the 2nd channel region place, that be positioned at the 4th extrinsic region side; Be formed on the area of isolation between the 1st zone and the 2nd zone, be connected to form at the 2nd grid on the 1st zone and be formed on the 1st connecting portion of the 3rd grid on the 2nd zone; Be formed on the 2nd connecting portion between the 1st connecting portion, the 2nd conducting film that the 2nd connecting portion comprises the 1st conducting film and forms around the 1st conducting film by the 5th dielectric film.
On the other hand, semiconductor storage of the present invention has: Semiconductor substrate; The area of isolation that on Semiconductor substrate, optionally forms; The active region of on the first type surface of Semiconductor substrate, stipulating by area of isolation; The 1st extrinsic region that on the active region, forms; The 2nd extrinsic region that on the active region, forms; At the channel region that on the first type surface of the Semiconductor substrate between the 1st extrinsic region and the 2nd extrinsic region, forms; The 1st grid of the ring-type that forms via the 1st dielectric film on the upper surface in the upper surface of channel region, the 1st extrinsic region side; The recess that on the side of the 1st grid that is positioned at the 2nd extrinsic region, forms; The 2nd grid by the ring-type on the 2nd dielectric film that can the accumulate electric charge side that form, that be formed on the 1st grid on the upper surface in the upper surface of channel region, the 2nd extrinsic region; Be connected with the 2nd grid, be formed on the connecting portion in the recess; The voltage application portion that is connected with connecting portion, can apply voltage to the 2nd grid.
On the other hand, the manufacture method of semiconductor device of the present invention comprises the steps: optionally to form area of isolation on the first type surface of Semiconductor substrate, and the regulation active region; On the active region, form the 1st dielectric film; On the 1st dielectric film, form the 1st conducting film; The 1st conducting film is implemented composition, form conductive film figure, this conductive film figure has peristome on the zone that forms the 1st extrinsic region that can play the source region effect, have recess in the side of the 1st extrinsic region side; Conductive film figure as mask, is introduced impurity on the first type surface of Semiconductor substrate, form the 1st extrinsic region; Cover conductive film figure, formation can be accumulated the 2nd dielectric film of electric charge; On the 2nd dielectric film, form the 2nd conducting film; The 2nd conducting film and the 2nd dielectric film are implemented etching, on the side of the peristome of conductive film figure, form the 2nd grid via the 2nd dielectric film; Etching is carried out in zone in the conductive film figure, that can play the 2nd extrinsic region place of drain region effect, on the first type surface that surrounds the 1st extrinsic region Semiconductor substrate on every side, form the 1st grid; On the first type surface of Semiconductor substrate, introduce impurity, thereby form the 2nd extrinsic region.
According to semiconductor storage of the present invention (conductor integrated circuit device) and manufacture method thereof, can reduce total number of steps, and can reduce cost.
Above-mentioned and other purpose, feature, aspect and advantage of the present invention will be by will be clearer and more definite by the detailed description of understanding in conjunction with the accompanying drawings of the present invention.
Description of drawings
Fig. 1 is the plane graph of the conductor integrated circuit device (Nonvolatile semiconductor memory device) of schematically illustrated execution mode 1.
Fig. 2 is the profile of the memory cell region in ROM zone.
Fig. 3 is the profile of peripheral circuit region.
The profile of the memory cell region when Fig. 4 is write activity.
Fig. 5 is the profile of the memory cell region of erasing move.
The profile of the memory cell region of the 1st step of Fig. 6 conductor integrated circuit device.
Fig. 7 is the profile of peripheral circuit region of the 1st step of conductor integrated circuit device.
Fig. 8 is the profile of memory cell region of the 2nd step of conductor integrated circuit device.
Fig. 9 is the profile of peripheral circuit region of the 2nd step of conductor integrated circuit device.
Figure 10 is the profile of memory cell region of the 3rd step (pattern step of the 1st conducting film) of conductor integrated circuit device.
Figure 11 is the profile of peripheral circuit region of the 3rd step of conductor integrated circuit device.
Figure 12 is the profile of memory cell region of the 4th step (the formation step in the storage grid lower channel zone of memory cell transistor) of conductor integrated circuit device.
Figure 13 is the profile of peripheral circuit region of the 4th step of conductor integrated circuit device.
Figure 14 is the profile of memory cell region of the 5th step (the formation step of the 2nd dielectric film) of conductor integrated circuit device.
Figure 15 is the profile of peripheral circuit region of the 5th step of conductor integrated circuit device.
Figure 16 is the profile of memory cell region of the 6th step (the formation step in storage grid, source region) of conductor integrated circuit device.
Figure 17 is the profile of peripheral circuit region of the 6th step of conductor integrated circuit device.
Figure 18 is the profile of memory cell region of the 7th step (control grid and grid form step) of conductor integrated circuit device.
Figure 19 is the profile of peripheral circuit region of the 7th step of conductor integrated circuit device.
Figure 20 is the profile of memory cell region of the 8th step (the formation step of the drain region of memory cell transistor and the transistorized extrinsic region of peripheral circuit) of conductor integrated circuit device.
Figure 21 is the profile of peripheral circuit region of the 8th step of conductor integrated circuit device.
Figure 22 is the profile of memory cell region of the 9th step (the formation step of the transistorized extrinsic region of peripheral circuit) of conductor integrated circuit device.
Figure 23 is the profile of peripheral circuit region of the 9th step of conductor integrated circuit device.
Figure 24 is the profile of memory cell region of the 10th step (the formation step of memory cell transistor and the transistorized side wall of peripheral circuit) of conductor integrated circuit device.
Figure 25 is the profile of peripheral circuit region of the 10th step of conductor integrated circuit device.
Figure 26 is the profile of memory cell region of the 11st step (metal silicide formation step) of conductor integrated circuit device.
Figure 27 is the profile of outer peripheral areas of the 11st step of conductor integrated circuit device.
Figure 28 is the profile of memory cell region of the 12nd step (bit line formation step) of conductor integrated circuit device.
Figure 29 is the profile of peripheral circuit region of the 12nd step of conductor integrated circuit device.
Figure 30 is the profile of the details of the connecting portion shown in expression Figure 39.
Figure 31 is the profile of the details on the area of isolation among expression Figure 41.
Figure 32 is the profile of upper surface of representing the area of isolation of Figure 42 in detail.
Figure 33 is the profile of the details of area of isolation among expression Figure 44.
Figure 34 is the plane graph of peripheral circuit region of pattern step of the conducting film of conductor integrated circuit device.
Figure 35 is the plane graph that forms the peripheral circuit region of the 7th step of controlling grid and grid.
Figure 36 is the plane graph of the peripheral circuit region of photomask.
Figure 37 is the plane graph of the outer peripheral areas when forming the grid of peripheral circuit region.
Figure 38 is the profile of memory cell transistor of representing the conductor integrated circuit device of execution mode 1 in detail.
Figure 39 is the plane graph of memory cell region of the conductor integrated circuit device of execution mode 2.
Figure 40 be in the manufacturing step of conductor integrated circuit device of expression execution mode 1 with the profile of Fig. 6, manufacturing step that the 1st manufacturing step shown in Figure 7 is corresponding.
Figure 41 is the expression manufacturing step corresponding with the 3rd step of the conductor integrated circuit device of execution mode 1, the profile of Figure 10 XLI-XLI line.
Figure 42 is the profile of the expression manufacturing step corresponding with the 5th step of the conductor integrated circuit device of the execution mode 1 shown in Figure 14.
Figure 43 is the profile of the expression manufacturing step corresponding with the 5th step of the conductor integrated circuit device of the execution mode 1 shown in Figure 14.
Figure 44 is the profile of the XLIV-XLIV line of, Figure 16 corresponding with the 6th step of the conductor integrated circuit device of the execution mode 1 shown in Figure 16.
Figure 45 is the profile of the XLV-XLV line of manufacturing step, Figure 18 behind the manufacturing step of the conductor integrated circuit device of expression shown in Figure 44.
Figure 46 is the plane graph of the conductor integrated circuit device of execution mode 3.
Figure 47 is the profile of the XLVII-XLVII line of Figure 46.
Figure 48 is the profile of the XLVIII-XLVIII line of Figure 46.
Figure 49 is the plane graph of the expression step corresponding with the 1st step of the manufacturing step of the conductor integrated circuit device of the execution mode 1 shown in Fig. 6, Fig. 7.
Figure 50 is the plane graph of the expression manufacturing step corresponding with the 3rd step of the conductor integrated circuit device of the execution mode 1 shown in Figure 10, Figure 11.
Figure 51 is the plane graph of the expression manufacturing step corresponding with Figure 16, Figure 17.
Figure 52 is the plane graph of the manufacturing step behind the manufacturing step shown in expression Figure 51.
Figure 53 is the plane graph of for example ram region of the conductor integrated circuit device of execution mode 4.
Figure 54 is the equivalent electric circuit of memory cell M1.
Figure 55 is the profile of the LV-LV line of Figure 53.
Figure 56 is the plane graph of the 1st step of manufacturing step of the conductor integrated circuit device of expression execution mode 4.
Figure 57 is the profile of the LVII-LVII line of Figure 56.
Figure 58 is the plane graph of the manufacturing step of the semiconductor integrated circuit behind the manufacturing step shown in expression Figure 56.
Figure 59 is the profile of the LIX-LIX line of Figure 58.
Figure 60 is the plane graph of the manufacturing step of the conductor integrated circuit device behind the manufacturing step shown in expression Figure 58.
Figure 61 is the profile of the LXI-LXI line of Figure 60.
Figure 62 is the profile of the manufacturing step behind the manufacturing step of the conductor integrated circuit device of expression shown in Figure 61.
Figure 63 is the profile of the manufacturing step behind the manufacturing step shown in expression Figure 62.
Figure 64 is the plane graph of the manufacturing step shown in Figure 63.
Figure 65 is the plane graph of the manufacturing step behind the manufacturing step shown in expression Figure 64.
Figure 66 is the profile of the LXVI-LXVI line of Figure 65.
Figure 67 is the plane graph of peripheral circuit region of conductor integrated circuit device of the variation of execution mode 4.
Figure 68 is the profile of the LXVIII-LXVIII line of Figure 67.
Figure 69 is the plane graph of the 1st step of conductor integrated circuit device of the variation of expression execution mode 4.
Figure 70 is the profile of Figure 69.
Figure 71 is the plane graph of the manufacturing step behind the manufacturing step shown in expression Figure 69.
Figure 72 is the profile of Figure 71.
Figure 73 is the plane graph of peripheral circuit region in the pattern step of conducting film of conductor integrated circuit device.
Figure 74 is the profile of Figure 73.
Figure 75 is the profile of the manufacturing step behind the manufacturing step of the conductor integrated circuit device of expression shown in Figure 74.
Figure 76 is the plane graph that forms the peripheral circuit region of the 7th step of controlling grid and grid.
Figure 77 is the profile of Figure 76.
Figure 78 is the plane graph of the manufacturing step behind the manufacturing step shown in expression Figure 76.
Figure 79 is the profile of Figure 78.
Figure 80 is the action line chart of reading when action of the conductor integrated circuit device of execution mode 3.
Figure 81 is the action line chart of write activity.
Figure 82 is the action line chart of erasing move.
Figure 83 is the circuit diagram of the semiconductor integrated device of execution mode 3.
Figure 84 is the schematic diagram of the conductor integrated circuit device of execution mode 3.
Figure 85 is the profile of the transistorized details of expression peripheral circuit.
Embodiment
Use Fig. 1 embodiments of the present invention to be described to Figure 85.
(execution mode 1)
Fig. 1 is the plane graph of the conductor integrated circuit device (Nonvolatile semiconductor memory device) 10 that schematically shows present embodiment 1.This conductor integrated circuit device 10 for example is used as and is equipped with MONOS (Metal Oxide Nitride Oxide Silicon: the metal oxide silicon oxynitride) flash memory of structure mix to carry a microcomputer.This conductor integrated circuit device 10 has peripheral circuit region 65 and memory cell region 67 on substrate.
In addition, memory cell region 67 has ROM (Read Only Memory: zone 63 and RAM (Random Access Memory: zone 62 random access memory) read-only memory).
These each zones 61,63a, 64,63,62 are by area of isolation 25 regulations that optionally form on the first type surface of Semiconductor substrate 13.The groove of the 300nm left and right sides degree of depth constitutes with the dielectric films such as for example silicon oxide layer that are filled in this groove this area of isolation 25 by for example etching on the first type surface of Semiconductor substrate 13.Fig. 2 is the profile of the memory cell region in ROM zone 63.As shown in Figure 2, a plurality of memory cell transistors 27 on the ROM zone 63 of memory cell region 67, have been formed.
In this memory cell region 67, at the main surface side formation P of Semiconductor substrate 13 type trap 12.For example on the first type surface of this Semiconductor substrate 13, form a plurality of memory cell transistors (the 1st transistor) 27 that constitute by MONOS structure etc., be provided with bit line 48 in the upper surface side of memory cell transistor 27.Memory cell transistor 27 has: drain region (the 1st extrinsic region) 17 is formed on the Semiconductor substrate 13; Source region (the 2nd extrinsic region) 15 is formed on the first type surface of Semiconductor substrate 13; Channel region 75 is formed on the first type surface of the Semiconductor substrate 13 between source region 15 and the drain region 17; Control grid (the 1st grid) 42 is formed on via dielectric film (the 1st dielectric film) 41 on the first type surface in the first type surface of Semiconductor substrate 13 at channel region 75 places, that be positioned at drain region 17 sides; Storage grid (the 2nd grid) 45 is formed on via the dielectric film that can accumulate electric charge (the 2nd dielectric film) 44 on the first type surface in the first type surface of Semiconductor substrate 13 at channel region 75 places, that be positioned at source region 15 sides.
For example on the side of the drain region of this control grid 42 17 sides, form the dielectric film 46 of the side wall shape that constitutes by silicon oxide layer etc.Storage grid 45 forms with the side wall shape on the side of source region 15 sides of control grid 42, and for example the conducting film by polysilicon film etc. constitutes.The width of storage grid 45 bottoms of this side wall shape for example is about 45nm.On the side of the source region of this storage grid 45 15 sides, form the dielectric film 46 of the side wall shape that constitutes by silicon oxide layer etc.
When thermal diffusion, phosphorus is being parallel to the direction diffusion of Semiconductor substrate 13 first type surfaces than arsenic is easier.Therefore, the end of control grid 42 sides of low concentration impurity diffusion layer 15a is lower than the central portion concentration of low concentration impurity diffusion layer 15a.Therefore, by injecting phosphorus etc., can form the charge density zone of the impurity that is suitable for forming the hole in the end of low concentration impurity diffusion layer 15a.And, when using arsenic to form low concentration impurity diffusion layer 15a,, can be constructed as follows structure by introducing boron simultaneously, promptly the impurity diffusion layer of boron covers the impurity diffusion layer structure (Halo structure) on every side of arsenic, and can further improve electric field.
And, on the upper surface in the upper surface in the upper surface of the upper surface of memory electrode 45, control grid 42, source region 15, drain region 17, form the metal silicide film 37 that for example waits formation respectively by cobalt silicide (CoSi) or nickle silicide (NiSi).Herein, 17 sides form smooth planarly the upper surface of control grid 42 to the drain region across source region 15 sides, and also 17 sides form smooth planar to the drain region across source region 15 sides to be formed on metal silicide film 37 on these control grid 42 upper surfaces.Therefore, the thickness of metal silicide film 37 does not have deviation, can realize controlling the uniformity of the resistance of grid 42, and the resistance of control grid 42 can be set at desirable value.
The charge density (impurity concentration) in storage grid lower channel zone 14 is littler than the charge density in control grid lower channel zone 16.For example, the charge density in storage grid lower channel zone 14 is preferably 10
17～10
18/ cm
3, more preferably 3 * 10
17～7 * 10
17/ cm
3, for example 5 * 10
17/ cm
3About.The charge density (impurity concentration) of the impurity in control grid lower channel zone 16 for example is 10
18/ cm
3
For example successively the thickness perpendicular to the vertical direction of Semiconductor substrate 13 first type surfaces is formed silicon oxide layer about 5nm, carries out lamination at the silicon nitride film about the 10nm that forms on this silicon oxide layer, silicon oxide layer about the 5nm that forms on this silicon nitride film and form this dielectric film 44.And the thickness perpendicular to Semiconductor substrate 13 first type surface directions of this dielectric film 44 for example is about 20nm.
On the surface of the memory cell transistor 27 that constitutes like this, form dielectric film 52, on this dielectric film 52, form interlayer dielectric 38.And, on the upper surface of this interlayer dielectric 38, form bit line 48.
And, on the metal silicide film 37 that is formed on 17 upper surfaces of drain region, form contact site 49.This contact site 49 is by constituting as the lower part: contact hole, and the upper surface that runs through interlayer dielectric 38 is to lower face side; Conducting film 39 is formed on the internal face of this contact hole; Conducting film 50 is formed on the face side of conducting film 39, is filled in the contact hole.And contact site 49 runs through interlayer dielectric 38 and is connected with bit line 48 on being formed on interlayer dielectric 38.
Fig. 3 is the profile of peripheral circuit region 65.As shown in Figure 3, on the first type surface of the Semiconductor substrate 13 at peripheral circuit region 65 places, form P type trap 12 and N type trap 18.In addition, the boundary member at P type trap and N type trap 18 forms area of isolation (STI (Shallow TrenchIsolation: shallow-trench isolation) isolate) 25.And, on the upper surface of P type trap 12, form peripheral circuit transistor 28a.In addition, on the upper surface of N type trap 18, form peripheral circuit transistor 28b.And, on the upper surface of peripheral circuit transistor 28a, 28b, form dielectric film 52, on the upper surface of dielectric film 52, form interlayer dielectric 38.The a plurality of upper strata wiring of configuration 48a, 48b, 48c, 48d on the upper surface of this interlayer dielectric 38.Peripheral circuit transistor 28a have the grid 43a on the Semiconductor substrate of being formed on 13 first type surfaces and be formed on this grid 43a and Semiconductor substrate 13 between gate insulating film 40.
Height perpendicular to the control grid 42 of the height of the Semiconductor substrate 13 first type surface directions of grid 43a and memory cell transistor 27 shown in Figure 2 is roughly the same.
In addition, peripheral circuit transistor 28a has source region 19a and the drain region 19b on the Semiconductor substrate of being formed on 13 first type surfaces.On the side of grid 43a, form side wall 47.
Use Fig. 4 that the write activity of the conductor integrated circuit device 10 that as above constitutes is described.The profile of the memory cell region 67 when Fig. 4 is write activity.As shown in Figure 4, on the drain region 17 of selected memory cell transistor 27a, apply for example voltage about 0.8V, on source region 15, apply for example voltage about 6V.And, on storage grid 45, apply the voltage about 11V, on control grid 42, apply the voltage about 1.5V.
Like this, apply voltage after, produce bigger electric field at the boundary vicinity of control grid 42 and memory cell grid 45, and produce a lot of hot electrons.And, trapped electron in the dielectric film 44 that can accumulate electric charge.Moreover in the dielectric film 44, electronics enters the part of silicon nitride, writes electrical information.This phenomenon is that the source of knowing injects (Source side injection:SSI).
In addition, use Fig. 5 that the erasing move of the conductor integrated circuit device 10 that as above constitutes is described.Fig. 5 is the profile of the memory cell region 67 of erasing move.As shown in Figure 5, for example on source region 15, apply the voltage about 6V, on drain region 17, apply the voltage about 0V.And, apply voltage about 0V on the grid 42 in control, applying on the storage grid 45-voltage about 6V.
Like this, storage grid 45 is applied negative potential, storage grid side impurity diffusion layer is applied positive potential, thus, can produce strong counter-rotating, cause the interband tunnel(l)ing, produce the hole in the end in the source region 15 of storage grid 45 sides.The hole that is produced is caused by bias voltage, by being injected into the dielectric film 44 that is arranged under the storage grid 45, carries out erasing move.
Like this, hole and the electron recombination that is injected in the dielectric film 44 thus, can make the threshold voltage of rising reduce.
In reading action, for example on the control grid 42 of selected memory cell transistor 27 and storage grid 45, apply for example voltage about 1.5V.And, on source region 15, apply for example voltage about 0V, on drain region 17, for example apply the voltage about 1.5V.Like this, will be applied between source region 15 and the drain region 17 at the voltage between the threshold voltage of threshold voltage under the write state of selected memory cell transistor 27 and the memory cell transistor under the erase status 27., under the situation that trapped electron and threshold voltage rise in the dielectric film 44 of selected memory cell transistor 27, keeping the OFF state herein, is the ON state under the situation of injected hole in dielectric film 44.
Manufacture method to the conductor integrated circuit device 10 that constitutes as mentioned above describes.
Fig. 6 is the profile of memory cell region 67 in the 1st step of manufacturing step of conductor integrated circuit device 10, and Fig. 7 is the profile of peripheral circuit region 65 in the 1st step.
As shown in Figure 7, the first type surface of Semiconductor substrate 13 is optionally for example carried out etching about 300nm, form the groove of area of isolation (element separation zone) 25 usefulness.And, implement thermal oxidation, at the heat oxide film that for example forms on the first type surface of Semiconductor substrate 13 and on the surface of slot part about 10nm.Like this, after forming heat oxide film, at the dielectric films such as silicon oxide layer about deposition 500nm on the first type surface of Semiconductor substrate 13, (Chemical MechanicalPolishing: cmp) method is filled silicon oxide layer in slot part, thereby forms area of isolation 25 by CMP.
Like this, by optionally forming area of isolation 25, on the first type surface of Semiconductor substrate 13, stipulate the ROM shown in Figure 1 zone 63 of formation memory cell transistor 27 shown in Figure 2 or ram region 62, logical circuit zone (peripheral circuit region) 65 etc.
Like this, form after the area of isolation 25, for example form dielectric film 30 with the thickness about 5nm on the first type surface of Semiconductor substrate 13, this dielectric film 30 is made of the silica that for example forms by the oxidizing process as ISSG (In-SituSteam Generation: on-the-spot steam generates) oxidizing process.Herein, as shown in Figure 6, for example introducing on the first type surface of the Semiconductor substrate 13 at memory cell region 67 places of Fig. 1, charge density is 10
18/ cm
3About impurity, form extrinsic region 16a.
Fig. 8 is the profile of memory cell region 67 of the 2nd step (the formation step of the 1st conducting film) of conductor integrated circuit device 10.In addition, Fig. 9 is the profile of peripheral circuit region 65 in the 2nd step of conductor integrated circuit device 10.As this Fig. 8, shown in Figure 9, for example on the upper surface of the dielectric film 30 that forms on memory cell on the first type surface of Semiconductor substrate 13 67 and peripheral circuit region 65 whole, deposit the conducting film 31 that constitutes by polysilicon film about 2.9nm.And, by using TEOS (Tetraethoxysilane: deposition dielectric film 32 on the upper surface of this conducting film that constitutes by polysilicon film 31 such as the CVD method of gas tetraethoxysilane).
Figure 10 is the profile of the middle memory cell region 67 of the 3rd step (pattern step of the 1st conducting film) of conductor integrated circuit device 10.As shown in figure 10, dielectric film 32 and conducting film 31 are implemented composition, form conductive pattern 31a, this conductive pattern 31a forms peristome 31b on the zone in the source region 15 that forms memory cell transistor shown in Figure 2 27.Figure 11 is the profile of peripheral circuit region 65 in the 3rd step of conductor integrated circuit device 10.As shown in Figure 11, conductive film figure 31a covers on the first type surface of Semiconductor substrate 13 of peripheral circuit region 65.
Figure 12 is the profile of the middle memory cell region 65 of the 4th step (the formation step in the storage grid lower channel zone 14 of memory cell transistor) of conductor integrated circuit device 10.As shown in Figure 12, conductive film figure 31a has the peristome 31b that the part in the extrinsic region 16a upper surface is exposed.And, this conductive film figure 31a as mask, is introduced the conduction type impurity different with the conduction type of extrinsic region 16a at the first type surface of Semiconductor substrate 13.Like this, when the first type surface of Semiconductor substrate 13 is introduced the conduction type impurity different with the conduction type of extrinsic region 16a, the formation charge density extrinsic region 14a littler than the charge density of extrinsic region 16a.Like this, at the part residual impurity first type surface that is positioned at Semiconductor substrate 13, under the conductive film figure 31a zone 16a, the part at the peristome 31b place of conductive film figure 31a forms the extrinsic region 14a littler than extrinsic region 16a charge density.
Like this, by on conductive film figure 31a, forming peristome 31b in advance, even also can carry out the isolation (beat Chi and divide け) of the different extrinsic region of concentration without mask.
Like this, can carry out maskless and inject, more easily form storage grid lower channel zone 14 with conductive pattern 31a as mask.Figure 13 is the profile of peripheral circuit region 65 in the 4th step of conductor integrated circuit device 10.As shown in Figure 13, in peripheral circuit region 65, the dielectric film 32 that on roughly whole of the first type surface of Semiconductor substrate 13, forms conducting film 31 and on this conducting film 31, form.
Figure 14 is the profile of memory cell region 67 of the 5th step (the formation step of the 2nd dielectric film) of semiconductor integrated circuit 10.As shown in Figure 14, remove dielectric film 32, the dielectric film that constitutes by silica in the mode that covers conductive film figure 31a lamination successively, the dielectric film that constitutes by silicon nitride, the dielectric film that constitutes by silica.Thus, form dielectric film 33 in the mode that covers conductive film figure 31a.And, can adopt the thermal oxidation method as ISSG oxidizing process etc. to form silica.As mentioned above, when on conductive pattern 31a, forming dielectric film 33, on the first type surface of the Semiconductor substrate 13 at peristome 31b place, also form heat oxide film.On the other hand, between the first type surface of conductor fig 31a and Semiconductor substrate 13, form dielectric film 30.And, the conducting film 34 that deposition is made of polysilicon film etc. on the upper surface of this dielectric film 33.
Figure 15 is the profile of the peripheral circuit region of the 5th step in the conductor integrated circuit device 10.As shown in Figure 15, in the 5th step of conductor integrated circuit device 10, zone at peripheral circuit region shown in Figure 1 65 places is at the conducting film 34 that forms the conductive film figure 31a that forms via dielectric film 30, the dielectric film 33 that is forming on the upper surface of this conductive film figure 31a, formation on this dielectric film 33 on the first type surface of Semiconductor substrate 13.
Figure 16 is the profile of memory cell region of the 6th step (the formation step in storage grid, source region) of conductor integrated circuit device 10.As shown in Figure 16, the conducting film 34 that is formed on dielectric film 33 upper surfaces is carried out etching, on the medial surface of the peristome 31b of conductive film figure 31a, form the storage grid 45 of side wall shape.Like this, by on conductive film figure 31a, forming peristome 31b in advance, thereby can be formed naturally storage grid 45.That is, when forming storage grid 45,, thereby can realize reducing the number of mask even do not use mask also can form storage grid 45.
And, because can be formed naturally storage grid 45, so, different with the situation that forms storage grid 45 by photoetching process, can prevent the offset that skew produced, or generation forms problems such as bad with mask.
Herein, in the first type surface of Semiconductor substrate 13, formed extrinsic region 14a by storage grid 45 area surrounded of side wall shape.And, conductive film figure 31a and storage grid 45 as mask, are introduced impurity, form the impurity diffusion layer 15a of the low concentration of n type.Therefore, residual impurity zone 14a forms storage grid lower channel zone 14 on the first type surface that is positioned at the Semiconductor substrate 13 under the storage grid 45.And, on the first type surface that is positioned at the Semiconductor substrate 13 under the conductive film figure 31a, form extrinsic region 16a.Like this,, can inject by maskless and form storage grid lower channel zone 14, simultaneously, can form the low concentration impurity layer 15a in source region 15 according to the manufacture method of the conductor integrated circuit device 10 of present embodiment 1.
Figure 17 is the profile of peripheral circuit region in the 6th step of conductor integrated circuit device 10.As shown in Figure 17, on the first type surface of the Semiconductor substrate 13 of peripheral circuit region, form conducting film 31 and be formed on dielectric film 33 on these conducting film 31 upper surfaces successively.
Figure 18 is the profile of memory cell area of the 7th step (control grid and grid form step) of conductor integrated circuit device 10, and Figure 19 is the profile of peripheral circuit region in the 7th step of conductor integrated circuit device 10.In the 7th step, at first remove the dielectric film 33 that on Figure 16, memory cell region shown in Figure 17 and peripheral circuit region, forms.Herein, in memory cell region, dielectric film 33 in removing on the first type surface of the dielectric film 33 that on the upper surface of conductive film figure 31a, forms, Semiconductor substrate 13, that form on the zone by storage grid 45 clampings.In addition, at peripheral circuit region, remove the dielectric film 33 that on the upper surface of conductive film figure 31a, forms.Therefore, dielectric film 33 remains on the side of peristome 31b side of conductive pattern 31a and is positioned on the first type surface of the Semiconductor substrate 13 under the storage grid 45.That is, the lower surface across formed storage grid 45 forms dielectric film 33 to the side.Like this, form dielectric film 44 shown in Figure 2.
And, remove after the part of dielectric film 33, on the upper surface of conductive pattern 31a, dispose photomask, by photoetching process conductive pattern 31a is implemented composition.By this composition, thereby form grid 43a, the 43b of the formation peripheral circuit transistor 28a of institute, 28b on the control grid 42, peripheral circuit region of formed memory cell transistor 27 on the memory cell region simultaneously.
And, expose drain region 19b, the 20b of the drain region 17 of memory cell transistor shown in Figure 2 27, peripheral circuit transistor 28a, 28b by being patterned at the outside.
In the composition of this conductive film figure 31a, adopt the bigger etching of selection of silicon oxide layer and polysilicon film, thus, can suppress the first type surface of the Semiconductor substrate 13 at each drain region 17,19b, 20b place is caused etching injury.Like this, minimizing causes etching injury to the first type surface of the Semiconductor substrate 13 at each drain region 17,19b, 20b place, thus, can suppress the first type surface depression of the Semiconductor substrate 13 at each drain region 17,19b, 20b place.
Figure 20 is the profile of the middle memory cell region of the 8th step (the formation step of the drain region of memory cell transistor and the transistorized extrinsic region of peripheral circuit) of conductor integrated circuit device 10.In addition, Figure 21 is the profile of peripheral circuit region in the 8th step of conductor integrated circuit device 10.Among this Figure 20, Figure 21, use the mask 72 of the regional opening at the source region 19a of drain region 17, peripheral circuit transistor 28a of memory cell transistor 27 shown in Figure 1 and 19b place, drain region, carry out photoetching.And,, form low concentration impurity diffusion layer 17a, low concentration impurity diffusion layer 19a1, the 19b1 of peripheral circuit transistor 28a of memory cell transistor 27 to the first type surface implanted dopant of the Semiconductor substrate of exposing from formed photoresist 13.
In the manufacture method of the conductor integrated circuit device 10 of present embodiment 1, on the first type surface of the Semiconductor substrate 13 at drain region 17,19b, 20b and source region 19a, 20a place, do not form the dielectric film 33 that constitutes by so-called ONO film herein.Therefore, on the first type surface of the Semiconductor substrate 13 at drain region 17,19b, 20b and source region 19a, 20a place the silicon oxide layer to the ONO film implement thermal oxidation.Thus, the first type surface of the Semiconductor substrate 13 at drain region 17,19b, 20b and source region 19a, 20a place can suppress depression by the film formed thermal oxidation of ONO.
And, do not form the ONO film on the first type surface of the Semiconductor substrate 13 at drain region 17,19b, 20b and source region 19a, 20a place, so, can not produce the damage when removing the ONO film, the first type surface that can further suppress the Semiconductor substrate 13 at drain region 17,19b, 20b and source region 19a, 20a place caves in.
And, when forming low concentration impurity diffusion layer 17a as mentioned above, be positioned on the first type surface of the Semiconductor substrate 13 of control under the grid 42 residual extrinsic region 16a shown in Figure 180 as control grid lower channel zone 16.
Figure 22 is the profile of the middle memory cell region of the 9th step (the formation step of the transistorized extrinsic region of peripheral circuit) of semiconductor integrated circuit 10.In addition, Figure 23 is the profile of peripheral circuit region in the 9th step of semiconductor integrated circuit 10.As this Figure 22, shown in Figure 23, in the 9th step, configuration photomask 73 on the first type surface of Semiconductor substrate 13 forms the photoresist of part opening at source region 20a, the 20b place, drain region of peripheral circuit transistor 28b by photoetching process.And, introduce impurity at the first type surface of the Semiconductor substrate 13 at source region 20a, 20b place, drain region, form low concentration impurity diffusion layer 20a1,20b1.
Figure 24 is the profile of memory cell region of the 10th step (the formation step of memory cell transistor and the transistorized side wall of peripheral circuit) of conductor integrated circuit device 10.In addition, Figure 25 is the profile of peripheral circuit region in the 10th step of conductor integrated circuit device 10.Among this Figure 24,25, for example on the first type surface of Semiconductor substrate 13, form the dielectric film 36 that constitutes by silicon oxide layer etc. by CVD method etc.And, this dielectric film 36 is implemented etching, on the side of control grid 42 and grid 43a, 43b, form the dielectric film 36,46 of side wall shape.
And, first type surface in Semiconductor substrate 13 is introduced impurity, on the first type surface of Semiconductor substrate 13, form high concentration impurity diffusion layer 17b, 15b and high concentration impurity diffusion layer 19a 2,19b2, form memory cell transistor 27 and peripheral circuit transistor 28a.And, behind formation high concentration impurity diffusion layer 20a2, the 20b2, form peripheral circuit transistor 28b.
Figure 26 is the profile of memory cell region of the 11st step (metal silicide formation step) of conductor integrated circuit device 10.In addition, Figure 27 is the profile of outer peripheral areas of the 11st step of conductor integrated circuit device 10.
As this Figure 26, shown in Figure 27, on the upper surface of source region 19a, the 20a of the upper surface of the control grid 42 of formed memory cell transistor 27, source region 15, drain region 17, peripheral circuit transistor 28a, 28b and drain region 19b, 20b, form the metal silicide film 37 that waits formation by cobalt silicide (CoSi) or nickle silicide (NiSi).At this moment, the metal silicide film 37 that will be formed on control grid 42 upper surfaces by dielectric film 44 completely cuts off with metal silicide film 37 electricity that are formed on storage grid 45 upper surfaces.
Figure 28 is the profile of the middle memory cell region of the 12nd step (bit line formation step) of conductor integrated circuit device 10.In addition, Figure 29 is the profile of peripheral circuit region of the 12nd step of conductor integrated circuit device 10.As this Figure 28, shown in Figure 29, on the upper surface of formed memory cell transistor 27, peripheral circuit transistor 28a, 28b, form dielectric film 52, on the upper surface of this dielectric film 52, form interlayer dielectric 38.And, form through being formed on the dielectric film 52 on the high concentration impurity diffusion layer 17b and the contact site 49 of interlayer dielectric 38.And, on interlayer dielectric 38, form wiring 48a, 48b, 48c, 48d.As mentioned above, form Fig. 2, conductor integrated circuit device 10 shown in Figure 3.
In the manufacture method of described conductor integrated circuit device 10, can be suppressed on the first type surface of semiconductor device 13 at drain region 17,19b, 20b and source region 19a, 20a place and form recess, so, form drain region 17,19b, 20b and source region 19a, 20a on can be at the first type surface of the distance Semiconductor substrate 13 more shallow position.
Herein, when on the zone that becomes drain region 17,19b, 20b and source region 19a, 20a, forming recess, be positioned at the borderline region formation step difference of the first type surface of control grid 42, grid 43a, 43b Semiconductor substrate 13 down and drain region 17,19b, 20b, source region 19a, 20a.And, for example forming on the borderline region under the state of 30nm left and right sides step difference, when introducing impurity on the zone that becomes drain region 17,19b, 20b and source region 19a, 20a, it is big that the charge density of the impurity of borderline region becomes, and this is known.Therefore, when making the impurity thermal diffusion of being introduced, on the direction of the relative first type surface level of Semiconductor substrate 13, also spread.Consequently, produce following problem: the distance between source region 15,19a, 20a and drain region 17,19b, the 20b diminishes, and the threshold voltage of memory cell transistor 27 sharply diminishes.And the threshold voltage of each memory cell transistor 27 produces deviation.
On the other hand, according to the manufacture method of the conductor integrated circuit device 10 of present embodiment 1, can be suppressed on the upper surface of drain region 17,19a, 20a and source region 19a, 20a and form recess.Therefore, can suppress the bigger step difference of formation on the borderline region with the first type surface that is positioned at control grid 42,43a, 43b Semiconductor substrate 13 down.
Figure 38 is the profile of memory cell transistor 27 of representing the conductor integrated circuit device 10 of execution mode 1 in detail.
As shown in Figure 38, the first type surface of the Semiconductor substrate 13 of control under the grid 42 and with respect between the first type surface R1 of the Semiconductor substrate 13 of the storage grid 45 opposite sides of control grid 42, perpendicular to the distance h 2 of Semiconductor substrate 13 first type surface directions, for example be about 2nm～3nm.And, be about 10nm in the first type surface R2 and the distance h 1 between the first type surface of the Semiconductor substrate 13 under the control grid 42 of the Semiconductor substrate under the storage grid 45 13.
That is, littler than distance h 1 in order to make distance h 2, the first type surface that is positioned at the Semiconductor substrate 13 under the dielectric film 46 is compared with the first type surface of Semiconductor substrate 13 under being positioned at storage grid 45, and it is positioned at the top.And, as Figure 20 and shown in Figure 38, first type surface R2 does not almost have step difference with the borderline region of the first type surface that is positioned at the Semiconductor substrate 13 under the control grid 42, at borderline region is under the planar state of general planar, introduce impurity at first type surface R2, form low concentration impurity diffusion layer 17a, so the charge density that can suppress the impurity that imported produces deviation.
Figure 85 is the profile of the transistorized details of expression peripheral circuit.Shown in this Figure 85, even when making impurity that diffusion take place, also can suppress impurity with the direction of the major surfaces in parallel of Semiconductor substrate 13 on diffusion bigger, the threshold voltage of formed memory cell transistor 27 is become desirable value, and can suppress the threshold voltage generation deviation of a memory cell transistor 27.
And, the time that the first type surface of Semiconductor substrate 13 that is positioned at grid 43a, the 43b two sides side of peripheral circuit transistor 28a, 28b produces damage with when conductive film figure 31a implements composition, produce, to produce the time of damaging at first type surface R1 shown in Figure 38 be the identical time.
Therefore, the bigger step difference part of formation on the borderline region of the first type surface that can be suppressed at the Semiconductor substrate 13 that is positioned at grid 43a, 43b two sides side and the first type surface that is positioned at the Semiconductor substrate 13 grid 43a, 43b under.Accompany therewith, even in peripheral circuit transistor 28a, 28b, the distance that also can suppress between source region 19a, 20a and drain region 19b, the 20b diminishes, and the threshold voltage that can suppress peripheral circuit transistor 28a, 28b diminishes, and can become desirable threshold voltage.
And, be positioned at the Semiconductor substrate 13 under grid 43a, the 43b first type surface and adjacent to the first type surface of the Semiconductor substrate 13 of grid 43a, 43b, for example can suppress perpendicular to the distance of the direction of first type surface for about 2nm～3nm.And, in Fig. 6, manufacturing step shown in Figure 7, the charge density that makes the impurity on the first type surface of the Semiconductor substrate 13 that is incorporated into the memory cell region place is smaller or equal to the charge density on the first type surface of the Semiconductor substrate 13 that is incorporated into the peripheral circuit region place.
In such cases, by the thermal oxidation in Fig. 6, the manufacturing step shown in Figure 7, the thickness of formed dielectric film 30 is smaller or equal to the thickness of formed dielectric film 30 on the first type surface of the Semiconductor substrate 13 at peripheral circuit region place on the first type surface of the Semiconductor substrate 13 at memory cell region place.
And, the dielectric film 30 that first type surface R1 shown in Figure 38 go up to form and be positioned at that formed dielectric film 30 all is removed on the first type surface of Semiconductor substrate 13 of side of grid 43a, 43b of peripheral circuit transistor 28a, 28b, so, first type surface R1 compares with the first type surface of the Semiconductor substrate 13 of the side that is positioned at grid, and it is positioned at the top.Thus, can with the threshold voltage settings of memory cell transistor 27 desirable threshold voltage.
Herein, the 4th step of conductor integrated circuit device 10 (the formation step in the grid lower channel zone of memory cell transistor), the 5th step (the formation step of the 2nd dielectric film), the 6th step (the formation step in storage grid, source region) are the memory cell transistor 27 distinctive manufacturing steps different with the manufacturing step of peripheral circuit transistor 28a, 28b.When carrying out such memory cell transistor 27 distinctive steps, cover with conductive film figure 31a on the first type surface of Semiconductor substrate 13 at peripheral circuit region place, can suppress influence to the Semiconductor substrate 13 at peripheral circuit region place.
On the other hand, carry out following steps respectively simultaneously: control grid and the transistorized grid of peripheral circuit are carried out composition; Form the drain region 17 of memory cell transistor 27 and drain region 19b, the source region 19a of peripheral circuit transistor 28a; Form each side wall; Form metal silicide film.
Like this, at first under the state that covers peripheral circuit region, carry out memory cell transistor 27 distinctive steps, then, carry out the common step of memory cell transistor 27 and peripheral circuit transistor 28a, 28b, thus, can reduce the number of manufacture steps of conductor integrated circuit device 10.
(execution mode 2)
Use Figure 30 to Figure 45 the conductor integrated circuit device 10 of embodiment of the present invention 2 to be described to Figure 33 and Figure 39.Figure 39 is the profile of memory cell region 67 of the conductor integrated circuit device 10 of present embodiment 2.As shown in Figure 39, conductor integrated circuit device 10 has: area of isolation 90 optionally is formed on the first type surface of Semiconductor substrate 13 at memory cell region 67 places; A plurality of memory cell region MCR1, MCR2 cut apart by these area of isolation 90 regulations; Control grid 42 is formed on and respectively cuts apart on memory cell region MCR1, the MCR2; Join domain PR is between the connected storage grid 45.
And, on the first type surface of the Semiconductor substrate 13 of respectively cutting apart memory cell region MCR1, MCR2 place, formed a plurality of control grids 42 that extend in a direction and the storage grid 45 that on the side of this control grid 42, forms via dielectric film 44.
In addition, on the first type surface of the Semiconductor substrate between the control gate utmost point 42 13, forming area of isolation 92.And, on the first type surface of the Semiconductor substrate between the control gate utmost point 42 13, stipulating a plurality of drain regions 17 by this area of isolation 92.And, on each drain region 17, be provided with the contact site 49 that each drain region 17 is applied desirable voltage.
On the first type surface of the Semiconductor substrate between the storage grid 45 13, forming the source region 15 of extending along storage grid 45.On the first type surface of the Semiconductor substrate 13 between this source region 15 and the drain region 17, forming channel region 75 shown in Figure 2.Forming connecting wiring (the 1st connecting portion) 45A on the adjacent area of isolation of cutting apart between memory cell region MCR1, the MCR2 90, it is connected to form at one cuts apart the storage grid 45 on the memory cell region MCR1 and is formed on the adjacent storage grid of cutting apart on the memory cell region MCR2 45 via area of isolation 90.
And, connecting portion (the 1st connecting portion) 59 in the upper surface of area of isolation 90, that connect between the part between the connecting wiring 45A forms connecting wiring 45A forms the contact site (voltage application portion) 69 that storage grid 45 is applied desirable voltage on the 1st connecting portion 59.
In addition, form connecting wiring (the 3rd connecting portion) 42A on this area of isolation 90, it is connected to form is cutting apart the control grid 42 on the memory cell region MCR1 and is being formed on the control grid of cutting apart on the memory cell region MCR2 42.Form the contact site 68 that control grid 42 is applied desirable voltage on this connecting wiring, form welding disk 93 in the bottom of this contact site 68.
Figure 30 is the profile of the details of the connecting portion 59 shown in expression Figure 39.As shown in Figure 30, connecting portion 59 has: conducting film (residual portion) 31A, be formed on the upper surface of area of isolation 90, and for example constitute by polysilicon membrane etc.; Dielectric film (the 5th dielectric film) 44 is formed on the side (side face) of this residual 31A, for example is made of ONO film etc.; Conducting film (the 2nd conducting film) 31B is formed on residual the side face on the 31A, is filled between the connecting wiring 45A.On the upper surface of the connecting portion 59 that constitutes like this, form contact site 69.Therefore, the voltage that is applied on the contact site 69 is sent on the connecting wiring 45A by conducting film 31B, imposes on each storage grid 45.
And in present embodiment 2, the direction of extending at storage grid 45 between storage grid 45A has formed residual the 31A in 2 places (a plurality of), still, is not limited to this, also can be 1 place.Manufacture method to the conductor integrated circuit device 10 that constitutes as mentioned above describes.Figure 40 illustrates the profile of Fig. 6 in the manufacturing step with the conductor integrated circuit device 10 of described execution mode 1, manufacturing step that the 1st manufacturing step shown in Figure 7 is corresponding.
As shown in Figure 40, on the first type surface of Semiconductor substrate 13, optionally form area of isolation 90,92.Thus, on the first type surface of Semiconductor substrate 90, form and cut apart memory cell region MCR1, MCR2 by area of isolation 90 regulations.And, on the first type surface of the Semiconductor substrate 13 of respectively cutting apart memory cell region MCR1, MCR2 place, form active region 91 by area of isolation 92 regulations.
Figure 41 is the profile of expression XLI-XLI line manufacturing step, Figure 10 corresponding with the 3rd step of the conductor integrated circuit device 10 of described execution mode 1, and Figure 31 is the profile of the details on the area of isolation 90 among expression Figure 41.
As this Figure 41, shown in Figure 31, when forming conductive film figure 31a, on area of isolation 90, form residual 31A, this conductive film figure 31a forms peristome 31b on the zone at 15 places, formed source region.
And the distance L 1 between the conductive film figure 31a for example forms about 300nm.In addition, the width L2 of residual 31A of the direction that a plurality of conductive film figure 31a arrange for example forms about 150nm, and the width L3 of residual 31A of the direction that conductive film figure 31a extends forms for example about 100nm.And, forming under the situation of a plurality of residual 31A, for example be that mode about 100nm forms residual 31A with the distance L 4 between residual the 31A.In addition, the distance L 5 between residual 31A and the adjacent conductive film pattern 31a forms for example below the 100nm.
Figure 42 and Figure 43 are the profiles of XLII-XLII line manufacturing step, Figure 14 corresponding with the 5th step of the conductor integrated circuit device 10 of described described execution mode 1 shown in Figure 14, and Figure 32 is the profile of upper surface of representing the area of isolation 90 of Figure 42 in detail.
As Figure 14, shown in Figure 42, cover conductive film figure 31a, simultaneously, on the first type surface of the Semiconductor substrate between the conductive film figure 31a 13, forming dielectric film 33.Thus, also forming dielectric film 33 on the two sides of conducting film 31a and on the surface of residual 31A.And, depositing electrically conductive film 34 on the upper surface of this dielectric film 33.
And,, on the upper surface of dielectric film 33, form conducting film 34 as Figure 14, Figure 32, shown in Figure 43.At this moment, fill gap between residual the 31A and the gap between residual 31A and the conductive film figure 31a by conducting film 34.
Figure 44 is the profile of the XLIV-XLIV line of, Figure 16 corresponding with the 6th step of the conductor integrated circuit device 10 of the described execution mode 1 shown in described Figure 16, and Figure 33 is the profile of the details of area of isolation 90 among expression Figure 44.
As these Figure 16, Figure 33, shown in Figure 44, conducting film 34 is implemented etching, form storage grid 45.
At this moment, when forming storage grid shown in Figure 2 45, residual conducting film 31B on the surface of residual 31A., dispose in mutual approaching mode between residual the 31A herein, so, be connected to form between the conducting film 31B on residual 31A surface, make it into as a whole.In addition, since also approaching between residual 31A and the conductive pattern 31a, so the conducting film 31B and the formed storage grid 45 that are formed on residual 31A surface are connected.That is, in the step that forms storage grid 45, connect as a whole by the conducting film 31B that is formed on residual 31A surface between the storage grid 45 of arranged opposite.
Like this, in the pattern step in the manufacturing step of the conductor integrated circuit device 10 shown in the aforesaid execution mode 1, conducting film 31, conducting film 31 is implemented composition to form residual 31A, thus, can be formed naturally connecting portion 59.
Figure 45 is the profile of XLV-XLV line manufacturing step, Figure 18 behind the manufacturing step of the conductor integrated circuit device 10 of expression shown in described Figure 44.As shown in Figure 45, conductive film figure 31a is implemented composition, the zone that becomes drain region 17 is exposed, simultaneously, form welding disk 93.
And, as shown in figure 30, on the upper surface of formed connecting portion 59, form contact site 69.That is, connecting portion 59 is used as the lead division of storage grid shown in Figure 2 45.And the manufacturing step beyond the manufacturing step of described conductor integrated circuit device 10 comprises the manufacturing step of the conductor integrated circuit device 10 of record in the described execution mode 1.
According to the manufacture method of the conductor integrated circuit device 10 of such present embodiment 2, do not need to be provided with the step of the lead division that forms storage grid 45, just can reduce the total number of steps and the mask number of the manufacturing step of conductor integrated circuit device 10.And, form residual 31A during pattern step in the manufacturing step of the conductor integrated circuit device 10 of described execution mode 1, conducting film 31, the manufacture method of the conductor integrated circuit device 10 of present embodiment 2 can obtain effect and the effect identical with the conductor integrated circuit device 10 of execution mode 1.
(execution mode 3)
Use Figure 46 the conductor integrated circuit device 10 of present embodiment 3 to be described to Figure 52.And the identical symbol of structure mark to identical with the conductor integrated circuit device 10 of described execution mode 1 or execution mode 2 omits its explanation.
Figure 46 is the plane graph of the conductor integrated circuit device 10 of present embodiment 3.Among this Figure 46, conductor integrated circuit device 10 has: area of isolation 90 optionally is formed on the first type surface of Semiconductor substrate 13 at memory cell region 67 places; Active region 91 by the band shape of this area of isolation 90 regulations; Be formed on source region 15 and drain region 17 on each area of isolation 91; A plurality of control grids (the 1st grid) 42A, 42B with ring-type formation; The ring storage grid (the 2nd grid) 45A, the 45B that on the side of source region (the 1st extrinsic region) 15 sides of control grid 42A, 42B, form via dielectric film 44.
And source region 15 is formed on the both ends of this banded active region 19, and drain region 17 is formed on the central portion of banded active region 91.And channel region 75 is formed between the drain region 17 and source region 15 of active region 91.
Therefore, the active region 91 that 91 long axis direction is adjacent in the active region disposes in source region 15 mutual opposed modes.And, on each source region 15, form contact site (voltage application portion) 51.This voltage application portion is connected with upper strata wiring 48B, 48C.
Like this, each source region 15 is applied voltage, reduce the cloth line resistance by contact site or wiring by formations such as little barrier metal in resistance ratio active region (barrier metal) or tungsten.
Therefore, the voltage change in source region 15 can be suppressed to be applied to, no matter on the source region 15 of which memory cell transistor, desirable voltage can be applied, and can suppress misoperation by the position of selected memory cell transistor.
, connect by the active region under the situation in source region 15 of each memory cell transistor herein, when write activity,, need apply bigger voltage shared source region for the source region to each memory cell transistor applies desirable voltage.But, like this under the shared state in the source region 15 of a plurality of memory cell transistors, when applying big voltage,, cause being easy to generate misoperation even in non-selected memory cell transistor, also can cause write activity.On the other hand, as mentioned above, each source region is made respectively independently source region, and the wiring low by the resistance ratio active region applies voltage, thus, can suppress misoperation.
Figure 47 is the profile of the XLVII-XLVII line of Figure 46.As shown in Figure 47, on the first type surface of Semiconductor substrate 13, form memory cell transistor 27A that comprises control grid 42A and memory cell transistor 27B, the 27C that comprises control grid 42B.And, the shared drain region 17 of memory cell transistor 27A, 27B.On this shared drain region 17, form contact site 49 with barrier metal 39 and tungsten film 50.
This contact site 49 is connected with upper strata wiring 48B, and, be connected with bit line 95 by contact site 94.
In addition, comprise the control grid 42B that forms ring-type, adjacent memory unit transistor 27B isolates by area of isolation 90 mutually.And Figure 48 is the profile of the XLVIII-XLVIII line of Figure 46, is near the profile the welding disk 59.As shown in Figure 48, recess 96 is positioned on the area of isolation 90, forms dielectric film 44 on the upper surface of the area of isolation 90 at the inner surface of this recess 96 and this recess 96 places.
And, on the medial surface of this recess 96, form storage grid 45 with the side wall shape, be formed on storage grid 45 on the medial surface of recess 96 and the storage grid 45 that is formed on another medial surface and be in contact with one another.
Like this, the welding disk 59 of contact site 69 constitutes by being formed on storage grid 45 in the recess 96, that be in contact with one another.
And the width of recess 96 is than 2 times little of the width of storage grid shown in Figure 46 45, less than 60nm.
And the structure beyond the described structure is identical with conductor integrated circuit device 10 structures of illustrated embodiment 1 or execution mode 2.Figure 83 is the circuit diagram of the conductor integrated circuit device 10 that constitutes as mentioned above, and Figure 84 is its schematic diagram.
As mentioned above, respectively the moving of conductor integrated circuit device 10 that is constituted described.Figure 80 is the action line chart of reading when action of the conductor integrated circuit device 10 of present embodiment 3.In this Figure 80 and Figure 46, on the source region 15 of selected memory cell, apply the voltage about 0V.And, on the storage grid 45 of selected memory cell, apply for example voltage about 0V.And, on the control grid 42 of selected memory cell, apply for example voltage about 1.5V, on drain region 17, apply for example voltage about 1V, on Semiconductor substrate 13, apply the voltage about 0V.
Figure 81 is the action line chart of write activity.Shown in this Figure 81, on the source region 15 of selected memory cell, apply for example voltage about 6V, on storage grid 45, apply for example voltage about 11V.And, on the control grid 42 of selected memory cell, apply the voltage about 1V, simultaneously, on drain region 17, apply the voltage about 0.8V～1.5V, on Semiconductor substrate 13, apply the voltage about 0V.
Figure 82 is the action line chart of erasing move.Shown in this Figure 82, on the source region 15 of selected memory cell, apply for example voltage about 6V, and, on storage grid 45, apply for example voltage of 3V, on drain region 17 and control grid, apply the voltage about 0V.And, on Semiconductor substrate 13, apply the voltage about 0V.Herein, for example applying on the storage grid 42 of non-selected memory cell-voltage about 6V.
Manufacture method to the conductor integrated circuit device 10 of the present embodiment 3 that as above constitutes describes.
Figure 49 is the plane graph of the step corresponding with the 1st step of the manufacturing step of the conductor integrated circuit device 10 of the described execution mode 1 shown in described Fig. 6, Fig. 7.
As shown in Figure 49, on the first type surface of the Semiconductor substrate 13 at memory cell region 67 places, form area of isolation 90, stipulate a plurality of active regions 91.
Figure 50 is the plane graph of the expression manufacturing step corresponding with the 3rd step of the conductor integrated circuit device 10 of the described execution mode 1 shown in described Figure 10, Figure 11.
As shown in Figure 50, form conductive film figure 31a, this conductive film figure 31a has peristome 31b on the zones in each active region 91,15 places, source region.At this moment, simultaneously recess 96 is carried out composition in the both ends side of the long axis direction of peristome 31b.
Figure 51 is the plane graph of the expression manufacturing step corresponding with described Figure 16, Figure 17.As this Figure 51 and shown in Figure 16, forming dielectric film 44 on the surface of conductive film figure 31a and on the first type surface of the Semiconductor substrate 13 at peristome 31b place.At this moment, all forming conducting film 34 on the inner surface of recess 96 and on the area of isolation 90 at these recess 96 places.
And deposition (formation) conducting film 34 carries out etching to this conducting film 34 on the upper surface of this dielectric film 44, forms storage grid 45 via dielectric film 34 on the surface of peristome 31b.
At this moment, as Figure 51 and shown in Figure 48, in recess 96,, be formed naturally welding disk 59 with the conducting film 34 of the residual formation storage grid 45 of side wall shape., form by photoetching process under the situation of welding disk 59 herein, need have the tolerance limit (margin) of formed welding disk and control grid, perhaps need to have the tolerance limit of using when producing bad the grade.On the other hand, as mentioned above, under situation about forming naturally, do not need such tolerance limit, compare, can realize the granular of conductor integrated circuit device 10 with the situation that forms welding disk by photoetching process.
Figure 52 is the plane graph of the manufacturing step behind the manufacturing step shown in the described Figure 51 of expression.Shown in this Figure 52, conductive film figure 31a is implemented composition, form control grid 42, simultaneously, carry out composition and also form other the transistorized grid of peripheral circuit.
And the step beyond the described manufacturing step is identical with the manufacturing step of described execution mode 1,2.
(execution mode 4)
Use Figure 53 the conductor integrated circuit device 10 of present embodiment 4 to be described to Figure 66.Figure 53 is the plane graph of for example ram region 62 of the conductor integrated circuit device 10 of present embodiment 4.Shown in this Figure 53, on the first type surface of the Semiconductor substrate 13 at ram region 62 places, form memory cell M1～M6 of a plurality of SRAM.
On the first type surface of Semiconductor substrate 13, dispose each memory cell M1～M6 with mutual line symmetrical manner.Use Figure 54 that the structure of the memory cell M1 of SRAM is carried out simple declaration.Memory cell M1 has the whole CMOS cellular construction, has the 1st inverter and the 2nd inverter.Figure 54 illustrates the equivalent electric circuit of this memory cell M1.Use Figure 54 that the structure of the memory cell M1 of SRAM is carried out simple declaration.Memory cell M1 has the whole CMOS cellular construction, has the 1st and the 2nd inverter, 2 access nmos pass transistor N3, N4.
The 1st inverter comprises the 1st driver MOS transistor N1 and the 1st load PMOS transistor P1, and the 2nd inverter comprises the 2nd driver MOS transistor N2 and the 2nd load PMOS transistor P2.
The 1st inverter forms the trigger that is connected mutual input and output with the 2nd inverter, the source electrode of the 1st access nmos pass transistor N3 is connected with the 1st memory node Na of trigger, and the source electrode of the 2nd access nmos pass transistor N4 is connected with the 2nd memory node Nb of trigger.
Memory node Na is connected with bit line BL1 by the 1st access nmos pass transistor N3, and memory node Nb is connected with bit line BL2 by the 2nd access nmos pass transistor N4.And the 1st is connected with word line WL with the grid of the 2nd access nmos pass transistor N3, N4, and the 1st is connected with power line VDD with the source electrode of the 2nd load PMOS transistor P1, P2.
Then, the layout to the memory cell M1 of described whole CMOS SRAM describes.Shown in Figure 53, introduce impurity and the P well area is set in the both sides of N well area.And, on the first type surface of Semiconductor substrate 13, optionally form area of isolation 120, regulation active region 102a, 102b, 102c, 102d on P well area and N well area.And, optionally inject N type impurity such as phosphorus among active region 102a, 102b in being formed on the P well area, 102c, the 102d, form impurity diffusion layer, optionally inject p type impurities such as boron in the active region that in the N well area, forms, form impurity diffusion layer.In this explanation, active region 102a, 102b, 102c, 102d be comprise the zone that becomes transistorized source/drain and be positioned at that this is interregional, with the zone in the zone (substrate part) of this zone conductivity type opposite.
The memory cell M1 of present embodiment is made of 6 MOS transistor.Specifically, memory cell M1 is made of the 1st and the 2nd driver nmos pass transistor N1 and N2, the 1st and the 2nd access nmos pass transistor N3 and N4 and the 1st and the 2nd load PMOS transistor P1, P2.
The the 1st and the 2nd access nmos pass transistor N3, N4 and the 1st and the 2nd driver nmos pass transistor N1, N2 are respectively formed on the P well area of N well area both sides, and the 1st and the 2nd load PMOS transistor P1, P2 are formed on the central N well area.The 1st access nmos pass transistor N3 is formed on the cross part of diffusion of impurities zone 102a1 and polysilicon wire 103a, the 2nd access nmos pass transistor N4 is formed on the cross part of active region 102d and polysilicon wire 103d, this diffusion of impurities zone 102a1 comprises the zone that becomes source/drain, and this active region 102d comprises the zone that becomes source/drain.
The 1st driver nmos pass transistor N1 is formed on the cross part of diffusion of impurities zone 102a1 and polysilicon wire 103b, the 2nd driver nmos pass transistor N2 is formed on the cross part of active region and polysilicon wire 103c, this diffusion of impurities zone 102a1 comprises the zone that becomes source/drain, and this active region comprises the zone that becomes source/drain.
The 1st load PMOS transistor P1 is formed on the cross part of diffusion of impurities zone 102b1 and polysilicon wire 103b, the 2nd access PMOS transistor P2 is formed on the cross part of active region 102c and polysilicon wire 103c, this diffusion of impurities zone 102b1 comprises the zone that becomes source/drain, and this active region 102c comprises the zone that becomes source/drain.
Form not shown interlayer dielectric in the mode that covers active region 102a～102d and polysilicon wire 103a～103d, form contact site 104a～1041, this contact site 104a～1041 arrive and are formed on impurity diffusion layer on the 102a～102d of this active region, that play the source/drain function.In this contact site 104a～1041, imbed the conductive layer that is connected usefulness with the upper strata wiring.
And, contact site 104a, the 1041st arrives the grid contact of grid, contact site 104f, 104g are shared contacts the (Shared Contact) that arrives impurity diffusion layer and polysilicon wire, and in addition contact site 104b, 104c, 104d, 104e, 104h, 104i, 104j, 104k are that the diffusion that arrives the diffusion of impurities layer region contacts.
Among Figure 53, the shared N type diffusion of impurities zone and the N type diffusion of impurities zone that becomes the drain electrode of the 1st access nmos pass transistor N3 that becomes the drain electrode of the 1st driver MOS transistor N1 of these transistors.By being formed on contact site 104c, the 1st metal line 105a and contact site (shared contact) 104f on this N type diffusion of impurities zone, the drain electrode of the drain electrode of the 1st driver nmos pass transistor N1 and the 1st access nmos pass transistor N3 is connected with the drain electrode of the 1st load transistor P1.Its terminal becomes the memory node Na of the equivalent circuit diagram shown in Figure 54.
Equally, as the N type diffusion of impurities zone of the drain electrode of the 2nd driver nmos pass transistor N2 with as the N type diffusion of impurities zone of the drain electrode of the 2nd access nmos pass transistor N3, by contact site 104j, the 1st metal line 105b and contact site (shared contact) 104g, be connected with the drain electrode of the 2nd load transistor P2.This terminal becomes the memory node Nb of the equivalent circuit diagram shown in Figure 54.
And, identical with the memory cell M1 of such formation, also can constitute other memory cell.Herein, relative memory cell M1, memory cell M2 is adjacent in the direction that polysilicon wire 103b extends, relative memory cell M1, memory cell M3 is adjacent in the direction that active region 102a～102d extends.In addition, same, relative memory cell M3, memory cell M4 is adjacent in the direction that polysilicon wire 103b extends.
Herein, the end face of the polysilicon wire 103b of memory cell M1 and and the end face of the polysilicon wire 103b of this memory cell M1 adjacent memory unit M2 between for example be about 100nm～120nm.And, for example be about 200nm～220nm between the extrinsic region 102a of memory cell M1 and the extrinsic region 102a of memory cell M2.And, on the end face of mutual opposed polysilicon wire 103a between this polysilicon wire 103a, form dielectric film 44.
In addition, the distance of the end face of the end face of polysilicon wire 103b and polysilicon wire 103d is about 100nm～120nm too.And, also form dielectric film 44 on the end face of, polysilicon wire 103b, 103d opposed at polysilicon wire 103d and polysilicon wire 103b.
Figure 55 is the profile of the LV-LV line of Figure 53.Shown in this Figure 55, the polysilicon wire 103b of memory cell M1, M2 is formed on the 102a of active region via dielectric films such as silicon oxide layer 30.
And the boundary member of the polysilicon wire 103b of the polysilicon wire 103b of memory cell M1 and memory cell M2 is positioned on the area of isolation 90, and this area of isolation 90 is between the active region 102a of the active region of memory cell M1 102a and memory cell M2.From also forming dielectric film 44 on the area of isolation to the surface of the leading section of polysilicon wire 103b, 103b, this area of isolation is between the polysilicon wire 103b of the polysilicon wire 103b of memory cell M1 and memory cell M2.Guarantee by this protection mould 44 to insulate between the polysilicon wire 103b of the polysilicon wire 103b of memory cell M1 and memory cell M2.And, on leading section surface, form the conducting film 34 of side wall shapes via dielectric film 44 at the polysilicon wire 103b of the boundary member between the polysilicon wire 103b.
Use Figure 56 the manufacture method of the conductor integrated circuit device 10 of formation as mentioned above to be described to Figure 66.Figure 56 is the plane graph of the 1st step of manufacturing step of the conductor integrated circuit device 10 of expression present embodiment 4, is the corresponding step of the 1st step with the conductor integrated circuit device 10 of the described execution mode 1 shown in described Fig. 6, Fig. 7.In addition, Figure 57 is the profile of the LVII-LVII line of Figure 56.Shown in this Figure 57, on the first type surface of Semiconductor substrate 13, optionally form area of isolation 120, the regulation active region, and, regulation P well area, N well area.
And, in each P well area and in the N well area, optionally introduce impurity, form extrinsic region 102a～102d.
Figure 58 is the plane graph of the manufacturing step of the conductor integrated circuit device 10 behind the manufacturing step of expression shown in described Figure 56, is the plane graph of the manufacturing step corresponding with the 2nd step of the conductor integrated circuit device 10 of described Fig. 8, described execution mode 1 shown in Figure 9.Figure 59 is the profile of the LIX-LIX line of described Figure 58.
Shown in this Figure 58, Figure 59, on the first type surface of Semiconductor substrate 13, implement thermal oxidation, form the dielectric film 30 that constitutes by silicon oxide layer etc.
And, on the first type surface of Semiconductor substrate 13, deposit the conducting film 31 that constitutes by polysilicon film etc. via dielectric film 30.
Figure 60 is the plane graph of the manufacturing step of the conductor integrated circuit device 10 behind the manufacturing step shown in described Figure 58, is the plane graph of the step corresponding with the 3rd step of the conductor integrated circuit device 10 of Figure 10, described execution mode 1 shown in Figure 11.Figure 61 is the profile of the LXI-LXI line of described Figure 60.
As this Figure 60 and shown in Figure 10, on ROM zone 63, form conductive film figure 31a, this conductive film figure 31a has: peristome 31b is positioned at the zone in the memory cell transistor source region that forms the MONOS structure; A plurality of peristome 31c～31f are formed on the zone shown in the ram region 62 shown in Figure 60.
Specifically, form the conductive film figure 31a that has as the lower part: peristome 31c, it is positioned at as lower area, that is: the zone between the polysilicon wire 103b of adjacent memory unit M1～M6; Peristome 31d, it is positioned at as lower area, that is: the zone between polysilicon wire 103a and polysilicon wire 103c; Peristome 31e is positioned at as lower area, that is: the zone between polysilicon wire 103b and polysilicon wire 103d; Peristome 31f, it is positioned at as lower area, that is: the zone between the polysilicon wire 103c of adjacent memory unit M1～M6.
Among Figure 53, peristome 31c across from the zone between the polysilicon wire 103b of the polysilicon wire 103b of formed memory cell M1 and memory cell M2 to the zone the polysilicon wire 103b of the polysilicon wire 103b of memory cell M3 and memory cell M4 and extend.That is, the mode of extending with the direction of extending at active region 102a～102d forms peristome 31c.In addition, peristome 31d, 31c, 31f are also identical with peristome 31c, and the direction of extending at active region 102a～102d forms with strip.Like this, have the conductive film figure 31a of the peristome 31c～31f that forms with strip, can be by the laser of KrF excimer laser, ArF excimer laser etc. be more easily made as the steeper that light source carries.
Figure 62 is the profile of the manufacturing step behind the manufacturing step of the conductor integrated circuit device 10 of expression shown in described Figure 61, is the profile of the manufacturing step corresponding with the 5th step of the conductor integrated circuit device 10 of the described execution mode 1 shown in described Figure 14, Figure 15.
Shown in this Figure 62, on the surface of conductive film figure 31a, form the dielectric film 44 that constitutes by so-called ONO film on the upper surface of the area of isolation 120 on the internal face of peristome 31c～31f and peristome 31c～31f place.And, on conductive film figure 31a, deposit (formation) conducting film 34 via this dielectric film 44.At this moment, also filled conductive film 34 in peristome 31c～31f.
Figure 63 is the profile of the manufacturing step behind the manufacturing step shown in described Figure 62, is the profile of the manufacturing step corresponding with the 6th step of the conductor integrated circuit device 10 of the described execution mode 1 shown in described Figure 16, Figure 17.Figure 64 is the plane graph of the manufacturing step shown in this Figure 63.
Shown in this Figure 63, conducting film 34 is implemented etching.Thus, as described shown in Figure 64, on the first type surface of the Semiconductor substrate 13 at 63 places, ROM zone, form storage grid 45.At this moment, in peristome 31c～31f, form the conducting film 34 of side wall shape on the medial surface of peristome 31c～31f.
Between the conducting film 34 of this side wall shape and conductive film figure 31a, form dielectric film 44, guarantee the state of insulation between conductive film figure 31a and the conducting film 34.
Figure 65 is the plane graph of the manufacturing step behind the manufacturing step shown in described Figure 64, is the plane graph of the manufacturing step corresponding with the 7th step of the conductor integrated circuit device 10 of the described execution mode 1 shown in described Figure 18, Figure 19.Figure 66 is the profile of the LXV-LXV line of described Figure 65.Shown in this Figure 65, Figure 66, conductive film figure 31a is implemented composition, form polysilicon wire 103a～103d.The step that forms this polysilicon wire 103a～103d at first forms Etching mask on the entire upper surface of conductive film figure 31a.And configuration photomask 200 is implemented exposure-processed to Etching mask above this Etching mask.
Form a plurality of opening figure 200a, 200b on this photomask 200, this a plurality of opening figure 200a, 200b extend along the direction that polysilicon wire 103a～103d extends.
Opening figure 200a for example is made into polysilicon wire 103a and the polysilicon wire 103a of polysilicon wire 103c and memory cell M2 and the figure of polysilicon wire 103c that connects memory cell M1.
In addition, opening figure 200b for example is made into polysilicon wire 103b and the polysilicon wire 103b of polysilicon wire 103d and memory cell M2 and the figure of polysilicon wire 103b and polysilicon wire 103d that connects memory cell M1.
Use such photomask 200 to implement photoetching, conductive film figure 31a is implemented composition.At this moment, on the first type surface of formed Semiconductor substrate 13, formed peristome 31c～31f.Therefore, even use 200 couples of conducting film 31a of aforesaid photomask to implement composition, also can isolate by the dielectric film 44 that on the internal face of peristome 31c～31f, forms.For example, isolate by the dielectric film on the inner peripheral surface that is formed on peristome 31c 44 between the polysilicon wire 103b of the polysilicon wire 103b of memory cell M1 and memory cell M2.In addition, also isolate between polysilicon wire 103a and the polysilicon wire 103c by the dielectric film on the inner peripheral surface that is formed on peristome 31d 44.And, also isolate between polysilicon wire 103b and the polysilicon wire 103d by the dielectric film on the inner peripheral surface that is formed on peristome 31e 44.And, the polysilicon wire 103c of memory cell M1 and and the polysilicon wire 103c of memory cell M1 adjacent memory unit between also isolate by the dielectric film 44 that is formed on the peristome 31c inner peripheral surface.
Like this, the borderline region between each polysilicon wire 103a～103d forms peristome 31c～31f in advance, forms dielectric film 44 on the internal face of this peristome 31c～31f, thus, can cut apart each polysilicon wire 103a～103f naturally.Therefore, when conductive film figure 31a is implemented photoetching, can implement composition in the mode that is connected between each adjacent on long axis direction polysilicon wire 103a～103d.
Herein, the width of the short-axis direction of peristome 31c (bearing of trend of polysilicon wire 103a～103d) for example is made into 100nm～120nm.And the edge of opening portion of peristome 31c and the distance between the 102a of active region for example can be made into about 50nm.
Therefore, the distance between the active region 102a of the active region 102a of memory cell M1 and memory cell M2 can be made into about 200nm～220nm.
On the other hand, under the state that does not form peristome 31c～31f, when polysilicon wire 103a～103d is carried out composition, at first, need to consider that the formation of formed polysilicon wire 103a～103d is bad, guarantee the tolerance limit between each polysilicon wire 103a～103d, for example, the distance between each polysilicon wire 103a～103d need be made into for example about 120nm.And, consider the mask skew or form tolerance limits such as bad that distance between the 102a～102d of active region need be guaranteed for example about 100nm.Therefore, for example the distance between the active region 102a of the active region 102a of memory cell M1 and memory cell M2 for example is about 300nm～320nm.
Particularly, under the peristome 31c and be positioned on the first type surface of Semiconductor substrate 13 of peristome 31c both sides and be made into the P well area, and be made into the well area of identical conduction type.Therefore, the distance between the active region 102a of the active region 102a of memory cell M1 and memory cell M2 is decided by the distance between the polysilicon wire 103b fully.
Therefore,, can reduce the distance between the 102a of active region reliably by reducing the distance between the polysilicon wire 103b, very big to the microminiaturization contribution of conductor integrated circuit device 10.Like this, the manufacture method according to the conductor integrated circuit device 10 of present embodiment 4 can reduce the distance between the transistorized polysilicon wire of each SRAM, realizes the microminiaturization of conductor integrated circuit device 10.In addition, in present embodiment 4, the situation of the SRAM that the ram region 62 that is applied at semiconductor integrated circuit 10 is formed is illustrated, and still, is not limited to be applied to such situation of carrying microcomputer of mixing.And, be not limited to be applied in the situation of SRAM, also applicable under the situation that forms a plurality of grids, and can reduce distance between each grid.
Use Figure 34 to Figure 79 the variation of present embodiment 4 to be described to Figure 37 and Figure 67.Figure 67 is the plane graph of peripheral circuit region of conductor integrated circuit device 10 of the variation of present embodiment 4, and Figure 68 is the profile of the LXV111-LXVIII line of described Figure 67.Shown in this Figure 67, on the first type surface of the Semiconductor substrate 13 at peripheral circuit region place, form: the grid of Yan Shening (wiring) 42a, 42b facing one direction; And grid (wiring) 42c, it is positioned at the end side of this grid 42a, 42b, and extends on the direction that the direction with this grid 42a, 42b extension intersects.
The borderline region of grid 42a, 42b and grid 42c is formed on the area of isolation 52, and this area of isolation 52 is formed on the first type surface of Semiconductor substrate 13.And, shown in Figure 68, on the upper surface of active region 53, form grid 42b, and the part of grid 42b reaches on the area of isolation 52 via dielectric film 54.In the side of the end face of this grid 42b, grid 42c with the opposed part of grid 42b and be positioned at this grid 42b and the surface of the area of isolation 52 of grid 42c boundary member on form the dielectric film 44 that for example constitutes by the ONO film.Therefore, guarantee isolation between grid 42b and the grid 42c.And, on the end face of grid 42b, form the conducting film 45 of side wall shape via dielectric film 44, and, via dielectric film 44 the side face of grid 42c, with the opposed side face of grid 42b on also form the conducting film 45 of side wall shape.
Figure 69 is the plane graph of the 1st manufacturing step of the conductor integrated circuit device 10 of this variation of expression, is the corresponding step of the 1st manufacturing step with the conductor integrated circuit device 10 of the described execution mode 1 shown in described Fig. 6, Fig. 7.Figure 70 is the profile of described Figure 69.
Shown in this Figure 69 and Figure 70, on the first type surface of Semiconductor substrate 13, optionally form area of isolation 52, and regulation active region 53.
Figure 71 is the plane graph of the manufacturing step behind the manufacturing step of expression shown in described Figure 69, is the corresponding plane graph of the 2nd step with the conductor integrated circuit device 10 of the described execution mode 1 shown in described Fig. 8, Fig. 9.And Figure 72 is the profile of Figure 71.
Shown in this Figure 71 and Figure 72, on the first type surface of Semiconductor substrate 13, form dielectric film 54, deposition (formation) conducting film 31 on the upper surface of this dielectric film 54.
Figure 34, Figure 73 are the plane graphs of peripheral circuit region in the pattern step of conducting film 31a of conductor integrated circuit device 10, and Figure 74 is the profile of Figure 73.Shown in this Figure 34, Figure 73, Figure 74, in the pattern step of conducting film, form conductive film figure 31a, this conductive film figure 31a has peristome 80 on the zone of the borderline region 83 of the adjacent grid that forms formed peripheral circuit transistor.
Figure 75 is the profile of the manufacturing step behind the manufacturing step of the conductor integrated circuit device 10 of expression shown in described Figure 74, is the profile with the corresponding step of the 5th step of the conductor integrated circuit device 10 of the described execution mode 1 shown in described Figure 14, Figure 15.Shown in this Figure 75, on the surface of the surface of peristome 80 and conductive film figure 31a, form dielectric film 33.And, depositing electrically conductive film 34 on the upper surface of this dielectric film 33.And, in the 5th step that forms storage grid 45, on the surface of the dielectric film 44 that is formed at peristome 80 surfaces, form conducting film 34.Figure 35, Figure 76 are the plane graphs that forms the peripheral circuit region of the 7th step of controlling grid and grid.Figure 77 is the profile of Figure 76, and Figure 36 is the plane graph of the peripheral circuit region of photomask 72.Shown in Figure 35, Figure 76, Figure 77, in the 7th step of conductor integrated circuit device 10, on the surface of peristome 80, form dielectric film 44, form conducting film 34 on the surface of peristome 80 inboards in the surface of dielectric film.
Like this, at the upper surface side configuration etching mask 72 shown in Figure 36 of the peristome 80 that is formed with dielectric film 44, conducting film 34, implement composition by photoetching.In addition, Figure 37 is the plane graph of the outer peripheral areas when forming the grid of peripheral circuit region.As shown in figure 36, on etching mask 72, form peristome 81.
In Figure 37, this peristome 81 forms as follows: formed grid 42a, 42b, 42c are connected in area of isolation shown in Figure 35 83 respectively.And, the peristome 81 of configuration etching mask 72 as shown in Figure 36 on the zone of the upper surface side of conductive pattern 31a, formed grid 42a, 42b, 42c.Like this, during configuration etching mask 72, part in the peristome 81, area of isolation 83 is positioned on the upper surface of peristome shown in Figure 35 80.
Figure 78 is the plane graph of the manufacturing step behind the manufacturing step shown in the described Figure 76 of expression, and Figure 79 is the profile of this Figure 78.Among these Figure 78, Figure 79, Figure 37, configuration etching mask 72 is when implementing composition by photoetching, by peristome shown in Figure 35 80 difference isolated gate 42a, 42b, 42c.That is, form adjacent grid 42a, 42b, 42c respectively in the both sides of peristome 80., on the surface of peristome 80, form dielectric film 44 herein, so, form dielectric film 44 on the surface of area of isolation 83 sides of formed grid 42a, 42b, 42c, on surfaces this dielectric film 44, area of isolation 83 sides, form conducting film 34.Like this, on the surface of area of isolation 83 sides of formed grid 42a, 42b, 42c, form dielectric film 44, so each grid 42a, 42b, 42c are isolated by electricity.
Like this, in forming the 7th step of grid, form peristome 80 on the part of area of isolation 83 in conductive pattern 31a, grid 42a, 42b, 42c in advance, on the surface of this peristome 80, formed dielectric film 44.Therefore, the peristome 82 that is formed on the etching mask 72 need not form in the mode of isolating formed grid 42a, 42b, 42c respectively, can form with ways of connecting in area of isolation 83.Like this, because can implement photoetching in the mode that connects grid 42a, 42b, 42c, thus different with the situation that forms segregate grid by photoetching, need between grid 42a, 42b, 42c, tolerance limit be set.Like this, the manufacture method according to the conductor integrated circuit device 10 of present embodiment 4 can make the interval of grid 42a, 42b, 42c approaching, and can realize dwindling of area.
And present embodiment 4 is applicable to the transistorized grid of peripheral circuit, still, is not limited to this, also can be applicable between the control grid or various wiring of memory cell transistor.That is, be manufacture method: on the first type surface of Semiconductor substrate, form conducting film with conductor integrated circuit device of following steps; Form conductive pattern, form peristome on this conductive pattern area of isolation in this conducting film, formed wiring; Form dielectric film in the mode that covers this conductive pattern; Use etching mask that described dielectric film and conductive pattern are implemented composition, form wiring, this etching mask has the peristome that forms to connect the mode of formed wiring at area of isolation.According to the manufacture method of such conductor integrated circuit device, compare with the situation that forms wiring by common photoetching process, shorten between wiring, and can reduce area.
The present invention is fit to be equipped with MONOS, and (Metal Oxide Nitride Oxide Silicon: the burning silicon oxynitride) mixing of the flash memory of structure carried microcomputer.
More than embodiments of the present invention are illustrated, still, should think that disclosed execution mode is an example, not by this restriction.Scope of the present invention represented by the scope of claim, comprise be equal to mutually with the scope of claim and scope in all changes.
Claims (8)
1. the manufacture method of a semiconductor storage, this semiconductor storage has: forms the memory cell region of memory cell transistor and forms the peripheral circuit region of the peripheral circuit of the action control of carrying out described memory cell transistor, comprising following steps:
On the first type surface of Semiconductor substrate, optionally form area of isolation, and the regulation active region;
On described active region, form the 1st dielectric film;
Form described the 1st conducting film in described memory cell region;
In described memory cell region, described the 1st conducting film is carried out composition, form conductive film figure, in this conductive film figure, on the zone that becomes the 1st extrinsic region that can play the source region effect, have peristome;
The described conductive film figure of described memory cell region as mask, is introduced impurity to the first type surface of described Semiconductor substrate;
Cover described conductive film figure, form by film formed the 2nd dielectric film that can accumulate electric charge of the 1st silicon oxide layer, silicon nitride film and the 2nd silicon oxidation;
On described the 2nd dielectric film, form the 2nd conducting film;
In described memory cell region, described the 2nd conducting film is carried out etching, in the side of the peristome of described conductive film figure, form the storage grid of the side wall shape of two described memory cell transistors simultaneously;
In described memory cell region, described conductive film figure and described two storage grids as mask, are formed described the 1st extrinsic region;
In described memory cell region, the zone at the 2nd extrinsic region place that can play the drain region effect in the described conductive film figure is carried out etching and carried out composition, simultaneously, the transistorized grid that is formed on the described peripheral circuit region is formed; And
The first type surface of described Semiconductor substrate is introduced impurity, form described the 2nd extrinsic region of described memory cell transistor and be formed on transistorized source region and drain region on the described peripheral circuit region.
2. as the manufacture method of the semiconductor storage of claim 1 record, wherein
Described the 1st conducting film is carried out the step that composition forms described conductive film figure to be comprised: the step of the residual portion of residual described the 1st conducting film on the zone of described the 1st extrinsic region that forms described memory cell transistor,
The formation step of described the 2nd dielectric film comprises the step that forms described the 2nd dielectric film in the mode that covers described residual portion,
Forming described storage grid step comprises: form connecting portion around described residual portion, this connecting portion is the connecting portion that the described storage grid with arranged opposite connects as one,
Also has the step that on described connecting portion, forms contact site.
3. the manufacture method of a semiconductor storage, this semiconductor storage has: forms the memory cell region of memory cell transistor and forms the peripheral circuit region of the peripheral circuit of the action control of carrying out described memory cell transistor, comprising following steps:
On the first type surface of Semiconductor substrate, optionally form area of isolation, and the regulation active region;
On described active region, form the 1st dielectric film;
On described the 1st dielectric film, form the 1st conducting film;
In described memory cell region, described the 1st conducting film is implemented composition, on the zone that forms the 1st extrinsic region that can play the source region function, have peristome, and, at the both ends side of the length direction of described peristome etching recess simultaneously;
In described memory cell region, described conductive film figure as mask, is introduced impurity to the first type surface of described Semiconductor substrate;
Cover described conductive film figure, form by film formed the 2nd dielectric film of accumulating electric charge of the 1st silicon oxide layer, silicon nitride film and the 2nd silicon oxidation;
On described the 2nd dielectric film, form the 2nd conducting film;
In described memory cell region, described the 2nd conducting film is implemented etching, in the side of the peristome of described conductive film figure, form the storage grid of the side wall shape of two memory cell transistors simultaneously;
In described memory cell region, described conductive film figure and two storage grids as mask, are formed the 1st extrinsic region;
In described memory cell region, etching is carried out in zone in the described conductive film figure, that can play the 2nd extrinsic region place of drain region effect, form the control grid that surrounds described the 1st extrinsic region ring-type on every side; And
On the first type surface of described Semiconductor substrate, introduce impurity, form described the 2nd extrinsic region,
The 1st storage grid of described two memory cell transistors and the 2nd storage grid are wired for connection to the end of memory cell region.
4. as the manufacture method of the semiconductor storage of claim 3 record, wherein
The step that forms the 2nd conducting film on described the 2nd dielectric film also comprises the steps: to fill described the 2nd conducting film in described recess, forms welding disk thus, and this welding disk is connected with the voltage application portion that can apply voltage to described storage grid.
5. as the manufacture method of the semiconductor storage of claim 3 record, wherein
Also has the step that on the upper surface of described control grid, forms silicide film.
6. as the manufacture method of the semiconductor storage of claim 3 record, wherein
When forming the control grid that surrounds described the 1st extrinsic region ring-type on every side, the transistorized grid that is formed on the described peripheral circuit region is formed.
7. semiconductor storage, wherein
Comprise:
Semiconductor substrate;
The area of isolation that on the first type surface of described Semiconductor substrate, optionally forms;
By described area of isolation regulation, via this area of isolation adjacent the 1st memory cell region that forms memory cell transistor and the 2nd memory cell region;
Be formed on described the 1st memory cell region and can play the 1st extrinsic region of source region effect;
Be formed on described the 1st memory cell region and can play the 2nd extrinsic region of drain region effect;
Be formed on described the 2nd memory cell region and can play the 3rd extrinsic region of source region effect;
Be formed on described the 2nd memory cell region and can play the 4th extrinsic region of drain region effect;
Be formed on the 1st channel region between described the 1st extrinsic region and described the 2nd extrinsic region;
Be formed on the 2nd channel region between described the 3rd extrinsic region and described the 4th extrinsic region;
The 1st control grid is formed on the described first type surface via the 1st dielectric film, and this first type surface is a first type surface in the first type surface of described Semiconductor substrate at described the 1st channel region place, that be positioned at described the 2nd extrinsic region side;
Be formed on the 1st storage grid of the side wall shape of the described memory cell transistor on the described first type surface via the 2nd dielectric film that can accumulate electric charge, this first type surface is a first type surface in the first type surface of described Semiconductor substrate at described the 1st channel region place, that be positioned at described the 1st extrinsic region side;
The 2nd control grid is formed on the described first type surface via the 3rd dielectric film, and this first type surface is a first type surface in the first type surface of described Semiconductor substrate at described the 2nd channel region place, that be positioned at described the 4th extrinsic region side;
Be formed on the 2nd storage grid of the side wall shape of the described memory cell transistor on the described first type surface via the 4th dielectric film that can accumulate electric charge, this first type surface is a first type surface in the first type surface of described Semiconductor substrate at described the 2nd channel region place, that be positioned at described the 3rd extrinsic region side;
The 1st connecting portion, be formed on the described area of isolation between described the 1st memory cell region and described the 2nd memory cell region, be connected to form at described the 1st storage grid on described the 1st memory cell region and described the 2nd storage grid that is formed on described the 2nd zone; And
The 2nd connecting portion is formed between described the 1st connecting portion,
Described the 2nd connecting portion comprises the 1st conducting film and is formed on described the 1st conducting film the 2nd conducting film on every side via the 5th dielectric film.
8. semiconductor storage, comprising:
Semiconductor substrate;
The area of isolation that on the first type surface of described Semiconductor substrate, optionally forms;
The active region of on the first type surface of described Semiconductor substrate, stipulating by described area of isolation;
Be formed on the described active region and can play the 1st extrinsic region of source region effect;
Be formed on the described active region and can play the 2nd extrinsic region of drain region effect;
Be formed on the channel region on the first type surface of the described Semiconductor substrate between described the 1st extrinsic region and the 2nd extrinsic region;
The control grid of ring-type is formed on via the 1st dielectric film on the upper surface in the upper surface of described channel region, described the 2nd extrinsic region side;
Recess is formed on the side of the described control grid that is positioned at described the 1st extrinsic region side;
The storage grid of the side wall shape of ring-type is formed on via the 2nd dielectric film that can accumulate electric charge on the upper surface in the upper surface of described channel region, described the 1st extrinsic region side, and is formed on the side of described control grid;
Connecting portion is connected with described storage grid, and is formed in the described recess; And
Voltage application portion is connected with described connecting portion, and can apply voltage to described storage grid.
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| JP2017045947A (en) * | 2015-08-28 | 2017-03-02 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method for semiconductor device |
| JP2021150600A (en) * | 2020-03-23 | 2021-09-27 | キオクシア株式会社 | Semiconductor storage device |
| CN112563277A (en) * | 2020-11-13 | 2021-03-26 | 上海华力微电子有限公司 | NOR flash unit structure and manufacturing method thereof |
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| CN100565843C (en) | 2009-12-02 |
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