JP2021150600A - Semiconductor storage device - Google Patents

Abstract

To provide a semiconductor storage device in which the potential difference is relieved between transistor array regions with different operation timings and application voltages.SOLUTION: A semiconductor storage device according to one embodiment includes a substrate, a first impurity region, a second impurity region, a first transistor, a third impurity region, a fourth impurity region, a second transistor, and an active region. The first impurity region, the second impurity region, the third impurity region, the fourth impurity region, and the active region with a first conductivity type are provided on the substrate. The first impurity region and the second impurity region are apart in a first direction. The first transistor includes a first electrode between the first impurity region and the second impurity region. The third impurity region is apart from the first impurity region in a second direction. The fourth impurity region is apart from the third impurity region in the first direction. The second transistor includes a second electrode between the third impurity region and the fourth impurity region. The active region is provided between the first transistor and the second transistor.SELECTED DRAWING: Figure 5

Description

Embodiments of the present invention relate to semiconductor storage devices.

A semiconductor storage device including a plurality of memory blocks including memory cells and a block selection circuit that selects and operates a predetermined memory cell block is known. In the block selection circuit, there is a problem that a high potential difference is generated between transistor array regions having different operation timings or applied voltages, and withstand voltage failure is likely to occur.

Japanese Unexamined Patent Publication No. 2016-171243

An object to be solved by the present invention is to provide a semiconductor storage device having a structure for relaxing a potential difference between transistor array regions having different operation timings or applied voltages.

The semiconductor storage device of the embodiment has a substrate, a first impurity region, a second impurity region, a first transistor, a third impurity region, a fourth impurity region, a second transistor, and an active region. .. The first impurity region is provided on the substrate and has a first conductive type. The second impurity region is provided on the substrate, is located away from the first impurity region in the first direction, and has the first conductive type. The first transistor includes a first electrode provided on the surface of the substrate between the first impurity region and the second impurity region. The third impurity region is provided on the substrate, is located apart from the first impurity region in the second direction intersecting the first direction, and has a first conductive type. The fourth impurity region is provided on the substrate, is located away from the third impurity region in the first direction, and has the first conductive type. The second transistor includes a second electrode provided on the surface of the substrate between the third impurity region and the fourth impurity region. The active region is provided between the first transistor and the second transistor, and has a first conductive type.

The equivalent circuit diagram which shows the typical structure of the semiconductor storage device which concerns on embodiment. Schematic plan view of the semiconductor storage device. (A) A schematic cross-sectional view of the semiconductor storage device when the structure shown in FIG. 2 is cut along the AA'line and viewed in the direction of the arrow. (B) A partially enlarged view of a cross section of the semiconductor storage device shown in (a). A schematic cross-sectional view of the semiconductor storage device when the structure shown in FIG. 2 is cut along the BB'line and viewed in the direction of the arrow. FIG. 5 is an equivalent circuit diagram showing a schematic configuration of a block selection circuit constituting the semiconductor storage device of FIG. 1. (A), (b) is a cross-sectional view showing a schematic configuration of a part of the block selection circuit of FIG. (A) An enlarged view of the active region in the semiconductor storage device, and (b) a diagram showing a modified example of the active region. The figure which shows one configuration example of the control circuit connected to an active region. The figure which shows the other configuration example of the control circuit connected to the active region.

Hereinafter, the semiconductor storage device of the embodiment will be described with reference to the drawings.

(First Embodiment)
[overall structure]
Hereinafter, the configuration of the semiconductor storage device according to the first embodiment will be described with reference to the drawings. The following drawings are schematic, and some configurations may be omitted for convenience of explanation.

FIG. 1 is a schematic equivalent circuit diagram showing the configuration of the semiconductor storage device 10 according to the first embodiment.

The semiconductor storage device 10 according to the present embodiment includes a memory cell array MA and a peripheral circuit PC that controls the memory cell array MA.

The memory cell array MA includes a plurality of memory blocks MB. These plurality of memory block MBs include a plurality of memory units MU. One end of each of the plurality of memory units MU is connected to the peripheral circuit PC via the bit line BL. Further, the other ends of the plurality of memory units MU are each connected to the peripheral circuit PC via a common source line SL.

The memory unit MU includes a drain selection transistor STD, a memory string MS, and a source selection transistor STS connected in series between the bit line BL and the source line SL. Hereinafter, the drain selection transistor STD and the source selection transistor STS may be simply referred to as selection transistors (STD, STS).

The memory string MS includes a plurality of memory cells MC connected in series. The memory cell MC according to the present embodiment is a field-effect transistor having a charge storage film in the gate insulating film. The threshold voltage of the memory cell MC changes according to the amount of charge in the charge storage film. A word line WL is connected to each of the gate electrodes of the plurality of memory cells MC corresponding to one memory string MS.

The selection transistor (STD, STS) is a field effect transistor. Selected gate wires (SGD, SGS) are connected to the gate electrodes of the selective transistors (STD, STS), respectively. The drain selection line SGD is provided corresponding to the memory finger MF and is commonly connected to all the memory unit MUs in one memory finger MF. The source selection line SGS is commonly connected to all memory unit MUs in one memory block MB.

The peripheral circuit PC includes an operating voltage generation circuit 21 that generates an operating voltage, an address decoder 22 that decodes the address data, a block selection circuit 23 that transfers the operating voltage to the memory cell array MA according to the output signal of the address decoder 22, and the block selection circuit 23. It includes a voltage selection circuit (hereinafter referred to as a control circuit) 24, a sense amplifier 25 connected to the bit line BL, and a sequencer 26 for controlling these.

The operating voltage generation circuit 21 includes a plurality of operating voltage output terminals 31. The operating voltage generation circuit 21 includes, for example, a step-up circuit such as a step-down circuit and a charge pump circuit. The operating voltage generation circuit 21 performs, for example, a bit line BL, a source line SL, a word line WL, and a selection gate line (SGD,) in a read operation, a write operation, and an erase operation with respect to the memory cell array MA according to a control signal from the sequencer 26. A plurality of operating voltages applied to SGS) are generated and output to a plurality of operating voltage output terminals 31 at the same time. Operating voltage The operating voltage output from the output terminal 31 is appropriately adjusted according to the control signal from the sequencer 26.

The operating voltage generation circuit 21 generates a read voltage and a read path voltage as operating voltages during the read operation. The read voltage is a voltage used to discriminate the data stored in the selected memory cell MC. When the read voltage is applied to the word line WL, a part of the plurality of memory cell MCs connected to the read voltage is turned ON, and the other memory cell MCs are turned OFF. The read path voltage is a voltage for turning on the memory cell MC, and is larger than the read voltage. When the read path voltage is applied to the word line WL, all of the plurality of memory cell MCs connected to the word line WL are turned on.

Further, the operating voltage generation circuit 21 generates a writing path voltage and a program voltage as operating voltages during the writing operation. The write path voltage is a voltage for turning on the memory cell MC, and has a magnitude equal to or larger than the read voltage. When the write path voltage is applied to the word line WL, all of the plurality of memory cell MCs connected to the word line WL are turned on. The program voltage is a voltage for accumulating charges in the charge storage film of the memory cell MC, and is larger than the write path voltage. When the write path voltage is applied to the word line WL, electrons are accumulated in some of the charge storage films of the plurality of memory cells MC.

The address decoder 22 includes a plurality of block selection lines BLKSEL and a plurality of voltage selection lines 33. For example, the address decoder 22 sequentially refers to the address data of the address register according to the control signal from the sequencer 26, decodes the address data, and turns on the predetermined block selection transistor 35 and the voltage selection transistor 37 corresponding to the address data. The other block selection transistors 35 and voltage selection transistors 37 are turned off. For example, the voltage of the predetermined block selection line BLKSEL and the voltage selection line 33 is set to the "H" state, and the other voltages are set to the "L" state. When a P-channel type transistor is used instead of an N-channel type transistor, a reverse voltage is applied to these wirings.

In the illustrated example, the address decoder 22 is provided with one block selection line BLKSEL for each memory block MB. However, this configuration can be changed as appropriate. For example, one block selection line BLKSEL may be provided for each of two or more memory block MBs.

The block selection circuit 23 includes a plurality of block selection units 34 corresponding to the memory block MB. Each of the plurality of block selection units 34 includes a plurality of block selection transistors 35 corresponding to the word line WL and the selection gate line (SGD, SGS). The block selection transistor 35 is, for example, a field effect type withstand voltage transistor. The drain electrode of the block selection transistor 35 is electrically connected to the corresponding word line WL or selection gate line (SGD, SGS), respectively. The source electrodes are electrically connected to the operating voltage output terminal 31 via the wiring CG and the voltage selection circuit 24, respectively. The gate electrode is commonly connected to the corresponding block selection line BLKSEL.

In the illustrated example, the block selection circuit 23 is provided with one block selection transistor 35 for each word line WL, and one block selection transistor 35 for each selection gate line (SGD, SGS). It is provided. However, this configuration can be changed as appropriate. For example, two block selection transistors 35 may be provided for each selection gate line (SGD, SGS).

The voltage selection circuit 24 includes a plurality of first voltage selection units 36 corresponding to the word line WL and the selection gate line (SGD, SGS). Each of the plurality of first voltage selection units 36 includes a plurality of voltage selection transistors 37. The voltage selection transistor 37 is, for example, a field effect type withstand voltage transistor. The drain terminal of the voltage selection transistor 37 is electrically connected to the corresponding word line WL or selection gate line (SGD, SGS) via the wiring CG and the block selection circuit 23, respectively. Each source terminal is electrically connected to the corresponding operating voltage output terminal 31. Each gate electrode is connected to the corresponding voltage selection line 33.

The sense amplifier 25 is connected to a plurality of bit lines BL. The sense amplifier 25 includes, for example, a plurality of sense amplifier units corresponding to the bit line BL. The sense amplifier unit has a clamp transistor that charges the bit line BL based on the voltage generated in the operating voltage generation circuit 21, a sense circuit that senses the voltage or current of the bit line BL, and an output signal of the sense circuit. It is provided with a plurality of latches for holding, write data, verify path flags, etc., and a logic circuit. The logic circuit identifies the data held in the memory cell MC by referring to the data on the lower page held in the latch, for example, during the read operation. Further, for example, in the writing operation, the voltage of the bit line BL is controlled by referring to the data on the lower page held in the latch.

The sequencer 26 outputs a control signal to the operating voltage generation circuit 21, the address decoder 22, and the sense amplifier 25 according to the input instruction and the state of the semiconductor storage device. For example, the sequencer 26 sequentially refers to the command data of the command register according to the clock signal, decodes the command data, and outputs the command data to the operating voltage generation circuit 21, the address decoder 22, and the sense amplifier 25.

Next, the configuration of the semiconductor storage device 10 according to the present embodiment will be described with reference to FIG. FIG. 2 is a schematic plan view of the semiconductor storage device 10 according to the present embodiment. Note that FIG. 2 shows a schematic configuration, and the specific configuration can be changed as appropriate. Further, in FIG. 2, some configurations are omitted.

As shown in FIG. 2, the semiconductor storage device 10 according to the present embodiment includes a semiconductor substrate 100. In the illustrated example, the semiconductor substrate 100 is provided with two memory cell array MAs arranged in the X direction. Further, a block selection circuit 23 and an address decoder 22 are provided in a region extending in the Y direction along both ends in the X direction of the memory cell array MA in order from the one closest to the memory cell array MA. Further, a sense amplifier 25 is provided in a region extending in the X direction along the end in the Y direction of the memory cell array MA. An operating voltage generation circuit 21 is provided in a region near both ends in the X direction of the region where the sense amplifier 25 is provided. A sequencer 26 is provided in an area outside these areas.

[Memory cell array MA]
Next, the configuration of the memory cell array MA will be described with reference to FIGS. 2 to 4. FIG. 3A is a schematic cross-sectional view when the semiconductor storage device 10 shown in FIG. 2 is cut along the AA'line and viewed in the direction of the arrow. FIG. 3B is an enlarged view of a part of the cross section of the semiconductor storage device shown in FIG. 3A. FIG. 4 is a schematic cross-sectional view when the semiconductor storage device 10 shown in FIG. 2 is cut along the BB'line and viewed in the direction of the arrow. It should be noted that FIGS. 2 to 4 show a schematic configuration, and the specific configuration can be changed as appropriate. Further, in FIGS. 2 to 4, some configurations are omitted.

As shown in FIG. 2, the memory cell array MA includes a plurality of memory block MBs arranged in the Y direction. The memory block MB has a plurality of memory trenches (not shown), a plurality of semiconductor columns 120, a plurality of select gate lines (not shown), and a plurality of word lines WL. The plurality of memory trenches are arranged at predetermined intervals in the Y direction. Each of the memory trenches is an insulating region and includes, for example, a silicon oxide layer. A word line WL is provided between the memory trenches adjacent to each other in the Y direction. The word lines WL adjacent to each other in the Y direction are separated by a memory trench.

In the memory block MB, as illustrated in FIG. 3, between the plurality of conductive layers 110 provided on the semiconductor substrate 100, the plurality of semiconductor columns 120, the plurality of conductive layers 110, and the plurality of semiconductor columns 120. Each of the plurality of gate insulating films 130 provided is provided.

The semiconductor substrate 100 is, for example, a semiconductor substrate such as single crystal silicon (Si) containing P-type impurities. An N-type well 101 containing N-type impurities such as phosphorus (P) is provided on a part of the surface of the semiconductor substrate 100. Further, a P-type well 102 containing a P-type impurity such as boron (B) is provided on a part of the surface of the N-type well 101. Further, an insulating region STI (FIG. 4) such as _{SiO 2} is provided on a part of the surface of the semiconductor substrate 100. Hereinafter, on the surface of the semiconductor substrate 100, a region in which the insulating region STI is not provided may be referred to as a semiconductor region.

The conductive layer 110 is a substantially plate-shaped conductive layer extending in the X direction, and a plurality of conductive layers 110 are arranged in the Z direction. The conductive layer 110 may contain, for example, a laminated film of titanium nitride (TiN) and tungsten (W), or may contain polycrystalline silicon or the like containing impurities such as phosphorus or boron. Further, an insulating layer 111 such as _{silicon oxide (SiO 2} ) is provided between the conductive layers 110.

Among the plurality of conductive layers 110, one or a plurality of conductive layers 110 located at the lowest layer function as gate electrodes of the source selection line SGS (FIG. 1) and the plurality of source selection transistors STS connected thereto. Further, the plurality of conductive layers 110 located above this function as gate electrodes of the word line WL (FIG. 1) and the plurality of memory cells MC (FIG. 1) connected thereto. Further, one or more conductive layers 110 located above this function as gate electrodes of the drain selection line SGD and the plurality of drain selection transistors STD (FIG. 1) connected to the drain selection line SGD.

A plurality of semiconductor columns 120 are arranged in the X direction and the Y direction. The semiconductor column 120 is, for example, a semiconductor film such as non-doped polycrystalline silicon (Si). As shown in FIG. 3A, the semiconductor column 120 has, for example, a substantially cylindrical shape, and an insulating film 121 such as silicon oxide is provided in the central portion thereof. Further, the outer peripheral surfaces of the semiconductor columns 120 are each surrounded by the conductive layer 110. The lower end of the semiconductor column 120 is connected to the P-type well 102 of the semiconductor substrate 100 via a semiconductor layer 122 such as non-doped single crystal silicon. The semiconductor layer 122 faces the conductive layer 110 via an insulating layer 123 such as silicon oxide. The upper end of the semiconductor column 120 is connected to the bit line BL via the semiconductor layer 124 containing N-type impurities such as phosphorus (P), contacts Ch and Cb. Each of the semiconductor columns 120 functions as a channel region of a plurality of memory cells MC and drain selection transistors STD included in one memory unit MU (FIG. 1). The semiconductor layer 122 functions as a channel region of the source selection transistor STS.

As shown in FIG. 3B, for example, the gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 laminated between the semiconductor column 120 and the conductive layer 110. The tunnel insulating film 131 and the block insulating film 133 are, for example, insulating films such as silicon oxide. The charge storage film 132 is, for example, a film capable of storing electric charges such as silicon nitride (SiN).

Although FIG. 3B shows an example in which the gate insulating film 130 includes a charge storage film 132 such as silicon nitride, the gate insulating film 130 is, for example, a polycrystal containing N-type or P-type impurities. A floating gate made of silicon or the like may be provided.

[Block selection circuit 23]
Next, a configuration example of the block selection circuit 23 according to the present embodiment will be described with reference to FIG. FIG. 5 is a schematic enlarged view of a part of the block selection circuit 23 constituting the semiconductor storage device of FIG. Note that FIG. 5 shows a schematic configuration, and the specific configuration can be changed as appropriate. Further, in FIG. 5, some configurations are omitted.

As illustrated in FIG. 4 and the like, in the present embodiment, a plurality of transistors are provided on the surface of the semiconductor substrate 100. Some of these plurality of transistors function as, for example, the block selection transistor 35 (FIG. 1) constituting the block selection circuit 23.

FIG. 5 is an equivalent circuit diagram showing a schematic configuration of the block selection circuit 23. The block selection circuit 23 is connected to each of four memory blocks (first memory block MB _C , second memory block MB _A , third memory block MB _D , and fourth memory block MB _B) that are operated at different timings. A plurality of transistor array regions C, A, D, and B are provided. Each of the transistor array regions A, B, C, and D has an array of a plurality of selection MOS transistors 35. Here, any transistor array is provided. region, in both the X and Y directions, and is configured so as to be adjacent to those that are connected to different memory blocks. for example, a transistor array region a, which is connected to the memory block MB _a is other memory blocks It is configured so that it is not adjacent to the transistor array region A connected to the MB _A.

Further, the block selection circuit 23 is used between the transistor array regions adjacent to each other in the X direction, specifically, between the transistor array region A and the transistor array region C, and between the transistor array region B and the transistor array region D. It has active regions AA1 and AA2, respectively.

6 (a) and 6 (b) are cross-sectional views showing a schematic configuration of a part of the block selection circuit 23 of FIG.

FIG. 6A is a cross-sectional view when the block selection circuit 23 is cut along the LL1 line. On one main surface 100A side of the substrate 100, a first impurity having a first conductive type (n type or p type) conductivity is injected into the transistor array region C, the active region AA1, and the transistor array region A. The case is illustrated. An insulating region STI is formed between the transistor array region C and the active region AA1 and between the active region AA1 and the transistor array region A. The entire substrate 100, or a part (well) surrounding each of the transistor array region C, the active region AA1, and the transistor array region A, has a second conductive type conductivity opposite to that of the first conductive type.

FIG. 6B is a cross-sectional view when the block selection circuit 23 is cut along the LL2 line. An example shows a case where the first impurity is injected into the active region AA1 on one main surface 100A side of the substrate 100. A contact (electrode) CS is formed on the active region AA1, and a gate electrode 140 is formed on the transistor array region C and the transistor array region A with a gate insulating film 150 interposed therebetween.

FIG. 7A is an enlarged view of the periphery (region surrounded by a broken line) of a part of the active regions AA1 and AA2 included in the block selection circuit 23 of FIG. Active regions AA1 and AA2 are provided between the two block selection transistors 35 (first transistor 35C, second transistor 35A). The concentration of impurities of the first conductive type provided in the active regions AA1 and AA2 becomes higher as it approaches the surface of the substrate 100.

The first transient 35C is provided on the substrate 100 and has a first impurity region D1 having a first conductive type, and is provided on the substrate 100 and is located apart from the first impurity region D1 in the first direction (Y direction). The second impurity region D2 having the first conductive type and the first electrode E1 provided on the substrate surface 100A between the first impurity region D1 and the second impurity region D2 are included.

The second transistor 35A is provided on the substrate 100, is located apart from the first impurity region D1 in the second direction (X direction) intersecting the first direction, and has a first conductive type with the third impurity region D3. , Between the fourth impurity region D4, the third impurity region D3, and the fourth impurity region D4, which are provided on the substrate 100 and are located apart from the third impurity region D3 in the first direction and have the first conductive type. The second electrode E2 provided on the substrate surface 100A is included.

The second impurity region D2, the fourth impurity region D4, and the active regions AA1 and AA2 are electrically connected to the control circuit 24 (FIG. 1).

The first impurity region D1 is electrically connected to the wiring provided in the first memory block MB _C. The third impurity region D3 is electrically connected to the wiring provided in _{the second memory block MB A.} Fifth impurity region D5 is electrically connected to the wiring provided in the third memory block MB _D. The sixth impurity region D6 is electrically connected to the wiring provided in _{the fourth memory block MB B.}

It is located on the substrate 100 and is located apart from the second impurity region D2 in the first direction, and is between the fifth impurity region D5 having one conductive type, the second impurity region D2, and the fifth impurity region D5. Further, a third transistor 35D including a third electrode D3 provided on the surface of the substrate 100 is further provided.

It is located on the substrate 100 and is located apart from the fourth impurity region D4 in the first direction, and is between the sixth impurity region D6 having one conductive type, the fourth impurity region D4, and the sixth impurity region D6. Further, a fourth transistor 35B including a fourth electrode D4 provided on the surface of the substrate 100 is further provided.

In the active regions AA1 and AA2, a contact CS connected to the control circuit 24 shown in FIG. 1 is formed on the surface of the semiconductor substrate 100. Of the surface of the semiconductor substrate 100, the portion in contact with the contact CS and the portion in the vicinity thereof (the portion surrounded by the broken line) have a higher impurity concentration than the other portions in order to reduce the electrical resistance. In the Y direction, the active region AA1 and the active region AA2 are separated from each other.

FIG. 7B is a diagram showing a modified example of the active regions AA1 and AA2 of FIG. 7A. Although the active regions arranged in the Y direction are separated from each other in FIGS. 5 and 7 (a), they may be connected to each other as shown in FIG. 7 (b). .. When the active regions are separated from each other, current leakage between the active regions can be suppressed. When the active regions are connected to each other, the number of wires connected to the control circuit 24 can be reduced.

In the active regions AA1 and AA2, at least a portion having a predetermined depth (a depth similar to that of the n-type well) from the surface of the semiconductor substrate 100 is the source / drain diffusion layer of the transistor array regions on both sides adjacent to each other in the X direction. , Have the same polarity (n-type or p-type). When a p-type semiconductor substrate is used and the transistor for selecting an adjacent transistor array region is a p-type MOS transistor as in the present embodiment, the active regions AA1 and AA2 are n-type wells like the p-type MOS transistor. Will be formed in. When the selection transistor in the adjacent transistor array region is an n-type MOS transistor, it is not necessary to form an n-type well.

Although not shown in FIG. 4, the potentials of the transistor array regions A, B, C, and D and the potentials of the active regions AA1 and AA2 in the block selection circuit 23 are controlled by the control circuit (voltage selection circuit) 24. ..

The control circuit 24 is preferably configured so that the potentials of the transistor array regions A, B, C, and D and the potentials of the active regions AA1 and AA2 can be controlled separately. That is, as shown in FIG. 1, in the control circuit 24, the first voltage selection unit 36 connected to the transistor array regions A, B, C, and D and the second voltage selection unit connected to the active regions AA1 and AA2. It is preferable that the parts 38 are circuits that are separate from each other and are electrically insulated from each other.

In the second voltage selection unit 38, when the voltage applied to one of the two adjacent transistor array regions is V ₁ and the voltage applied to the other is V ₂ , the voltage V applied to the active region is V ₁ ≤ V. It is preferably configured such that ≦ V _{2 and preferably V 1} <V <V ₂ . From the viewpoint of preventing the potential gradient from becoming steep between the transistor array regions, _{it is more preferable that the voltage V in the active region is close to (V 1} + V ₂ ) / 2, which is an intermediate voltage between _{V 1} and V _2. , (V ₁ + V ₂ ) / 2 is most preferable.

Specifically, the transistor array region A, B, C, the voltage applied to the D, when _{V A,} V _B, V C, and _{V D} respectively, the voltage V applied to the active region AA1 is, _{V A} ≦ V ≦ such that V _C or _{V C} ≦ V ≦ _{V a, preferably,} configured such that V a <V _{<V C} or _V C _{<V <V a.} Similarly, the voltage V applied to the active region AA2 is such that _{V B} ≦ V ≦ _{V D} or _{V D} ≦ V ≦ _{V B, preferably,} V B <V _{<V D} or _V D <V _{<V B} It is configured to be.

FIG. 8 is a diagram showing a configuration example 1 of the second voltage selection unit 38 connected to the active regions AA1 and AA2 of the block selection circuit 23. In this configuration example, two transistor array regions connected to different memory blocks form a plurality of rows CL alternately arranged in one direction (X direction), and a second voltage selection having a common active region for each row CL. It is connected to the unit 38. At least the same number of second voltage selection units 38 as the row CL are provided, and the active region belonging to one row CL is connected to one second voltage selection 38. Specifically, the two transistor array regions A and C form a plurality of rows CL1 (here, two rows) alternately arranged in one direction (X direction), and are connected to separate second voltage selection units 38 _AC . Will be done. Similarly, the two transistor array regions B and D are connected to _{separate second voltage selection units 38 BDs} that form a plurality of rows (here, two rows) of rows CL2 that are alternately arranged in one direction.

Further, for each column CL, a plurality of active regions to which it belongs are connected to a common second voltage selection unit 38. That is, the active region is connected to the second voltage selection unit 38, which is different for each column CL. In such a configuration, since the voltage applied to the active region can be controlled on a column-by-column basis, the second is provided in the control circuit 24 as compared with the case where the voltage is individually applied to each active region. The number of voltage selection units 38 can be reduced.

FIG. 9 is a diagram showing a configuration example 2 of the second voltage selection unit 38 connected to the active regions AA1 and AA2 of the block selection circuit 23. In the configuration example 2, the same columns CL1 and CL2 as in the configuration example 1 are formed, but the active region is common to each group G composed of a plurality of columns having the same combination of connected memory blocks. It is connected to the voltage selection unit 38. Active regions belonging to a plurality of columns CL are connected to one second voltage selection unit 38.

Specifically, in the group G1 composed of a plurality of columns CL1 in which the combination of the memory blocks to be connected is MB _A and MB _C , the active region AA1 is connected to the common second voltage selection unit 38. Similarly, in the group G2 composed of a plurality of columns CL2 in which the combination of the memory blocks to be connected is MB _B and MB _D , the active region AA2 is connected to the common second voltage selection unit 38. In such a configuration, since the voltage applied to the active region can be controlled in group units, the second voltage selection unit provided in the control circuit 24 is compared with the case where the voltage is individually applied to each row. The number of 38 can be reduced.

According to at least one embodiment described above, in the block selection circuit, by having an active region between two adjacent transistor array regions, a voltage different from this active region independently of the transistor array region is provided. Can be applied.

In semiconductor storage devices, design relaxation is performed to reduce the number of transistors per block in order to reduce the number of transistors and maintain the withstand voltage against write voltage and erase voltage at the same time. When the design is relaxed, the transistor array regions having different operation timings or applied voltages may be adjacent to each other. In this case, a high potential difference occurs between adjacent transistor array regions, but as described in the above embodiment, this potential difference is obtained by applying a voltage intermediate between the voltages applied to the two transistor array regions to the active region. Can be relaxed and the pressure resistance can be improved.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, as well as in the scope of the invention described in the claims and the equivalent scope thereof.

10 ... Semiconductor storage device, 21 ... Operating voltage generation circuit, 22 ... Address decoder,
23 ... block selection circuit, 24 ... voltage selection circuit (control circuit), 25 ... sense amplifier,
26 ... Sequencer, 31 ... Operating voltage output terminal, 33 ... Voltage selection line,
35 ... block selection transistor, 36 ... first voltage selection unit,
37 ... Voltage selection transistor, 38, 38 _{AC , 38 BD} ... Second voltage selection,
100 ... semiconductor substrate, 102P type well layer, 110 ... conductive layer, 111 ... insulating layer,
120 ... Semiconductor column, 122, 124 ... Semiconductor layer, 130 ... Gate insulating film,
131 ... Tunnel insulating film, 132 ... Charge storage film, 133 ... Block insulating film,
140 ... Gate electrode, A, B, C, D ... Transistor array region,
AA1, AA2 ... active region, BL ... bit line, BLKSEL ... block selection line, CG ... wiring,
CL, CL1, CL2 ... Column, CS ... Contact, MA ... Memory cell array,
MB ... memory block, MC ... memory cell, MF ... memory finger,
MS ... memory string, MU ... memory unit, PC ... peripheral circuit,
SGD, SGS ... Selective transistor, SL ... Source line,
STD ... drain selection transistor, STI ... isolated region, WL ... word line

Claims (12)

With the board
A first impurity region provided on the substrate and having a first conductive type,
A second impurity region provided on the substrate, located away from the first impurity region in the first direction, and having the first conductive type,
A first transistor between the first impurity region and the second impurity region, which includes a first electrode provided on the surface of the substrate.
A third impurity region provided on the substrate, located apart from the first impurity region in the second direction intersecting the first direction, and having a first conductive type,
A fourth impurity region provided on the substrate, located away from the third impurity region in the first direction, and having the first conductive type,
A second transistor between the third impurity region and the fourth impurity region, which includes a second electrode provided on the surface of the substrate.
A semiconductor storage device provided between the first transistor and the second transistor and including an active region having a first conductive type. The semiconductor storage device according to claim 1, further comprising a second impurity region, the fourth impurity region, and a control circuit electrically connected to the active region. The first aspect of claim 1, wherein the first impurity region is electrically connected to the wiring provided in the first memory block, and the third impurity region is electrically connected to the wiring provided in the second memory block. Semiconductor storage device. A fifth impurity region provided on the substrate, located away from the second impurity region in the first direction, and having the first conductive type,
The semiconductor storage device according to claim 1, further comprising a third transistor between the second impurity region and the fifth impurity region, which includes a third electrode provided on the surface of the substrate. Further including the second impurity region and a control circuit electrically connected to the active region.
The fourth aspect of claim 4, wherein the first impurity region is electrically connected to the wiring provided in the first memory block, and the fifth impurity region is electrically connected to the wiring provided in the third memory block. Semiconductor storage device. A sixth impurity region provided on the substrate, located away from the fourth impurity region in the first direction, and having the first conductive type,
The semiconductor storage device according to claim 4, further comprising a fourth transistor between the fourth impurity region and the sixth impurity region, which includes a fourth electrode provided on the surface of the substrate. The second impurity region, the fourth impurity region, and a control circuit electrically connected to the active region are further included.
The first impurity region is electrically connected to the wiring provided in the first memory block.
The third impurity region is electrically connected to the wiring provided in the second memory block.
The fifth impurity region is electrically connected to the wiring provided in the third memory block.
The semiconductor storage device according to claim 6, wherein the sixth impurity region is electrically connected to a wiring provided in the fourth memory block. The semiconductor storage device according to claim 1, wherein the concentration of impurities of the first conductive type provided in the active region becomes higher as it approaches the surface of the substrate. A plurality of transistor array regions having an array of multiple selection MOS transistors connected to a memory block,
An active region provided between adjacent transistor array regions and
With a block selection circuit equipped with
A control circuit for controlling the potential of the transistor array region and the potential of the active region is included.
A semiconductor storage device in which at least a portion of the active region connected to the control circuit has the same polarity as the diffusion layer of the selection MOS transistor. The semiconductor according to claim 9, wherein in the control circuit, a first voltage selection unit connected to the transistor array region and a second voltage selection unit connected to the active region are electrically insulated. Storage device. Two transistor array regions connected to different memory blocks form a plurality of rows alternately arranged in one direction.
The semiconductor storage device according to claim 10, wherein the active region is connected to the common second voltage selection unit for each column. The semiconductor storage device according to claim 11, wherein the active region is connected to a common second voltage selection unit for each group consisting of a plurality of the columns having the same combination of the memory blocks to be connected.

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