JPH11145433A - Semiconductor storage device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the access time of a flash memory. SOLUTION: Gate electrodes 56a and 58a, which are connected with block selecting transistors 56 and 58, are respectively constituted of the two electrodes 56a and 58a. Although the two gate electrodes 56a and the two gate electrodes 58a intersect at diffused layers 52 and 54, the one which functions as a transistor is only the one electrode 56a or 58a. Since the number of the transistors 56 or 58 connected with the one gate electrode 56a or 58a can be reduced to 1/2, the parasitic capacity between the gate electrodes and a semiconductor substrate can be lessened and a delay of gates can be lessened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device capable of electrically writing and erasing, and more particularly to a memory device capable of batch erasing. This storage device can be used alone or as an ASIC (Application Specific integrated
circuit), and a semiconductor chip such as a microcomputer chip which may contain a storage device.

[0002]

2. Description of the Related Art A flash memory is an EEPROM (El
By eliminating the single-bit erasing function of ectrically programmable erasable programmable ROM (ROM) and erasing the entire chip or large sector units, significant integration has been achieved. FIG.
U.S. Pat. No. 528 discloses one of the batch erasing type nonvolatile semiconductor memory devices by Yueh.Y.Ma.
No. 0446). (A) is a plan view, and (B) is a cross-sectional view at the XY position of (A). A common source diffusion layer 4 and a common drain diffusion layer 6 are formed on the silicon substrate 2 so as to face each other and are parallel to each other, and a floating gate 8 is formed on the substrate via a tunnel oxide film. The floating gate 8 partially overlaps with the drain diffusion layer 6 and forms the source diffusion layer 4.
And are arranged with a distance. A strip-shaped control gate 10 is formed on the floating gate 8 in parallel with the source diffusion layer 4 and the drain diffusion layer 6 via an insulating film. A strip-shaped selection gate 12 is formed on the control gate 10 in a direction orthogonal to the source diffusion layer 4 and the drain diffusion layer 6 via an insulating film. 14 is a LOCOS (Loca) for element isolation.
l Oxidation of Silicon), which separates the channels of memory cells adjacent to each other in the direction in which the control gate 10 extends.

By applying an appropriate voltage to the control gate 10 and the selection gate 12, high-efficiency carrier injection (source-side carrier injection) into the floating gate 8 is realized. In the source side carrier injection method, the injection efficiency is higher by one to three orders of magnitude than the carrier injection from the drain side by the conventional CHE (Channel Hot Electron) injection method. It is easy to implement and enables a single power supply. Another advantage of this method is that memory elements can be selected in a matrix by a control gate 10 and a selection gate 12 as shown in FIG. Since the source 4 and the drain 6 of adjacent memory elements can be shared, the size of the memory array can be extremely reduced. In addition, the structure having the selection gate 12 has an advantage that the current can be cut off even if excessive erasure occurs, so that confirmation of excessive erasure is not required.

[0004] A structure utilizing this advantage is the same as Yue.
disclosed by hYMa et al. A cross-sectional view of the structure is shown in FIG. 2 (see US Pat. No. 5,278,439). A strip-shaped n serving as a source or a drain is formed on a p-type silicon substrate 16.
A mold active region 18 is formed. On the substrate adjacent to each n-type active region 18 between two opposing n-type active regions 18, two floating gates 20 are formed with a gap therebetween via a tunnel oxide film. A strip-shaped control gate 22 is formed on the floating gate 20 in parallel with the n-type active region 18 via an insulating film. A strip-shaped selection gate 24 is formed on the control gate 22 in a direction orthogonal to the n-type active region 18 via an insulating film. The feature of this structure is
The two flash memories having the structure of FIG.
That is, a virtual ground array system in which the source diffusion layer and the drain diffusion layer are switched as needed is adopted. As a result, one source or drain line can be reduced, and the element can be formed small.

However, a flash memory having a large storage capacity has a large erasing size because of a common diffusion layer. Although this flash memory is functionally similar to an EEPROM, its use has been mainly for replacing a UV-EPROM of an ultraviolet erasing method. Flash memory that can be electrically programmed and erased can be erased and rewritten on-board.
In addition to ROM replacement applications, the use of EEPROM is expanding to fields where it is used. However, the bulk erasure has disadvantages. For example, when the program is debugged and re-written, the changed part is only a small part, but if it is erased all at once, all the data must be re-written, resulting in a time loss. is there. Further, if the configuration is such that data is stored, there is a problem that the time loss is multiplied many times. As the capacity of a flash memory increases, the junction capacitance and resistance of the source / drain diffusion layers become so large that they cannot be ignored, and it takes time to set the source / drain diffusion layers to a required voltage. As a result, the time loss due to the increase in capacity has neglected the advantage of speeding up by miniaturization.

In order to solve these problems, the memory is divided into blocks of a certain size, erasing can be performed in block units, and the access speed is ensured by dividing the source / drain diffusion layers of the memory. And the method has begun to be used. This block division method requires a selection circuit and a block selection transistor for selecting each memory block in the memory array. FIG.
FIG. 4A is a circuit diagram of a memory cell array including a block selection transistor, FIG. 4A is a plan view of the device in FIG. 3, and FIG. 4B is a cross-sectional view at the XY position in FIG. A plurality of split gate type memory cells having a floating gate, a control gate, and a selection gate are connected in parallel by memory diffusion layers 30 and 32 in a block, and share a source and a drain in a matrix. The memory array 42 is formed. The memory diffusion layers 30 and 32 are independently formed in each block, and the block selection transistors 26 and 2 are respectively formed.
8 are connected to the metal bit lines 34 and 36. The control gates of the elements in the block are connected to a common control gate line 38. The selection gate is a common word line 40 with elements arranged in a direction orthogonal to the memory diffusion layers 30 and 32. A strip-shaped gate electrode line 26 common to a plurality of block select transistors 26
a, a band-shaped gate electrode line 28a common to a plurality of block select transistors 28 is formed.

[0007]

As shown in FIGS. 3 and 4, the block select transistors 26 and 28 have a structure in which one strip-shaped gate electrode line 26a and 28a are connected to each other. , 28a and the semiconductor substrate, and the gate electrode lines 26a, 2a.
The gate delay occurs due to the resistance component of the 8a itself. This tendency is more problematic in the half-micron generation and thereafter, since the capacitance between the gate electrode line and the semiconductor substrate becomes large, since the gate oxide film is thin. Further, the large storage capacity of the flash memory means that the gate electrode line of the block select transistor also becomes long, and the influence of the gate delay cannot be ignored.

FIG. 5 is a graph showing the result of calculating the magnitude of the memory capacity and the magnitude of the gate delay. The X-axis is the distance from the power supply (expressed in the number of bits), and the Y-axis is the voltage rise time (second). Represents The distance from the power supply on the horizontal axis corresponds to the size of the memory array. It can be seen that as the size of the memory increases, it takes time for the voltage to rise, and the effect of the gate delay increases.

Accordingly, an object of the present invention is to reduce an increase in access time due to a gate delay of a block select transistor used in a semiconductor memory device such as a flash memory.

[0010]

In a semiconductor memory device according to the present invention, a memory diffusion layer serving as a source / drain region of a memory cell is formed on a semiconductor substrate in parallel and in a strip shape. A floating gate made of a first conductor is provided on a semiconductor substrate, adjacent to one memory diffusion layer and spaced from the other memory diffusion layer with a first insulating film interposed therebetween, and separated for each memory cell. And
A second second insulating film is formed on the floating gate and extends in a band shape in parallel with the memory diffusion layer.
A control gate made of a conductive material is formed on the semiconductor substrate between the floating gate and the memory diffusion layer, which is disposed at an interval between the control gate and the floating gate via a third insulator. A selection gate formed of a third conductor common to a plurality of memory cells extending in a band shape in a direction orthogonal to the second conductor via a fourth insulator, and a semiconductor below the floating gate is formed. The substrate surface is a memory channel,
In a semiconductor memory device including a memory matrix in which split gate type memory cells having a semiconductor substrate surface between a memory diffusion layer and a floating gate as a selection channel are arranged in a matrix, the memory matrix is a block including a plurality of memory cells. The memory diffusion layer is divided and formed so that the source and drain are independent for each block, and each memory diffusion layer extends in the direction of the memory diffusion layer via a block selection transistor. Connected to the metal bit line, and as a gate electrode for the block select transistor,
A plurality of gate electrode lines made of a strip-shaped fourth conductor are provided in a direction orthogonal to the memory diffusion layer direction;
In each block select transistor, only one of the gate electrode lines functions as a transistor, and a diffusion layer is continuously formed below the other gate electrode lines.
An insulating film thicker than the gate insulating film is formed between the diffusion layer and the gate electrode line. By providing a plurality of gate electrode lines for block select transistors, the number of block select transistors provided for each gate electrode line is reduced, and the parasitic capacitance of each gate electrode line is reduced.

A method for manufacturing a semiconductor memory device according to the present invention includes the following steps (A) to (D). (A) a step of forming an element isolation region in a semiconductor substrate;
(B) After the gate oxidation, the floating gate for each memory cell is arranged on the gate oxide film so that the length in the channel length direction is shorter than the source-drain interval and is arranged closer to the drain side. (C) forming a memory diffusion region that is independent for each block and a region in the block selection transistor formation region that does not function as a transistor; Implanting, (D) forming a select gate, and simultaneously forming a plurality of gate electrodes of a block select transistor for each block, (E) ion-implanting a source diffusion layer region and a drain diffusion layer region of the block select transistor region. Implantation, thermal oxidation to form a block select transistor, and at the same time, block with the gate electrode line An oxide film thicker than the gate oxide film is formed between the memory diffusion layer and a region below the gate electrode line in a region not functioning as a block selection transistor, which is an intersection of a memory diffusion region and a region connecting the region serving as a block selection transistor. The process to form. Since an oxide film thicker than the gate oxide film is formed between the gate electrode line and the memory diffusion layer in the region not functioning as the block selection transistor, the memory diffusion region and the block are formed within the block electrode and the gate electrode line. Insulation between the region connecting the regions to be the selection transistors can be ensured.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A gate electrode line is formed by a first gate electrode line made of a fourth conductor and a low-resistance metal film formed on the first gate electrode line via an interlayer insulating film. It is preferable that the first gate electrode line and the second gate electrode line are electrically connected by through holes. As a result, in addition to the reduction in the parasitic capacitance of the gate electrode line, the parasitic resistance component also decreases.

The first gate electrode line is not divided into one continuous band-shaped gate electrode line in the block, but is divided at least over the block select transistor, and the divided first gate electrode lines are respectively passed through. It is preferable to electrically connect to the second gate electrode line through the hole. As a result, the parasitic capacitance between the gate electrode line and the semiconductor substrate is further reduced.

It is preferable that the gate electrode of the block select transistor on the source side of the memory diffusion layer and the gate electrode of the block select transistor on the drain side are arranged on different lines. As a result, the gate width of the block selection transistor can be widened, and the amount of current can be increased.

[0015]

FIG. 6 shows an embodiment of the present invention. (A) is a plan view, (B) is a cross-sectional view at the AB position of (A), (C)
3A is a cross-sectional view at the XY position in FIG. Floating gate 6
1, a plurality of split gate type memory cells having a control gate 63 and a selection gate 66 are connected in parallel by memory diffusion layers 52 and 54 in a block, and a matrix is formed in such a manner that each source and drain are shared. Memory array 68 is formed. The memory diffusion layers 52 and 54 are independently formed in each block, and are connected to a metal bit line via a block selection transistor 56 for the source diffusion 52 and a block selection transistor 58 for the drain diffusion layer 54, respectively. I have. The control gates 63 of the elements in the blocks formed in a strip shape on the floating gate 61 are connected to a common control gate line 64 formed independently for each block. The band-shaped selection gate 66 is connected to the memory diffusion layers 52 and 54.
The elements arranged in a direction orthogonal to the above form a common word line 66. A common strip-shaped gate electrode 56a is formed by the plurality of block selection transistors 56, and a common strip-shaped gate electrode 58a is formed by the plurality of block selection transistors 58. Two gate electrodes 56 are provided on the diffusion layers 52 and 54.
Although a and 58a intersect, only the portion that intersects with one gate electrode 56a or 58a functions as a transistor. A speed-enhancing oxide film 56c or a speed-enhancing oxide film 58c is formed under the gate electrode 56a or 58a at the intersection that is not functioning.
2, 54 are connected to each other.

Since the number of gate electrodes of the block select transistors 56 and 58 is two, the number of the block select transistors 56 or 58 connected to one gate electrode 56a or 58a can be halved. With such a structure, the parasitic capacitance between the gate electrode and the semiconductor substrate can be reduced, and the gate delay can be reduced. Here, if the number of gate electrodes is further increased, the parasitic capacitance can be reduced, but on the other hand, the decoder circuit for controlling the gate electrodes becomes complicated, and the parasitic resistance of the diffusion layer of the block selection transistor increases. For this reason, it is preferable to use two gate electrodes.

FIG. 7 shows another embodiment of the gate electrode of the embodiment. 6A is the same as FIG. 6A, FIG. 6A is a cross-sectional view at the XY position in FIG. 6A, and FIG.
It is sectional drawing in the AB position of. Gate electrodes 56a, 5
Metal gate electrodes 56b and 58b made of, for example, a low-resistance metal are formed on 8a via an interlayer insulating film 70. The gate electrodes 56a, 58a and the metal gate electrodes 56b, 58b are connected via through holes 72, respectively. With this configuration, in addition to the effect of reducing the parasitic capacitance, the parasitic resistance component can be reduced, so that the gate delay can be further reduced. .

FIG. 8 shows still another embodiment of the gate electrode of the embodiment. The planar configuration is the same as that of FIG.
6A is a cross-sectional view at the XY position in FIG. 6A, and FIG. 6B is a cross-sectional view at the AB position in FIG. 6A. Gate electrodes 56d and 58d are block select transistors 56 and 58
It is cut at the part other than the part that works as a gate,
Metal gate electrodes 56b and 58b made of, for example, a low-resistance metal are formed on the gate electrodes 56d and 58d with an interlayer insulating film 74 interposed therebetween. Gate electrode 56
d, 58d and the metal gate electrodes 56b, 58b are connected via through holes 72, respectively. With this configuration, the parasitic capacitance with the semiconductor substrate can be reduced more than in the embodiment of FIG. 7, so that the gate delay can be further reduced.

FIG. 9 is a plan view showing another embodiment of the present invention.
The memory array 68 is similar to the embodiment of FIG. The block selection transistor 77 for the source diffusion layer 52 formed below the gate electrode 77a and the block selection transistor 79 for the drain diffusion layer 54 formed below the gate electrode 79a are not on one straight line but are shifted. Are located. The block selection transistor 77 has a gate electrode 77
a and the block selection transistor 7
Reference numeral 9 denotes a gate electrode 79a. With such a configuration, the block selection transistor 76,
The gate width of 78 can be widened, and a larger current amount can be secured. As a result, the effect of the gate delay can be reduced.

Here, the block select transistors 81 and 83 formed below the gate electrodes 81a and 83a are block select transistors of a block arranged below a block including the memory array 68 in the figure. The block selection transistors 85 and 87 formed below the gate electrodes 85a and 87a are block selection transistors of a block arranged above a block including the memory array 68 in the drawing. Further, in the configuration of the plan view of FIG.
It is preferable to have a structure having a gate electrode cross section of FIG. 9 or a structure having a gate electrode cross section of FIG. As a result, the gate delay can be further reduced.

Next, the manufacturing process of the present invention will be described with reference to FIGS.
I will explain using. (A) First, field oxidation is performed on a P-type silicon substrate to form a memory, a transistor, and an active region 70 serving as a diffusion layer and an element region 72 for separating the active region 70 from each other (FIG. 10). Next, arsenic is implanted into the region 74 where the polysilicon layer connecting the control gates in the active layer intersects by ion implantation.

(B) Next, a first thermal oxidation is performed on the entire surface to form an oxide film serving as a gate oxide film, and then a polysilicon film serving as a floating gate 61 is formed. After the polysilicon film is etched in a strip shape in the direction orthogonal to the bit lines, an inter-polysilicon insulating film is formed, and further a polysilicon film serving as the control gate 63 is formed. Further, the polysilicon film / interpolysilicon insulating film / polysilicon film is simultaneously etched in a strip shape in a direction parallel to the bit line, thereby forming the floating gate 61 and the control gate 63. At this time, the control gates 63 adjacent to each other with the drain interposed therebetween are etched so as to form electrically connected pairs and to connect the pairs alternately in the block (FIG. 1).
1).

(C) Next, a source 5 of the memory
2. Arsenic is implanted into the memory diffusion region of the portion 54 serving as the drain and the region 78 connecting the memory diffusion region and the region 76 serving as the block selection transistor by ion implantation (FIG. 12). At this time, in a region where the control gate line 64 exists on the region 78, the control gate line 64 serves as a mask, and arsenic is not implanted into the region 78. However, in this region, arsenic is implanted in advance as described above with reference to FIG.
The electrical connection between the memory diffusion layer and the block select transistor is maintained. Also, in this region, arsenic is implanted before the first thermal oxidation, so that a speed-up oxide film thicker than the gate oxide film is formed, so that electrical insulation between the diffusion layer and the control gate is ensured. it can.

(D) Next, after forming an oxide film side wall on the control gate side wall by self-alignment, gate oxidation is performed again on the entire surface of the wafer to form a polysilicon film. Next, the polysilicon film is patterned to form the selection gate 66 and the gate electrodes 77a and 79a of the block selection transistor (FIG. 13).

(E) Next, arsenic is implanted into the region 76 of the block select transistor (this step is also a source / drain implant for peripheral circuits) to form the source and drain of the block select transistor (FIG. 14). In a region 75 where a gate electrode of another block selection transistor crosses a diffusion region connecting the block selection transistor and the memory diffusion region, a source / drain diffusion layer of the memory is formed before the second thermal oxidation. Arsenic has been implanted. As a result, in the region 75, a speed-up oxide film thicker than the gate oxide film is formed between the polysilicon and the diffusion layer by the second gate oxidation, so that the electrical connection between the gate electrodes 56a and 58a and the memory diffusion layer is made. Insulation can be ensured, and the silicon substrate and the gate electrode 56
Since the distance between a and 58a is increased, the parasitic capacitance can be reduced.

(F) Next, a metal-polysilicon insulating film is formed on the entire surface, and a contact hole 80 is formed on the drain portion of the block select transistor, a contact hole 82 is formed on the select gate, a contact hole 84 is formed on the control gate, and the like.
A contact hole 86 is formed on the gate of the block select transistor (FIG. 15).

(G) Next, a metal layer made of an Al alloy is formed on the entire surface, and the metal layer is patterned. The metal layer is formed immediately above the selection gate at the same pitch as the selection gate and parallel to the selection gate. A strip-shaped metal pattern 88 is formed and connected to the contact hole 82. Further, a strip-shaped pattern 90 parallel to the word line direction is simultaneously formed by the metal layer and connected to the control gate via the contact hole 84. Further, a strip-shaped metal layer 92 is formed directly above the gate electrodes 56a, 58a of the block select transistor at the same pitch as the gate electrodes 56a, 58a and parallel to the gate electrodes 56a, 58a.
6 and is connected to the gate electrode of the block selection transistor. Thus, the gate electrode of the block select transistor can be backed with a low-resistance metal layer, and the resistance of the entire gate electrode can be reduced. (FIG. 16).
At this time, since the metal layer 88 is the lowest layer in the multilayer metal layer, the minimum processing size can be smaller than that of the upper metal layer. Therefore, the metal layer 88 having a stripe shape in a direction orthogonal to the bit line direction, which is a short direction of the memory.
However, processing can be performed at the same pitch as that of the memory.

(H) Next, a metal-metal insulating film is formed on the entire surface, and a through hole 94 is formed at the drain of the block select transistor (FIG. 17). The thickness of the metal-polysilicon insulating film at the portion where the through hole 94 is formed is the same as the thickness of the peripheral circuit portion. For this reason, since the height when the through hole 94 is formed is the same as that of the peripheral portion, the diameter of the through hole can be made the same as that of the peripheral circuit portion.

(I) Next, a metal layer made of an Al alloy is formed on the entire surface, and the same as the source / drain pitch of the memory,
In addition, a band-shaped metal bit line 96 is formed in parallel with the bit line direction, and is connected to the drain of the block select transistor via the through hole 94 and the contact hole 80 (FIG. 18). Through the above steps, the semiconductor device and the semiconductor memory device of the present invention can be manufactured. Further, an oxide film thicker than the gate oxide film can be formed between the gate electrode of the block select transistor and the diffusion layer by the accelerated oxidation, and as a result, the oxide film between the gate electrode of the block select transistor and the memory diffusion layer can be formed. Insulation between them can be ensured.

[0030]

According to the present invention, the memory matrix is divided into blocks each including a plurality of memory cells, and the memory diffusion layer is formed by dividing the source and drain so as to be independent for each block. The diffusion layer is connected to a common metal bit line extending in the direction of the memory diffusion layer via a block selection transistor, and a plurality of gate electrodes made of a strip-shaped conductor are used as gate electrodes for the block selection transistor in the direction of the memory diffusion layer. In each block select transistor, only one of the gate electrodes functions as a transistor, and a diffusion layer is formed continuously under the other gate electrodes, and the diffusion layer and its gate are formed. By forming an insulating film thicker than the gate insulating film between the electrodes, block selection at each gate electrode Transistor number decreases, the parasitic capacitance between the semiconductor substrate of the gate electrode is reduced, it is possible to reduce the gate delay.

When a metal gate electrode made of a low-resistance metal film is formed on the gate electrode via the gate electrode interlayer insulating film, and the gate electrode and the metal gate electrode are electrically connected to each other through through holes, In addition to reducing the parasitic capacitance with the semiconductor substrate, the parasitic resistance component is also reduced, and the gate delay can be reduced. The gate electrode is not divided into one continuous band-shaped gate electrode in the block, but is divided while leaving at least the block select transistor, and the divided gate electrodes are electrically connected to the metal gate electrodes through through holes, respectively. Then, the parasitic capacitance between the gate electrode and the semiconductor substrate is further reduced, and the gate delay can be further reduced. When the gate electrode of the block select transistor on the source side of the memory diffusion layer and the gate electrode of the block select transistor on the drain side are arranged on different lines, the gate width of the block select transistor can be widened and the amount of current can be increased. The effect of gate delay can be reduced.

In the present invention, ions are implanted into a memory diffusion region that is independent for each block and a region of the block selection transistor formation region that does not function as a transistor, and then gates of a plurality of block selection transistors are formed. After ion implantation into the source diffusion layer region and the drain diffusion layer region of the selection transistor region, thermal oxidation is performed to form a block selection transistor, and at the same time, the gate electrode is connected to the memory diffusion region and the region to be the block selection transistor in the block. Due to the accelerated oxidation of ions implanted under the gate electrode in the region not functioning as a block select transistor at the intersection with the region,
Since an oxide film thicker than the gate oxide film is formed, insulation between the gate electrode of the block select transistor and the region connecting the memory diffusion region and the region to be the block select transistor in the block can be ensured.

[Brief description of the drawings]

FIGS. 1A and 1B are schematic diagrams showing a split gate memory structure, wherein FIG. 1A is a plan view and FIG.

FIG. 2 is a sectional view of another conventional example.

FIG. 3 is a circuit diagram showing a conventional example of a memory array divided into blocks.

FIG. 4A is a plan view of the conventional example, and FIG. 4B is a cross-sectional view at the XY position of FIG.

FIG. 5 is a graph showing a voltage rise time with respect to the number of bits of a conventional memory.

FIGS. 6A and 6B are diagrams illustrating an embodiment, in which FIG.
(B) is a cross-sectional view at the AB position in (A), and (C) is a cross-sectional view at the XY position in (A).

FIG. 7 shows another embodiment of the gate electrode of the embodiment, and has a planar configuration same as that of FIG. 6A, and FIG.
6B is a cross-sectional view at the XY position, and FIG.
It is sectional drawing in a position.

FIG. 8 shows still another embodiment of the gate electrode of the embodiment, and has the same planar configuration as FIG. 6 (A), and FIG. 8 (A) is a cross-sectional view at the XY position in FIG. 6 (A). , (B) is FIG. 6 (A)
It is sectional drawing in the AB position of.

FIG. 9 is a plan view of another embodiment.

FIG. 10 is a diagram showing a step of forming an element-specific region and implanting ions into a region connecting control gates in the manufacturing method of the present invention.

FIG. 11 is a view showing a step of forming a control gate and a floating gate in the manufacturing method of the present invention.

FIG. 12 is a view showing a step of ion-implanting a memory diffusion region and a region connecting the memory diffusion region and a region to be a block selection transistor in the manufacturing method of the present invention.

FIG. 13 is a view showing a step of forming a select gate and a gate of a block select transistor in the manufacturing method of the present invention.

FIG. 14 is a diagram showing a step of forming a source and a drain of a block selection transistor in the manufacturing method of the present invention.

FIG. 15 is a view showing a step of forming contact holes in the drain portion and other portions of the block select transistor in the manufacturing method of the present invention.

FIG. 16 is a view showing a step of forming a metal layer patterning in the manufacturing method of the present invention.

FIG. 17 is a view showing a step of forming a through hole in a drain portion of a block select transistor in the manufacturing method of the present invention.

FIG. 18 is a view showing a step of forming a metal bit line in the manufacturing method of the present invention.

[Explanation of symbols]

52 Source diffusion region 54 Drain diffusion region 56, 58 Block select transistor 56a, 58a Gate electrode of block select transistor 61 Floating gate 63 Control gate 64 Control gate line 66 Select gate

Claims (5)

[Claims] 1. A memory diffusion layer serving as a source / drain region of a memory cell is formed on a semiconductor substrate in parallel and in a strip shape, and a first insulating film is provided on a semiconductor substrate between a pair of memory diffusion layers. A floating gate made of a first conductor is arranged adjacent to one memory diffusion layer and spaced from the other memory diffusion layer, and is separated for each memory cell. A second insulating film is formed on the floating gate. A control gate made of a common second conductor is formed for a plurality of memory cells and extending in a band shape in parallel with the memory diffusion layer, and a third gate is formed on the control gate via a third insulator. On the semiconductor substrate between the memory diffusion layer and the floating gate, which are arranged at an interval therebetween, a plurality of memory cells extend in a band shape in a direction orthogonal to the second conductor via a fourth insulator. Common third A select gate made of a conductor is formed, and a split gate type memory cell in which a semiconductor substrate surface below the floating gate is a memory channel and a semiconductor substrate surface between the memory diffusion layer and the floating gate is a select channel is formed in a matrix. In a semiconductor memory device including an arranged memory matrix, the memory matrix is divided into blocks each including a plurality of memory cells, and the memory diffusion layer is divided so that both a source and a drain are independent for each block. And each memory diffusion layer is connected to a common metal bit line extending in the direction of the memory diffusion layer via a block selection transistor, and as a gate electrode for the block selection transistor,
A plurality of gate electrode lines made of a band-shaped fourth conductor are provided in a direction orthogonal to the memory diffusion layer direction. In each of the block select transistors, only one of the gate electrode lines is a transistor. A diffusion layer is continuously formed under the other gate electrode lines, and an insulating film thicker than the gate insulating film is formed between the diffusion layer and the gate electrode line. A semiconductor memory device characterized by the above-mentioned. 2. A low-resistance metal film formed on the first gate electrode line via a first gate electrode line made of a fourth conductor and an interlayer insulating film. 2. The semiconductor memory device according to claim 1, comprising a second gate electrode line comprising: a first gate electrode line and the second gate electrode line are electrically connected by through holes. 3. 3. The first gate electrode line is not a single continuous band-shaped gate electrode line in a block.
3. The semiconductor device according to claim 2, wherein the first gate electrode line is divided while leaving at least the block select transistor, and the divided first gate electrode lines are electrically connected to the second gate electrode lines via the through holes. 3. The semiconductor device according to claim 1. 4. The semiconductor according to claim 1, wherein the gate electrode of the block select transistor on the source side of the memory diffusion layer and the gate electrode of the block select transistor on the drain side are arranged on different lines. Storage device. 5. A method for manufacturing a semiconductor memory device including the following steps (A) to (E). (A) a step of forming an element isolation region in a semiconductor substrate; (B) after performing gate oxidation, the length in the channel length direction is shorter than the source-drain interval on the gate oxide film, and is closer to the drain side. Forming a stacked body including a floating gate for each memory cell arranged and a control gate formed thereon via an insulating film; (C) a memory diffusion region independent for each block; (D) a step of forming a select gate and simultaneously forming a plurality of gate electrodes of a block select transistor for each block; and (E) a block. Ion is implanted into the source diffusion layer region and the drain diffusion layer region of the selection transistor region, thermal oxidation is performed, and a block selection transistor is formed. At the same time, an oxide film thicker than the gate oxide film is formed between the memory diffusion layer and the gate electrode line in a region where the gate electrode line and the memory diffusion layer do not function as a block select transistor. The process to form.