JP3830276B2 - Semiconductor memory device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device called a split gate type used for an EEPROM or a flash EEPROM, and a manufacturing method thereof. In particular, the semiconductor memory device of the present invention is suitable for use in fields where high-speed and large-capacity information recording is required.
[0002]
[Prior art]
The flash memory has achieved significant integration by omitting the single bit erase function of the EEPROM. Therefore, in most cases, the erase unit of the flash memory is a certain area (referred to as a block in this specification) or a batch erase of the entire chip. In recent years, flash memory has been dramatically increased in density, and thus, a larger capacity has been realized. On the other hand, a higher density and larger capacity tend to have a larger erase block.
[0003]
The flash memory was mainly used as a replacement for UV-EPROM at first, and the size of the erase block was not a problem. However, when considering other applications, it has become necessary that the erase block can be made small and can be set to an arbitrary size as required.
[0004]
There is a flash memory described in US Pat. No. 5,280,446. The memory device employs a buried diffusion layer method using a diffusion layer as a method of connecting each memory cell, and enables high integration. However, in this method, since a diffusion layer having a large capacitance is used for the bit line of the memory, the reading speed is reduced, and this is particularly noticeable when a large-capacity memory is configured.
[0005]
In such a buried diffusion layer type flash memory, the CR product of the bit line (source / drain diffusion layer) by the diffusion layer and the capacitance C and the resistance R of the word line by polysilicon is a factor that determines the cell access time. Become one. For this reason, the access time is improved by providing a plurality of contact holes on the bit lines or word lines and connecting them to metal lines to reduce the resistance. For this reason, it is necessary to form at least two metal layers on the memory region.
[0006]
FIG. 1 shows an outline of this split gate type memory structure. A band-like source 109 and drain 108 are formed in the bit line direction, and a band-like control gate 105 is also arranged close to the drain side therebetween. That is, the control gate 105 is close to the drain 108 and is spaced from the source. A band-shaped select gate 106 is formed in the word line direction perpendicular to the control gate 105. A memory channel 102 exists in the substrate under the control gate 105 via a floating gate, and a channel 101 of a select transistor exists between the memory channel 102 and the source 109. The channels 101 and 102 are separated by an island-shaped field oxide film 107 in the bit line direction.
[0007]
In memory, most patterns are usually formed with the minimum value of the processing limit. For this reason, in the memory shown in FIG. 1, the size 103 in the word line direction per bit where two channel regions exist is larger than the size 104 of the bit line per bit.
[0008]
FIG. 2 shows the state of the field and the diffusion layer in the memory array. The source diffusion layers 121 and the drain diffusion layers 122 are alternately arranged, and a channel region 125 in which a memory is formed is provided between them. An island-like field oxide film 124 is formed for element isolation in the bit line direction of the channel region 125. Is formed. In the source / drain diffusion layers 121 and 122, contact holes 123 are formed alternately for a plurality of bits and alternately between the source and the drain, and the bit line resistance is lowered by connecting to the upper metal bit line. Although not shown in the figure, the select gate is provided with contact holes at both ends of the array and connected to the metal layer to reduce the word line resistance.
[0009]
FIG. 3 shows a cross-sectional view of the memory array in the bit line direction (vertical direction in FIG. 2). In this figure, reference numeral 134 denotes a polysilicon-metal interlayer insulating film, which insulates the floating gate 130, the control gate 105 and the select gate 106 from each other. A source or drain contact 132 in the memory is formed between the memory regions 131 where a plurality of memory transistors are formed. Reference numeral 135 denotes a gate of a peripheral transistor, and 133 denotes a contact of a peripheral circuit portion.
[0010]
In FIG. 3, since the memory region 131 has three polysilicon layers, the level difference is larger than the peripheral circuit portion having one polysilicon layer. For this reason, the contact hole 132 formed close to the memory region 131 is located higher than the contact hole 133 of the peripheral circuit. However, since there is a limit to the depth of focus in the lithography process, when the memory portion is higher than the surrounding area in this way, the spatial resolution deteriorates in the steps after contact formation, and as a result, this portion In this case, the minimum processing dimension becomes large. Usually, the through hole diameter is larger than the contact hole diameter. Therefore, if the metal bit line is formed on the upper layer of the metal word line, the through hole 141 is formed on the contact in the memory region as shown in FIG. The hole pitch becomes larger. For this reason, it is impossible to form a through hole on the source / drain contact formed near the processing limit value as shown in FIG. 4, and this means that a metal bit line is formed above the metal word line. It is impossible to do. For this reason, the metal bit line must be configured as a lower layer of the metal word line.
[0011]
FIG. 5 shows the first metal layer (the lowest metal layer when the metal layer is multi-layered) in the metal bit line, and the second metal layer (multi-metal layer in the metal word line). It is sectional drawing of the bit line direction at the time of setting it as the structure of the 2nd metal layer from the bottom in the case of becoming. As shown in FIG. 1, this device has a pitch 104 in the bit line direction narrower than a pitch 103 in the word line direction. For this reason, the pitch 151 of the second metal layer shown in FIG. 5 is larger than the pitch 104 of the memory in the bit line direction.
[0012]
[Problems to be solved by the invention]
Conventionally, memory cells connected to one metal bit line are erased all at once. Therefore, an erase block can be set only in units of metal bit lines, and the erase block size can be set freely. There were few.
In a flash memory, charges in the floating gate are released by UV light at the end of the process (hereinafter referred to as UV erasure). This UV erasure is very important in making a reference signal in a readout circuit and analyzing process data. However, when UV erasure is performed when the arrangement pitch of the metal word line and the select gate is different as shown in FIG. 5, bits that are not UV-erased every several bits are generated due to the shadow of the metal word line.
[0013]
In addition, when the first metal layer is used for the metal bit line as shown in FIG. 5, the distance between the select gate and the metal bit line is short, so the capacitance between the two controls the read speed. It became one of.
[0014]
The first object of the present invention is to increase the degree of freedom in setting the erase block size.
A second object of the present invention is to prevent the formation of bits that are not UV erased by shadows on metal word lines.
The third object of the present invention is to prevent the reading speed from being suppressed due to the capacitance between the select gate and the metal bit line.
[0015]
[Means for Solving the Problems]
The present invention is a semiconductor memory device having a memory matrix in which split gate type memory cells are arranged in a matrix, and the memory matrix is set regardless of the area of the memory cell selected by the metal bit line. It has a plurality of memory areas as blocks, and the memory diffusion layer is divided and formed so that both the source and drain are independent for each block, and each memory diffusion layer is connected to a metal bit line via a block select transistor. The control gates are also divided and formed so as to be independent for each block.
Thereby, the erase block size can be set regardless of the number of memory cells connected to the metal bit line, and a large degree of freedom can be given to the setting of the erase block size.
[0016]
Since the block select transistor is interposed between the bit line contact hole forming portion and the memory portion, the distance between the contact hole and the memory cell is increased. Since the memory cell portion has a three-layer poly-thincon structure, the level difference is large. However, the step size is reduced by moving away from the memory cell, and the diameter of the contact hole or through hole formed in that portion is reduced as in the peripheral circuit portion. be able to.
[0017]
The semiconductor memory device of the present invention includes the following steps (A) to (D).
(A) a step of forming an element dividing region on a semiconductor substrate;
(B) After performing the gate oxidation, the floating gate for each memory cell arranged on the gate oxide film with the length in the channel length direction being shorter than the distance between the source and the drain and being close to the drain side; Forming a stack gate comprising a control gate formed on an insulating film on the top;
(C) Ion implantation into a memory diffusion region independent for each block and a region connecting the memory diffusion region and a region that becomes a block select transistor in the block;
(D) A step of forming a block select transistor in the area of the block select transistor.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
In the semiconductor memory device of the present invention, the memory cells arranged adjacent to each other with the memory diffusion layer interposed therebetween are arranged in line targets with respect to the respective memory diffusion layers.
The memory matrix has a plurality of memory regions as blocks set independently of the memory cell region selected by the metal bit line, a memory diffusion layer is formed for each block in both source and drain, and each memory The diffusion layer is connected to the metal bit line via a block select transistor arranged between adjacent select gates of blocks adjacent in the bit line direction, and the control gate is also divided so that each block is independent. The control gates formed on both sides of the drain are electrically connected so that they are always at the same potential to form a control gate pair, and adjacent control gate pairs are connected to each other. Instead, every other pair of control gates is connected and controlled. It is preferred that Rugeto pairs are summarized into two blocks. As a result, the write operation can be performed without applying stress due to the half-selected state to the adjacent bits.
[0019]
When the conductor connecting the control gate pairs crosses the diffusion layer connecting the block select transistor and the memory diffusion layer, ion implantation is performed in that region before the gate oxidation in the step (B).
The impurity concentration of the source / drain of the block select transistor is preferably the same as the impurity concentration of the source / drain of the peripheral transistor.
[0020]
It is preferable that the gate electrode of the block select transistor on the source side of the memory diffusion layer and the gate electrode of the block select transistor on the drain side are arranged at positions off one straight line. As a result, the block select transistor can be widened to allow a large current to flow. This contributes to an increase in reading speed.
[0021]
The metal bit line connected to the memory diffusion layer via the block select transistor is a strip-shaped metal layer parallel to the memory diffusion layer and at the same interval as the memory diffusion layer, and an insulating layer is provided above the memory diffusion layer. A metal word line is connected to the select gate, but the metal word line is made of a metal layer formed in a strip shape in parallel with the select gate and at the same interval as the select gate. The metal word line and the select gate are electrically connected by a contact hole located on the extension line of the select gate, and the metal word line is formed below the metal bit line. It is preferable that As a result, the capacitance between the select gate and the metal bit line is reduced, and the signal reading speed is improved. In addition, since the pitch between the metal layer on the memory and the memory is the same in both the word line direction and the bit line direction, there is no bit shadowing the metal layer, and all bits can be UV erased.
[0022]
The control gate is also divided into blocks. Therefore, at least two contact holes are formed on the control gate in the block, and a strip-shaped metal layer parallel to the word line is formed on the control gate via an insulating film. The metal layer is formed by the contact hole. It is preferably connected to a control gate. Thereby, the resistance of the control gate can be reduced, and the signal reading speed can be improved.
[0023]
The gate electrode of the block select transistor is formed of a polysilicon layer so as to be common to a plurality of block select transistors within the block. Therefore, at least two contact holes are formed on the common polysilicon layer, and a strip-shaped metal layer parallel to the word line is formed on the polysilicon layer via an insulating film. The contact hole is preferably connected to the polysilicon layer. Thereby, the gate resistance of the block select transistor can be reduced, and the signal reading speed can be improved.
[0024]
【Example】
FIG. 6 shows one block of the memory matrix in one embodiment. A plurality of split gate type memory cells 1 having a floating gate, a control gate, and a select gate are connected in parallel by memory diffusion layers 7 and 8 in the block, and each source and drain are shared in a matrix. Arranged in a shape. The memory diffusion layers 7 and 8 are formed independently for each block, and are connected to the metal bit lines 11 and 12 via block select transistors 9 and 10, respectively. The memory cells 1 arranged adjacent to each other with the memory diffusion layers 7 and 8 interposed therebetween are arranged as line targets with respect to the respective memory diffusion layers 7 or 8.
[0025]
Control gates 2 and 3 on both sides of the drain 8 are electrically connected to form a control gate pair 4. Also, the control gate pairs 4 are not connected to the adjacent control gate pair 5 but are connected to each other, such as one control gate pair 6 and another control gate pair 14. Similarly, the control gate pair 5 adjacent to the control gate pair 4 is also connected to every other control gate pair 13, 15. As a result, the write operation can be performed without applying stress due to the half-selected state to the adjacent bits. All the connections between these control gate pairs are made within the block, and no direct electrical connection is made with the other blocks.
[0026]
FIG. 7 shows an example of operating conditions of this embodiment. Read L1 & L2 indicates a voltage condition when reading data in the memory cells L1 and L2 in the figure. Here, all units are volts (V), and F means open. Erase indicates that all memories in the block are erased, and PGM means writing to each memory cell.
[0027]
Next, FIG. 8 shows a schematic plan view when this circuit is manufactured on a semiconductor substrate.
A floating gate 32 whose length in the channel length direction is shorter than the distance between the source diffusion layer 38 and the drain diffusion layer 39 is arranged close to the drain side, and a strip-shaped polysilicon control gate 33 is provided above the drain gate. The diffusion layer 39 is arranged in parallel. The source diffusion layer 38 and the drain diffusion layer 39 are shared between a pair of memory cells arranged so as to sandwich the source diffusion layer 38 and the drain diffusion layer 39, and the memory cells are arranged in line targets for both the source diffusion layer 38 and the drain diffusion layer 39. Has been. In the control gate 33, adjacent memory cells sandwiching one drain are connected by polysilicon layers 33a and 33b to form a pair, and every other pair of control gates is connected to each other. The control gate 33 is formed as an independent pattern for each block.
[0028]
A select gate 34 made of a strip-like polysilicon layer extending in a direction orthogonal to the control gate 33 is disposed.
The source diffusion layer 38 and the drain diffusion layer 39 that are memory diffusion layers are formed independently for each block. The source diffusion layer 38 and the drain diffusion layer 39 are connected to block select transistors 40 and 37, respectively, and are connected to a metal bit line (not shown) through contact holes 41 and 36.
[0029]
The gates 35 of the block select transistor 40 for the source diffusion layer 38 and the block select transistor 37 for the drain diffusion layer 39 are not arranged on one straight line but are shifted. As a result, a wider transistor width (channel width) can be ensured than when arranged on a straight line, and thus a larger amount of current can be secured, which leads to an increase in reading speed.
[0030]
Next, the manufacturing process of the present invention will be described with reference to FIGS.
(A) First, field oxidation is performed on a P-type silicon substrate to form an active region 50 in which a memory cell, a block select transistor, a peripheral transistor, and a diffusion layer are formed. 51 is formed (FIG. 9).
Next, arsenic is implanted by ion implantation into a region 53 where polysilicon layers 33a and 33b (see FIG. 8) connecting the control gates in the active region 50 intersect.
[0031]
(B) Next, gate oxidation is performed on the entire surface, and then polysilicon film to be the floating gate 32 is formed. After the floating gate is etched into a strip shape that is separated in a direction perpendicular to the bit line, an interpolysilicon insulating film is formed, and further, a polysilicon film to be the control gate 33 is formed.
Further, the floating gate polysilicon layer / polysilicon insulating layer / control gate polysilicon layer are simultaneously etched in a strip shape in the direction parallel to the bit line, thereby forming the floating gate 32 and the control gate 33 independent for each block. Form. At this time, the control gate polysilicon layer is etched so that adjacent control gates sandwiching the drain form an electrically connected pair and every other pair is connected in the block. To form polysilicon layer patterns 33a and 33b (FIG. 10).
[0032]
(C) Next, arsenic is implanted into the memory diffusion regions of the memory source portion 38 and the drain portion 39 and the region 57 connecting these memory diffusion regions and the block select transistor region 60 by ion implantation. Inject (FIG. 11).
At this time, in the region where the polysilicon layer patterns 33a and 33b connecting the control gate are present on the region 57, the polysilicon layer patterns 33a and 33b become a mask, and arsenic is not implanted into the region 57. However, in this region, as described above with reference to FIG. 9, since arsenic is implanted in advance, the electrical connection between the memory diffusion layer and the block select transistor is maintained.
In this region, since arsenic is implanted before gate oxidation, a speed-up oxide film thicker than the gate oxide film is formed, so that electrical insulation between the diffusion layer and the control gate can be ensured.
[0033]
(D) Next, an oxide film sidewall is formed on the control gate sidewall by self-alignment, and then gate oxidation is performed again on the entire wafer surface to form a polysilicon layer.
Next, this polysilicon layer is patterned to form a select gate 34, a gate 35 of a block select transistor, and a gate (not shown) of a peripheral transistor (FIG. 12).
[0034]
(E) Next, arsenic is implanted into the block select transistor region 60 and the peripheral transistor source / drain regions (not shown), and the source and drain of the block select transistor and peripheral transistor (not shown) are connected. Form (FIG. 13).
In the region 64 where the gates of the other block transistors intersect on the diffusion region connecting the block select transistor and the memory diffusion region, arsenic is implanted in advance before the second gate oxidation. Since a speed-up oxide film thicker than the gate oxidation is formed between the silicon layer and the diffusion layer by the second gate oxidation, the electrical insulation between the gate and the diffusion layer can be ensured.
[0035]
(F) Next, a metal-polysilicon insulating film is formed on the entire surface, contact holes 36 and 41 are formed in the drain portion of the block select transistor, contact hole 66 is formed on the select gate, contact hole 67 is formed on the control gate, and the block select transistor. A contact hole 68 is formed on the gate (FIG. 14).
At this time, since the contact holes 36 and 41 have block select transistors, the distance from the memory becomes larger than when there is no block select transistor. For this reason, since the distance from the high step portion becomes large, the film thickness of the metal-polysilicon insulating film becomes the same as that of the peripheral circuit portion. Since the contact hole formed in this portion deviates from the depth of focus at the time of photography when the insulating film is thick, the contact hole diameter has to be larger than the surroundings. However, in the present invention, since the metal-polysilicon insulating film has the same thickness as that of the peripheral portion, this depth of focus problem is eliminated and the diameter of the contact hole in the peripheral circuit portion can be made the same.
[0036]
(G) Next, a metal layer made of an Al alloy is formed on the entire surface, the metal layer is patterned, and a strip-shaped metal that has the same pitch as the select gate and is parallel to the select gate immediately above the select gate. A layer pattern 69 is formed and connected to the select gate through the contact hole 66. In addition, a strip-like pattern parallel to the word line direction is simultaneously formed by the metal layer and connected to the control gate through the contact hole 67. Further, a strip-like pattern parallel to the word line direction is simultaneously formed by the metal layer and connected to the gate of the block select transistor through the contact hole 68 (FIG. 15).
At this time, since the metal layer 69 is the lowermost layer in the multilayer metal layer, the minimum processing dimension can be made smaller than that of the upper metal layer. Therefore, even the metal layer 69 having a stripe shape perpendicular to the bit line direction, which is the short direction of the memory, can be processed at the same pitch as that of the memory.
[0037]
(H) Next, a metal-metal insulating film is formed on the entire surface, and a through hole 72 is formed in the drain portion of the block select transistor (FIG. 16). As described above, the metal-polysilicon insulating film in the portion where the through hole 72 is formed has the same thickness as the peripheral circuit portion. For this reason, since the height when the through hole 72 is formed is also the same as that of the peripheral portion, the through hole diameter can be made the same as that of the peripheral circuit portion.
[0038]
(I) Next, a metal layer made of an Al alloy is formed on the entire surface, and a band-shaped metal bit line 73 having the same source / drain pitch as the memory and parallel to the bit line direction is formed. Through hole 72, contact hole The drains of the block select transistors are connected via 36 and 41 (FIG. 17).
Here, the metal bit line 73 is a connection portion with the through hole 72, and it is necessary to provide a certain overlap with respect to the through hole 72 in consideration of a mask alignment margin at the time of lithography. Conventionally, when trying to form a through-hole in this part, the metal-polysilicon insulating film is thick, so it is out of focus depth during lithography, so it is necessary to make the through-hole diameter larger than the peripheral circuit part. there were. The metal bit lines 73 could not be formed at the same pitch as the memory cycle using the second layer metal whose minimum processing dimension is larger than that of the first layer metal from the lower layer.
However, since the through hole can be reduced to the same diameter as the peripheral circuit portion in the present invention, the metal bit line 73 can be formed at the same pitch as the memory pitch even if the second layer metal is used.
[0039]
【The invention's effect】
In the present invention, a memory matrix in which split-gate memory cells are arranged in a matrix is divided into a plurality of blocks, and the memory diffusion layer is formed so that both the source and drain are divided independently for each block. Therefore, the erase block size can be set regardless of the number of memory cells connected to the metal bit line, and a large degree of freedom can be given to the setting of the erase block size.
Since each memory diffusion layer is connected to a metal bit line via a block select transistor, the block select transistor is interposed between the bit line contact hole forming portion and the memory portion, and the contact hole The distance between the memory cell and the memory cell increases. Since the memory cell portion has a three-layer poly-thincon structure, the level difference is large. However, the step size is reduced by moving away from the memory cell, and the diameter of the contact hole or through hole formed in that portion is reduced as in the peripheral circuit portion. be able to.
[0040]
Control gates arranged on both sides of the memory diffusion layer on the side where the floating gate is formed are electrically connected so that they are always at the same potential to form a control gate pair. Since the matched control gate pairs are not connected to each other, and every other control gate pair is connected, the write operation can be performed without applying stress due to the half-selected state to the adjacent bits.
Since the source / drain of the block select transistor and the memory diffusion layer are formed in separate steps, both can be optimized.
If the gate electrode of the block select transistor on the source side of the memory diffusion layer and the gate electrode of the block select transistor on the drain side are arranged at positions off one straight line, the width of the block select transistor is increased and a large current is generated. This contributes to an increase in reading speed.
[0041]
Metal bit lines are formed in a strip-shaped metal layer parallel to the memory diffusion layer and at the same interval as the memory diffusion layer, and metal word lines are formed in a strip shape parallel to the select gate and at the same interval as the select gate. If the metal word line is formed below the metal bit line, the capacitance between the select gate and the metal bit line is reduced, and the signal reading speed is improved. In addition, since the pitch between the metal layer on the memory and the memory is the same in both the word line direction and the bit line direction, there is no bit shadowing the metal layer, and all bits can be UV erased.
If the block is connected to the metal layer via at least two contact holes on the control gate, the resistance of the control gate can be reduced and the signal reading speed can be improved.
If the common gate in the block of the block select transistor is connected to the metal layer through at least two contact holes, the gate resistance of the block select transistor can be reduced and the signal reading speed can be improved. .
[0042]
In the manufacturing method of the present invention, ions are implanted into the connection region connecting the memory diffusion region and the region to be the block select transistor, and after the gate oxidation of the block select transistor, a polysilicon layer is formed, and then the pattern is formed. Since the gate of the block select transistor is formed, even if the gate of the block select transistor crosses the connection region, the gate oxide film is formed by accelerated oxidation between the gate of the block select transistor and the diffusion layer of the connection region. A thick oxide film can be formed, and insulation between the gate of the block select transistor and the diffusion layer can be secured.
In addition, when there is a region where the conductor connecting the control gates crosses over the diffusion layer connecting the block select transistor and the memory diffusion layer, gate oxidation for forming a gate oxide film under the floating gate is present in that region. If ion implantation is performed before the step, an insulating film thicker than the gate oxide film can be formed between the conductor connecting the control gates and the diffusion layer by accelerated oxidation. It is possible to ensure insulation between the conductor connecting the and the diffusion layer.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing a split gate type memory structure.
FIG. 2 is a plan view showing a field and a diffusion layer in a conventional memory array.
3 is a cross-sectional view of the memory array of FIG. 2 in the bit line direction.
FIG. 4 is a cross-sectional view when a through hole is to be formed on a contact in a conventional memory region.
FIG. 5 is a cross-sectional view in the bit line direction of a conventional device when a metal bit line is a lower layer and a metal word line is an upper layer.
FIG. 6 is a circuit diagram showing an embodiment.
FIG. 7 is a circuit diagram and a table showing operating conditions of the embodiment.
FIG. 8 is a plan view of the same embodiment.
FIG. 9 is a diagram showing a process of forming an element region and an ion implantation step into a region connecting control gates in the manufacturing method of the present invention.
FIG. 10 is a diagram showing a process of forming a control gate and a floating gate in the manufacturing method of the present invention.
FIG. 11 is a diagram showing a step of ion implantation into a memory diffusion region and a region connecting the memory diffusion region and a region to be a block select transistor in the manufacturing method of the present invention.
FIG. 12 is a diagram showing a process of forming a select gate and a gate of a block select transistor in the manufacturing method of the present invention.
FIG. 13 is a diagram showing a process of forming a source and a drain of a block select transistor in the manufacturing method of the present invention.
FIG. 14 is a diagram showing a step of forming a contact hole in the drain portion and other portions of the block select transistor in the manufacturing method of the present invention.
FIG. 15 is a diagram showing a step of forming a metal layer patterning in the manufacturing method of the present invention.
FIG. 16 is a diagram showing a step of forming a through hole in the drain portion of the block select transistor in the manufacturing method of the present invention.
FIG. 17 is a diagram showing a process of forming a metal bit line in the manufacturing method of the present invention.
[Explanation of symbols]
1,32 floating gate
2,3,33 Control gate
7,38 Source diffusion region
8,39 Drain diffusion region
9, 10, 37, 40 Block select transistor
11, 12, 73 Metal bit line
33a, 33b Pattern to connect between control gates
34 Select Gate
35 Block Select Transistor Gate
36, 41 Contact hole

Claims (8)

A silicon substrate having a first conductivity type has a memory diffusion layer serving as a source / drain region having a second conductivity type formed in parallel and alternately in a strip shape, and has a length in the channel length direction. A first conductor, which is shorter than the source-drain interval and serves as a floating gate, is formed on each silicon cell between the source and the drain on the silicon substrate via the first insulator via the first insulator. A second conductor serving as a control gate via an insulator is directly above the first conductor, and is in a strip shape and parallel to the source / drain, and is common to a plurality of memory cells. Memory cells having a third conductor which is formed and is formed in a strip shape in a direction perpendicular to the second conductor and serving as a select gate are arranged in a matrix, and each metal bit line 1 In the semiconductor memory device having a memory matrix in which memory cells of each is adapted to be selected,
The memory matrix has a plurality of memory areas as blocks set independently of the area of the memory cells selected by the metal bit lines,
The memory diffusion layer is formed for each block in both source and drain, and each memory diffusion layer is connected to the metal via a block select transistor disposed between adjacent select gates of blocks adjacent in the bit line direction. It is connected to the bit line, and the control gate is also divided and formed to be independent for each block,
The memory cells share a memory diffusion layer in which memory cells adjacent to each other in a direction crossing the bit line direction serve as a source or a drain,
Control gates arranged on both sides of the drain are electrically connected so as to always have the same potential to form a control gate pair, and the control gate pairs adjacent to each other in the direction crossing the bit line direction Are connected, every other control gate pair is connected, and the control gate pair is grouped into two in the block. 2. The semiconductor memory device according to claim 1 , wherein the impurity concentration of the source / drain of the block select transistor is the same as the impurity concentration of the source / drain of the peripheral transistor. 3. The semiconductor memory device according to claim 1 , wherein the gate electrode of the block select transistor on the source side of the memory diffusion layer and the gate electrode of the block select transistor on the drain side are arranged at positions off one straight line. . The metal bit line is a strip-shaped metal layer parallel to the memory diffusion layer and at the same interval as the memory diffusion layer. The metal bit line is disposed above the memory diffusion layer with an insulating layer interposed therebetween. The transistor is electrically connected by a contact hole arranged on the extended line of the memory diffusion layer,
A metal word line made of a metal layer formed in a strip shape in parallel with the select gate and at the same interval as the select gate is arranged above the select gate via an insulating layer, and the metal word line and the select gate Are electrically connected by a contact hole arranged on the extension line of the select gate,
And the semiconductor memory device according to claim 1, metal word lines are formed below the metal bit lines 3. At least two contact holes are formed on the control gate, and a strip-shaped metal layer parallel to the word line is formed on the upper layer of the control gate via an insulating film. The metal layer is connected to the control gate by the contact hole. and that the semiconductor memory device according to any one of claims 1 to 4. At least two contact holes are formed on the gate electrode of the block select transistor, and a strip-shaped metal layer parallel to the word line is formed on the gate electrode via an insulating film, and the metal layer is formed by the contact hole. the semiconductor memory device according to any one of claims 1-5, which is connected to the gate electrode. The method for manufacturing a semiconductor memory device according to claim 1, comprising the following steps (A) to (D).
(A) a step of forming an element dividing region on a semiconductor substrate;
(B) After performing the gate oxidation, the floating gate for each memory cell arranged on the gate oxide film with the length in the channel length direction being shorter than the distance between the source and the drain and being close to the drain side; Forming a stack gate comprising a control gate formed on an insulating film on the top;
(C) Ion implantation into a memory diffusion region independent for each block and a region connecting the memory diffusion region and a region that becomes a block select transistor in the block;
(D) A step of forming a block select transistor in the area of the block select transistor. A region where a conductor connecting the control gates crosses the diffusion layer connecting the block select transistor and the memory diffusion layer, and ion implantation is performed in that region before the gate oxidation in the step (B). 8. A method for manufacturing a semiconductor memory device according to 7 .

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