JP4031167B2 - Nonvolatile semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device, and more particularly to improvement of a cell layout of a high-density and highly integrated nonvolatile semiconductor memory device.
[0002]
[Prior art]
Nonvolatile semiconductor memory devices capable of electrically rewriting data are widely used for high-speed ROM and mass storage. Further, the memory cell of the nonvolatile semiconductor memory device is generally composed of a MOS transistor. As the memory cell structure, a stack gate structure having a charge transfer layer and a control gate layer and a single gate structure including only the control gate layer are generally used.
[0003]
33 to 35 show an example of a memory cell having a stack gate structure. 33 is a plan view of the memory cell, FIG. 34 is a cross-sectional view taken along line XXXIV-XXXIV in FIG. 33, and FIG. 35 is a cross-sectional view taken along line XXXV-XXXV in FIG.
[0004]
In this example, the memory cell is composed of an N-channel MOS transistor. In this case, the memory cell is formed in a P-type silicon substrate or a P-type well region. In this example, the memory cell is formed in a P-type well region.
[0005]
Specifically, an N well region 12 and a P well region 13 are formed in the P type silicon substrate 11. In addition, a trench for element isolation is formed in the silicon substrate 11, and an element isolation insulating material (for example, silicon oxide) 14 is embedded in the trench.
[0006]
A region sandwiched between the element isolation insulating materials 14 is an element region. On the silicon substrate 11 (P well region 13) in the element region, a thin tunnel insulating film (for example, silicon oxide) 15 capable of flowing a minute tunnel current at the time of writing / erasing is formed.
[0007]
A charge transfer layer 16 is formed on the tunnel insulating film 15. The charge transfer layer 16 is composed of an electrically floating conductive layer (for example, a polysilicon layer containing impurities).
[0008]
A control gate layer 18 is formed on the charge transfer layer 16 via an intergate insulating layer 17. Since the charge transfer layer 16 and the control gate layer 18 are capacitively coupled, when the potential of the control gate layer 18 varies, the potential of the charge transfer layer 16 also varies.
[0009]
Since the charge transfer layer 16 and the control gate layer 18 are simultaneously processed in a self-aligning manner, the side edges in the direction (column direction) perpendicular to the direction (row direction) in which the control gate layer (word line) 18 extends are mutually aligned. Match. Further, the side end in the row direction of the charge transfer layer 16 exists on the element isolation insulating material 14.
[0010]
In the element region, the surface region of the silicon substrate 11 immediately below the charge transfer layer 16 is a channel region. Further, N-type diffusion layers (source region or drain region) 19 are formed on both sides of the channel region.
[0011]
In the memory cell having the stack gate structure described above, the data of the memory cell is determined by the amount of charge in the charge transfer layer 16. That is, the threshold value of the memory cell increases as the negative charge (electrons) in the charge transfer layer 16 increases, and decreases as the positive charge (holes) in the charge transfer layer 16 increases.
[0012]
A state where there are many negative charges in the charge transfer layer 16 is called a write state, and a state where there are many positive charges in the charge transfer layer 16 is called an erase state.
[0013]
The amount of charge in the charge transfer layer 16 can be adjusted by passing a tunnel current through the tunnel insulating film 15 during the write / erase operation. Whether or not a tunnel current flows is determined by a voltage applied between the control gate layer (charge transfer layer) and the channel. That is, when a high voltage is applied to the tunnel insulating film 15, a tunnel current flows.
[0014]
For example, when a high voltage is applied to the tunnel insulating film 15 and the channel potential is higher than the potential of the charge transfer layer, the tunnel current flows from the channel toward the charge transfer layer. When a high voltage is applied to the tunnel insulating film 15 and the potential of the charge transfer layer is higher than the potential of the channel, the tunnel current flows from the charge transfer layer toward the channel.
[0015]
36 to 38 show an example of a memory cell having a single gate structure. 36 is a plan view of the memory cell, FIG. 37 is a cross-sectional view taken along line XXXVII-XXXVII in FIG. 36, and FIG. 38 is a cross-sectional view taken along line XXXVIII-XXXVIII in FIG.
[0016]
Also in this example, the memory cell is composed of an N-channel MOS transistor. In this case, the memory cell is formed in a P-type silicon substrate or a P-type well region. However, in this example, the memory cell is formed in the P-type well region.
[0017]
Specifically, an N well region 22 and a P well region 23 are formed in the P type silicon substrate 21. In addition, a trench for element isolation is formed in the silicon substrate 21, and an element isolation insulating material (for example, silicon oxide) 24 is embedded in the trench.
[0018]
A region sandwiched between the element isolation insulating materials 24 is an element region. A thin tunnel insulating film (for example, silicon oxide) 25 is formed on the silicon substrate 21 (P well region 23) in the element region so that a minute tunnel current can flow during writing / erasing.
[0019]
On the tunnel insulating film 25, a charge holding insulating layer 26 is formed for holding charges and suppressing charge loss. The charge retention insulating layer 26 is composed of, for example, a stack of a plurality of insulating materials.
[0020]
A control gate layer 27 is formed on the charge retention insulating layer 26. In the element region, the surface region of the silicon substrate 21 immediately below the control gate layer 27 is a channel region. Further, N-type diffusion layers (source region or drain region) 28 are formed on both sides of the channel region.
[0021]
In the memory cell having the above-described single gate structure, the data of the memory cell is determined by the amount of charges trapped at the charge trap level formed at the interface between the tunnel insulating film 25 and the charge holding insulating layer 26. That is, the threshold value of the memory cell increases as the number of negative charges (electrons) trapped in the charge trap level increases, and decreases as the number of positive charges (holes) trapped in the charge trap level increases. .
[0022]
A state where there are many negative charges trapped in the charge trap level is called a write state, and a state where there are many positive charges trapped in the charge trap level is called an erase state.
[0023]
The amount of charges at the charge trap level formed at the interface between the tunnel insulating film 25 and the charge holding insulating layer 26 can be adjusted by flowing a tunnel current through the tunnel insulating film 25 during the write / erase operation. Whether or not a tunnel current flows is determined by a voltage applied between the control gate layer and the channel. That is, when a high voltage is applied to the tunnel insulating film 25, a tunnel current flows.
[0024]
For example, when a high voltage is applied to the tunnel insulating film 25 and the channel potential is higher than the potential of the control gate layer, the tunnel current flows from the channel toward the charge retention insulating layer. In addition, when a high voltage is applied to the tunnel insulating film 25 and the potential of the control gate layer is higher than the channel potential, the tunnel current flows from the charge holding insulating layer toward the channel.
[0025]
In the single-gate memory cell, a charge transfer insulating layer is provided between the tunnel insulating film 25 and the charge holding insulating layer 26, and the state (data) of the memory cell is trapped in the charge transfer insulating layer. The amount of charge may be determined.
[0026]
39 to 42 show a memory cell array of a NOR cell type nonvolatile semiconductor memory device. 39 and 40 are plan views of the memory cell array, FIG. 41 is a cross-sectional view taken along line XLI-XLI in FIGS. 39 and 40, and FIG. 42 is a line XLII-XLII in FIGS. 39 and 40. FIG.
[0027]
For easy understanding of the drawing, FIG. 39 omits the wiring layer in which the bit line is formed, and FIG. 40 shows only the wiring layer in which the bit line is formed. That is, the bit line of FIG. 40 is formed on the device of FIG.
[0028]
In this example, a case in which a memory cell array is configured using memory cells having a stack gate structure will be described. However, a similar layout can be adopted even for a memory cell having a single gate structure.
[0029]
The structure of the memory cell has been described with reference to FIGS.
[0030]
The control gate layer (word line) 18 of the memory cell extends in the row direction. On the memory cell, an interlayer insulating film (for example, silicon oxide) 31 covering the memory cell is formed. In the interlayer insulating film 31, a contact hole (bit line contact) 30 reaching the drain diffusion layer 19d of the memory cell is formed.
[0031]
A contact plug 32 made of a conductive material is embedded in the contact hole 30. A bit line 33 is formed on the interlayer insulating film 31. The bit line 33 is electrically connected to the drain diffusion layer 19d of the memory cell via the contact plug 32.
[0032]
The bit line 33 extends in the column direction. That is, the control gate layer 18 and the bit line 33 are arranged so as to cross each other vertically or substantially vertically. One memory cell is arranged at the intersection of the control gate layer 18 and the bit line 33.
[0033]
The drain diffusion layer 19d is shared by two memory cells in the column direction, and is independent of the memory cells in the row direction. The source diffusion layer 19s extends in the row direction and serves as a common source line. Therefore, the source diffusion layer 19s is shared by two memory cells in the column direction, and is shared by a plurality of memory cells in the row direction adjacent to the source diffusion layer 19s.
[0034]
Further, the element isolation insulating material 14 is not formed in the region where the source diffusion layer 19s is formed. That is, the element isolation region (element isolation insulating material) 14 is formed to extend in the column direction, but is interrupted at the source diffusion layer 19s. The drain diffusion layers 19 d of the memory cells existing in one column are electrically connected to each other by the bit line 33.
[0035]
43 and 44 show the shapes of contact holes (bit line contacts) when the devices of FIGS. 39 to 42 are actually manufactured.
[0036]
That is, when the memory cell is miniaturized and the contact hole (bit line contact) is also miniaturized, even if the contact hole is laid out in a square shape, the shape of the resist film serving as a mask becomes circular. In some cases, the shape of the contact hole formed by etching using as a mask is also circular.
[0037]
This example merely explains that the shape of the contact hole is not limited to a square but may be a circle.
[0038]
45 to 48 show a memory cell array of the NAND cell type nonvolatile semiconductor memory device. 45 and 46 are plan views of the memory cell array, FIG. 47 is a cross-sectional view taken along line XLVII-XLVII in FIGS. 45 and 46, and FIG. 48 is a line XLVIII-XLVIII in FIGS. 45 and 46. FIG.
[0039]
For easy understanding of the drawing, FIG. 45 omits the wiring layer in which the bit line is formed, and FIG. 46 shows only the wiring layer in which the bit line is formed. That is, the bit line of FIG. 46 is formed on the device of FIG.
[0040]
In this example, a case in which a memory cell array is configured using memory cells having a stack gate structure will be described. However, a similar layout can be adopted even for a memory cell having a single gate structure.
[0041]
A NAND cell type memory cell array has a structure in which a plurality of NAND strings (or NAND cell units) are connected to a bit line. One NAND string includes a plurality of memory cells connected in series and two select transistors connected to both ends of each memory cell.
[0042]
The structure of the memory cell has been described with reference to FIGS. The structure of the select transistor has a stack gate structure as in the memory cell. However, the select transistor does not have a charge transfer layer. For example, an upper gate and a lower gate are connected to each other and function as one gate electrode (select gate line) SG1, SG2.
[0043]
Both the control gate layer (word line) 18 and select gate lines SG1, SG2 of the memory cell extend in the row direction. On the memory cell, an interlayer insulating film (for example, silicon oxide) 31 covering the memory cell is formed. In the interlayer insulating film 31, a contact hole (bit line contact) 30 reaching the drain diffusion layer 19d of the memory cell is formed.
[0044]
A contact plug 32 made of a conductive material is embedded in the contact hole 30. A bit line 33 is formed on the interlayer insulating film 31. The bit line 33 is electrically connected to the drain diffusion layer 19d of the memory cell via the contact plug 32.
[0045]
The bit line 33 extends in the column direction. That is, the control gate layer 18 and the bit line 33 are arranged so as to cross each other vertically or substantially vertically. One memory cell is arranged at the intersection of the control gate layer 18 and the bit line 33.
[0046]
In the NAND string, two adjacent transistors (memory cell and select transistor) share one diffusion layer 19. In addition, the drain diffusion layer 19d closest to the bit line 33 in the NAND string is shared by two NAND strings in the column direction and independent of the NAND string in the row direction. The source diffusion layer 19s extends in the row direction and serves as a common source line. Accordingly, the source diffusion layer 19s is shared by two NAND strings in the column direction, and is also shared by a plurality of NAND strings in the row direction adjacent to the source diffusion layer 19s.
[0047]
Further, the element isolation insulating material 14 is not formed in the region where the source diffusion layer 19s is formed. That is, the element isolation region (element isolation insulating material) 14 is formed to extend in the column direction, but is interrupted at the source diffusion layer 19s. In addition, the drain diffusion layers 19 d of the NAND strings existing in one column are electrically connected to each other by the bit line 33.
[0048]
49 and 50 show the shapes of contact holes (bit line contacts) when the devices of FIGS. 45 to 48 are actually manufactured.
[0049]
That is, when the memory cell is miniaturized and the contact hole (bit line contact) is also miniaturized, even if the contact hole is laid out in a square shape, the shape of the resist film serving as a mask becomes circular. In some cases, the shape of the contact hole formed by etching using as a mask is also circular.
[0050]
This example merely explains that the shape of the contact hole is not limited to a square but may be a circle.
[0051]
[Problems to be solved by the invention]
Although the NOR cell type and NAND cell type nonvolatile semiconductor memory devices have been described above, the contact holes (bit line contacts) 30 are arranged in a row in the row direction in any structure.
[0052]
This is because the memory cells can be laid out with the highest density when the element regions and the element isolation regions alternately arranged in the row direction extend in the column direction and the control gate layer extends in the row direction orthogonal to the element region. Because it is considered. That is, when such a layout is adopted, the contact holes (bit line contacts) 30 are necessarily arranged in a row in the row direction.
[0053]
In this case, as shown in FIGS. 39, 40, 45 and 46, the contact holes (bit line contacts) 30 are arranged at regular intervals with a constant pitch (or a constant cycle) Xpitch. The constant pitch Xpitch is equal to the repetitive pitch (or repetitive period) Xi + Xe between the element regions and the element isolation regions alternately arranged in the row direction. This is because the contact hole and the cell drain will gradually shift if they are not at the same pitch.
[0054]
Here, element regions and element isolation regions alternately arranged in the row direction are formed by repeating so-called lines (element regions, ie, the silicon substrate 11) and spaces (element isolation regions, ie, STI (Shallow Trench Isolation)). The repetition pitch (or repetition period) Xi + Xe can be narrowed according to the performance of the exposure apparatus and the processing technique.
[0055]
The contact hole (bit line contact) 30 is made of silicon dioxide (SiO 2). ₂ ) Or the like is formed by opening a hole (hole). If the diameter of the hole itself is small, it cannot be opened well, and if the diameter is large, the interval between adjacent holes is narrowed and cannot be processed well.
[0056]
Therefore, unlike the line & space repetition cycle determined by the exposure processing technique, the pitch Xpitch of the contact holes (bit line contacts) 30 is not determined only by the exposure processing technique, but the size of the contact hole 30 itself. The distance between the contact holes 30 is also determined.
[0057]
Further, the shape of the contact hole (bit line contact) 30 is set to a square (may be circular after manufacture). Further, it is known that a square hole is more difficult to miniaturize than a line and space in terms of processing technology. That is, even if the memory cell size is reduced and the repetition pitch Xi + Xe between the element region and the element isolation region can be reduced, the contact hole 30 itself cannot be reduced. As a result, the contact hole ( The pitch Xpitch (repetitive pitch Xi + Xe between the element region and the element isolation region) 30 of the bit line contact) 30 cannot be reduced.
[0058]
Thus, conventionally, since the contact hole (in particular, the bit line contact) is square, it is difficult to make the contact hole fine. For this reason, the repetition pitch (equal to the bit line pitch) Xi + Xe between the element region and the element isolation region is limited to the contact hole pitch Xpitch, and there is a problem that the memory cell cannot be densified.
[0059]
The present invention has been made to solve the above-described drawbacks, and its purpose is to devise the shape of the contact hole, so that the pitch of the contact hole, that is, the repetition pitch of the element region and the element isolation region (bit line pitch). In other words, the memory cell can be increased in density, capacity, and cost.
[0060]
[Means for Solving the Problems]
The nonvolatile semiconductor memory device of the present invention includes an element region and an element isolation region that are repeatedly arranged in one direction at a constant period, a memory cell formed in the element region, and the same period in the one direction. A contact hole arranged periodically, and a wiring for transmitting and receiving data to and from the memory cell through the contact hole. At the top The width in the other direction perpendicular to the one direction is the width of the contact hole. At the top Wider than the width in one direction When the width in the other direction at the top of the contact hole is Y1, and the width in the other direction at the bottom of the contact hole is Y2, Y1> Y2, and the width in the other direction at the top of the contact hole. And the width in the other direction at the bottom of the contact hole changes discontinuously. .
[0074]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the nonvolatile semiconductor memory device of the present invention will be described in detail with reference to the drawings.
[0075]
[First embodiment]
1 to 4 show a memory cell array of a NOR cell type nonvolatile semiconductor memory device according to the first embodiment of the present invention. 1 and 2 are plan views of the memory cell array, FIG. 3 is a cross-sectional view taken along line III-III in FIGS. 1 and 2, and FIG. 4 is a line IV-IV in FIGS. FIG.
[0076]
For easy understanding of the drawing, FIG. 1 omits a wiring layer in which a bit line is formed, and FIG. 2 shows only a wiring layer in which a bit line is formed. That is, the bit line of FIG. 2 is formed on the device of FIG.
[0077]
In this example, a case where a memory cell array is configured using memory cells having a stacked gate structure will be described. However, it goes without saying that the present invention can also be applied to a memory cell having a single gate structure. In this example, it is assumed that the memory cell is composed of an N channel type MOS transistor.
[0078]
Hereinafter, a specific device structure will be described.
An N well region 12 and a P well region 13 are formed in the P type silicon substrate 11. The memory cell is formed in the P-type well region 13. However, the memory cell may be formed in the silicon substrate 11. In addition, a trench for element isolation is formed in the silicon substrate 11, and an element isolation insulating material (for example, silicon oxide) 14 is embedded in the trench.
[0079]
A region sandwiched between the element isolation insulating materials 14 is an element region. On the silicon substrate 11 (P well region 13) in the element region, a thin tunnel insulating film (for example, silicon oxide) 15 capable of flowing a minute tunnel current at the time of writing / erasing is formed.
[0080]
A charge transfer layer 16 is formed on the tunnel insulating film 15. The charge transfer layer 16 is composed of an electrically floating conductive layer (for example, a polysilicon layer containing impurities).
[0081]
A control gate layer 18 is formed on the charge transfer layer 16 via an intergate insulating layer 17. Since the charge transfer layer 16 and the control gate layer 18 are capacitively coupled, when the potential of the control gate layer 18 varies, the potential of the charge transfer layer 16 also varies.
[0082]
Since the charge transfer layer 16 and the control gate layer 18 are simultaneously processed in a self-aligning manner, the side edges in the direction (column direction) perpendicular to the direction (row direction) in which the control gate layer (word line) 18 extends are mutually aligned. Match. Further, the side end in the row direction of the charge transfer layer 16 exists on the element isolation insulating material 14.
[0083]
In the element region, the surface region of the silicon substrate 11 immediately below the charge transfer layer 16 is a channel region. A source diffusion layer 19s and a drain diffusion layer 19d are formed on both sides of the channel region.
[0084]
The control gate layer (word line) 18 of the memory cell extends in the row direction. On the memory cell, an interlayer insulating film (for example, silicon oxide) 31 covering the memory cell is formed. In the interlayer insulating film 31, a contact hole (bit line contact) 30 reaching the drain diffusion layer 19d of the memory cell is formed.
[0085]
The contact hole 30 is not a square but a rectangle. In this example, the width Yh of the contact hole 30 in the column direction (direction in which the bit line 33 extends) is wider than the width Xh of the contact hole 30 in the row direction (direction in which the word line 18 extends).
[0086]
The contact holes 30 are arranged in a row in the row direction, and the pitch Xpitch thereof is equal to the width Xh of the contact holes 30 in the row direction and the interval Xb between the contact holes 30. Further, the pitch Xpitch of the contact holes 30 is naturally equal to the repetitive pitch (pitch of the bit line 33) Xi + Xe between the element region and the element isolation region.
[0087]
A contact plug 32 made of a conductive material is embedded in the contact hole 30. A bit line 33 is formed on the interlayer insulating film 31. The bit line 33 is electrically connected to the drain diffusion layer 19d of the memory cell via the contact plug 32.
[0088]
The bit line 33 extends in the column direction. That is, the control gate layer 18 and the bit line 33 are arranged so as to cross each other vertically or substantially vertically. One memory cell is arranged at the intersection of the control gate layer 18 and the bit line 33.
[0089]
Further, the drain diffusion layer 19d is shared by two memory cells in the column direction, and is independent of the memory cells in the row direction. The source diffusion layer 19s extends in the row direction and serves as a common source line. Therefore, the source diffusion layer 19s is shared by two memory cells in the column direction, and is shared by a plurality of memory cells in the row direction adjacent to the source diffusion layer 19s.
[0090]
Further, the element isolation insulating material 14 is not formed in the region where the source diffusion layer 19s is formed. That is, the element isolation region (element isolation insulating material) 14 is formed to extend in the column direction, but is interrupted at the source diffusion layer 19s. The drain diffusion layers 19 d of the memory cells existing in one column are electrically connected to each other by the bit line 33.
[0091]
5 and 6 show the shape of the contact hole (bit line contact) 30 when the device of FIGS. 1 to 4 is actually manufactured.
[0092]
That is, when a memory cell is miniaturized and a contact hole (bit line contact) is also miniaturized, the shape of the resist film serving as a mask is rounded at a rectangular corner even when the contact hole is laid out in a rectangle. In some cases, the shape of the contact hole formed by etching using this as a mask is also a shape in which the corners of the rectangle are rounded.
[0093]
This example merely explains that the shape of the contact hole is not limited to a rectangle, but may be a shape in which the corners of the rectangle are rounded.
[0094]
As shown in FIGS. 1 to 6, the feature of the present invention is the shape of a contact hole (bit line contact) 30. In other words, in the present invention, the width Yh of the contact hole 30 in the column direction (the direction in which the bit line 33 extends) is wider than the width Xh of the contact hole 30 in the row direction (the direction in which the word line 18 extends).
[0095]
In general, regarding the light exposure technology, when forming a hole (for example, contact hole) resist pattern, the amount of light (exposure required for exposing the resist is higher than when forming a line & space resist pattern. The exposure condition for obtaining the optimum dimension becomes very strict.
[0096]
For example, when the pitch Xpitch of the contact holes (bit line contacts) 30 is very short, if the exposure amount is increased, the adjacent contact holes 30 are likely to be short-circuited, and conversely, if the exposure amount is reduced, sufficient exposure is achieved. Is not performed and a hole is not formed.
[0097]
On the other hand, when a line-and-space-shaped resist pattern is formed, a so-called proximity effect occurs. Therefore, the amount of light (exposure amount) necessary for exposing the resist is the same as when forming a hole-shaped resist pattern. Less than. That is, under the same conditions, the line & space shape can be made finer than the hole shape.
[0098]
The present invention pays attention to this point, and the contact hole 30, which has been square (or circular) in the past, is formed into a rectangle (or a shape in which the corners of the rectangle are rounded). It is intended to improve the processing margin.
[0099]
Specifically, in the case of a nonvolatile semiconductor memory device, the contact holes (bit line contacts) 30 are arranged in a row in the row direction (the direction in which the word lines 18 extend), so the width Xh of the contact holes 30 in the row direction. And the width Yh in the column direction of the contact hole 30 is made longer than the width Xh in the row direction. As a result, the pitch Xpitch of the contact holes 30 can be reduced, and at the same time, the width Xe of the element region and the width Xi of the element isolation region can be reduced to the minimum processing dimension of the line and space.
[0100]
That is, conventionally, the line & space pitch Xe + Xi is limited to the diameter of the contact hole 30 and the distance between the contact holes 30, and the line & space pitch Xe + Xi cannot be reduced to the minimum processing dimension. On the other hand, according to the present invention, the line & space pitch Xe + Xi is not limited by the diameter of the contact hole 30 and the distance between the contact holes 30, and the line & space pitch Xe + Xi can be reduced to the minimum processing size.
[0101]
Further, even if the width Xh in the row direction of the contact hole 30 is shortened, if the width Yh in the column direction is increased, the contact area is not reduced compared to the conventional square contact hole, and the contact resistance is also reduced. It can be kept low.
[0102]
[Second Embodiment]
7 to 10 show a memory cell array of a NAND cell type nonvolatile semiconductor memory device according to the second embodiment of the present invention. 7 and 8 are plan views of the memory cell array, FIG. 9 is a cross-sectional view taken along line IX-IX in FIGS. 7 and 8, and FIG. 10 is a cross-sectional view taken along line XX in FIGS. FIG.
[0103]
For easy understanding of the drawing, FIG. 7 omits the wiring layer in which the bit line is formed, and FIG. 8 shows only the wiring layer in which the bit line is formed. That is, the bit line of FIG. 8 is formed on the device of FIG.
[0104]
In this example, a case where a memory cell array is configured using a memory cell having a stack gate structure will be described. However, it goes without saying that the present invention can be applied to a memory cell having a single gate structure.
[0105]
A NAND cell type memory cell array has a structure in which a plurality of NAND strings (or NAND cell units) are connected to a bit line. One NAND string includes a plurality of memory cells connected in series and two select transistors connected to both ends of each memory cell.
[0106]
Hereinafter, a specific device structure will be described.
An N well region 12 and a P well region 13 are formed in the P type silicon substrate 11. The memory cell and the select transistor are formed in the P-type well region 13. However, the memory cell and the select transistor may be formed in the silicon substrate 11. In addition, a trench for element isolation is formed in the silicon substrate 11, and an element isolation insulating material (for example, silicon oxide) 14 is embedded in the trench.
[0107]
A region sandwiched between the element isolation insulating materials 14 is an element region. On the silicon substrate 11 (P well region 13) in the element region, a thin tunnel insulating film (for example, silicon oxide) 15 capable of flowing a minute tunnel current at the time of writing / erasing is formed.
[0108]
A charge transfer layer 16 is formed on the tunnel insulating film 15. The charge transfer layer 16 is composed of an electrically floating conductive layer (for example, a polysilicon layer containing impurities).
[0109]
A control gate layer 18 is formed on the charge transfer layer 16 via an intergate insulating layer 17. Since the charge transfer layer 16 and the control gate layer 18 are capacitively coupled, when the potential of the control gate layer 18 varies, the potential of the charge transfer layer 16 also varies.
[0110]
Since the charge transfer layer 16 and the control gate layer 18 are simultaneously processed in a self-aligning manner, the side edges in the direction (column direction) perpendicular to the direction (row direction) in which the control gate layer (word line) 18 extends are mutually aligned. Match. Further, the side end in the row direction of the charge transfer layer 16 exists on the element isolation insulating material 14.
[0111]
In the element region, the surface region of the silicon substrate 11 immediately below the charge transfer layer 16 is a channel region. Further, N-type diffusion layers (source region or drain region) 19 are formed on both sides of the channel region.
[0112]
The structure of the select transistor has a stack gate structure as in the memory cell. However, the select transistor does not have a charge transfer layer. For example, an upper gate and a lower gate are connected to each other and function as one gate electrode (select gate line) SG1, SG2.
[0113]
Both the control gate layer (word line) 18 and select gate lines SG1, SG2 of the memory cell extend in the row direction. On the memory cell, an interlayer insulating film (for example, silicon oxide) 31 covering the memory cell is formed. In the interlayer insulating film 31, a contact hole (bit line contact) 30 reaching the drain diffusion layer 19d of the NAND string is formed.
[0114]
The contact hole 30 is not a square but a rectangle. In this example, the width Yh of the contact hole 30 in the column direction (direction in which the bit line 33 extends) is wider than the width Xh of the contact hole 30 in the row direction (direction in which the word line 18 extends).
[0115]
The contact holes 30 are arranged in a row in the row direction, and the pitch Xpitch thereof is equal to the width Xh of the contact holes 30 in the row direction and the interval Xb between the contact holes 30. Further, the pitch Xpitch of the contact holes 30 is naturally equal to the repetitive pitch (pitch of the bit line 33) Xi + Xe between the element region and the element isolation region.
[0116]
A contact plug 32 made of a conductive material is embedded in the contact hole 30. A bit line 33 is formed on the interlayer insulating film 31. The bit line 33 is electrically connected to the drain diffusion layer 19d of the memory cell via the contact plug 32.
[0117]
The bit line 33 extends in the column direction. That is, the control gate layer 18 and the bit line 33 are arranged so as to cross each other vertically or substantially vertically. One memory cell is arranged at the intersection of the control gate layer 18 and the bit line 33.
[0118]
In the NAND string, two adjacent transistors (memory cell and select transistor) share one diffusion layer 19. In addition, the drain diffusion layer 19d closest to the bit line 33 in the NAND string is shared by two NAND strings in the column direction and independent of the NAND string in the row direction. The source diffusion layer 19s extends in the row direction and serves as a common source line. Accordingly, the source diffusion layer 19s is shared by two NAND strings in the column direction, and is also shared by a plurality of NAND strings in the row direction adjacent to the source diffusion layer 19s.
[0119]
Further, the element isolation insulating material 14 is not formed in the region where the source diffusion layer 19s is formed. That is, the element isolation region (element isolation insulating material) 14 is formed to extend in the column direction, but is interrupted at the source diffusion layer 19s. In addition, the drain diffusion layers 19 d of the NAND strings existing in one column are electrically connected to each other by the bit line 33.
[0120]
11 and 12 show the shape of the contact hole (bit line contact) 30 when the devices of FIGS. 7 to 10 are actually manufactured.
[0121]
That is, when a memory cell is miniaturized and a contact hole (bit line contact) is also miniaturized, the shape of the resist film serving as a mask is rounded at a rectangular corner even when the contact hole is laid out in a rectangle. In some cases, the shape of the contact hole formed by etching using this as a mask is also a shape in which the corners of the rectangle are rounded.
[0122]
This example merely explains that the shape of the contact hole is not limited to a rectangle, but may be a shape in which the corners of the rectangle are rounded.
[0123]
Also in the device of this example, the width Yh of the contact hole (bit line contact) 30 in the column direction (direction in which the bit line 33 extends) is larger than the width Xh of the contact hole 30 in the row direction (direction in which the word line 18 extends). It is getting wider. Accordingly, in this example as well, as described in the first embodiment, the contact hole 30 is formed into a rectangle (or a shape with rounded corners), so that the characteristics of the line and space shape, that is, Thus, the processing margin can be improved by the proximity effect.
[0124]
That is, since the contact holes (bit line contacts) 30 are arranged in a row in the row direction (the direction in which the word lines 18 extend), the width Xh of the contact hole 30 in the row direction is shortened and the contact holes 30 in the column direction are arranged. The width Yh is made longer than the width Xh in the row direction. As a result, the pitch Xpitch of the contact holes 30 can be reduced, and at the same time, the width Xe of the element region and the width Xi of the element isolation region can be reduced to the minimum processing dimension of the line and space.
[0125]
Further, even if the width Xh in the row direction of the contact hole 30 is shortened, if the width Yh in the column direction is increased, the contact area is not reduced compared to the conventional square contact hole, and the contact resistance is also reduced. It can be kept low.
[0126]
In this example, the memory cell array has a NAND cell structure. In the NAND cell structure, one contact hole (bit line contact) 30 is provided for one NAND string, and one NAND string is composed of a plurality of memory cells connected in series in the column direction. That is, the memory cell array having the NAND cell structure can reduce the number of contact holes provided in the column direction as compared with the memory cell array having the NOR cell structure.
[0127]
In the present invention, in order to reduce the width Xh of the contact hole 30 in the row direction and increase the width Yh of the contact hole 30 in the column direction, the number of contact holes provided in the column direction is reduced. This means that the increase in the area of the memory cell array by increasing the width Yh in the column direction is reduced. That is, the effect of reducing the area of the memory cell array by reducing the width Xh of the contact hole 30 in the row direction becomes significant.
[0128]
As described above, when the present invention is applied to a NAND cell type nonvolatile semiconductor memory device, the effects of the present invention are remarkably exhibited. Even if the NOR cell type shown in the first embodiment is used, the effect of area reduction can be obtained, but further, by applying the arrangement of the memory cell and the process device (self-alignment contact) described later, The effect can be increased.
[0129]
[Third Embodiment]
13 to 16 show a memory cell array of a NAND cell type nonvolatile semiconductor memory device according to the third embodiment of the present invention. 13 and 14 are plan views of the memory cell array, FIG. 15 is a cross-sectional view taken along line XV-XV in FIGS. 13 and 14, and FIG. 16 is a line XVI-XVI in FIGS. FIG.
[0130]
For easy understanding of the drawing, the wiring layer in which the bit line is formed is omitted in FIG. 13, and FIG. 14A shows only the wiring layer in which the bit line is formed, and FIG. ) Shows only the element isolation insulating material (element isolation region) 14 and the element region sandwiched between them.
[0131]
In this example, a case where a memory cell array is configured using a memory cell having a stack gate structure will be described. However, it goes without saying that the present invention can be applied to a memory cell having a single gate structure.
[0132]
A NAND cell type memory cell array has a structure in which a plurality of NAND strings (or NAND cell units) are connected to a bit line. One NAND string includes a plurality of memory cells connected in series and two select transistors connected to both ends of each memory cell.
[0133]
Hereinafter, a specific device structure will be described.
An N well region 12 and a P well region 13 are formed in the P type silicon substrate 11. The memory cell and the select transistor are formed in the P-type well region 13. However, the memory cell and the select transistor may be formed in the silicon substrate 11. In addition, a trench for element isolation is formed in the silicon substrate 11, and an element isolation insulating material (for example, silicon oxide) 14 is embedded in the trench.
[0134]
In this example, the trench for obtaining the STI structure is formed linearly without being interrupted in the column direction (see FIG. 14B). That is, the element isolation region (element isolation insulating material) 14 is completely in a line and space shape in the memory cell array region, and the accuracy of processing control and dimension control of the element isolation region and element region can be improved. .
[0135]
As will be described later, this is an effect of providing the common source line 43 on the silicon substrate 11, and as a result, the source diffusion layer 19s in the silicon substrate 11 is shared with the NAND string in the row direction. (It is shared for two NAND strings in the adjacent column direction).
[0136]
In the second embodiment described above (FIGS. 7 to 12), a common source line extending in the row direction is formed as an N-type diffusion layer 19s in the silicon substrate 11 and shared by a plurality of NAND strings in the row direction. Therefore, in this portion, the element isolation region extending in the column direction is interrupted. As a whole, in the memory cell array region, a plurality of rectangular element isolation regions are regularly arranged. ing.
[0137]
A region sandwiched between the element isolation insulating materials 14 is an element region. On the silicon substrate 11 (P well region 13) in the element region, a thin tunnel insulating film (for example, silicon oxide) 15 capable of flowing a minute tunnel current at the time of writing / erasing is formed.
[0138]
A charge transfer layer 16 is formed on the tunnel insulating film 15. The charge transfer layer 16 is composed of an electrically floating conductive layer (for example, a polysilicon layer containing impurities).
[0139]
A control gate layer 18 is formed on the charge transfer layer 16 via an intergate insulating layer 17. Since the charge transfer layer 16 and the control gate layer 18 are capacitively coupled, when the potential of the control gate layer 18 varies, the potential of the charge transfer layer 16 also varies.
[0140]
Since the charge transfer layer 16 and the control gate layer 18 are simultaneously processed in a self-aligning manner, the side edges in the direction (column direction) perpendicular to the direction (row direction) in which the control gate layer (word line) 18 extends are mutually aligned. Match. Further, the side end in the row direction of the charge transfer layer 16 exists on the element isolation insulating material 14.
[0141]
In the element region, the surface region of the silicon substrate 11 immediately below the charge transfer layer 16 is a channel region. Further, N-type diffusion layers (source region or drain region) 19 are formed on both sides of the channel region.
[0142]
The structure of the select transistor has a stack gate structure as in the memory cell. However, the select transistor does not have a charge transfer layer. For example, an upper gate and a lower gate are connected to each other and function as one gate electrode (select gate line) SG1, SG2.
[0143]
Both the control gate layer (word line) 18 and select gate lines SG1, SG2 of the memory cell extend in the row direction. On the memory cell, an interlayer insulating film (for example, silicon oxide) 31 covering the memory cell is formed. In the interlayer insulating film 31, a contact hole (bit line contact) 30 reaching the drain diffusion layer 19d of the NAND string is formed.
[0144]
In the interlayer insulating film 31, a contact hole (source line contact) 40 reaching the source diffusion layer 19s of the NAND string is formed.
[0145]
The contact holes 30 and 40 are not rectangular but rectangular. In this example, the width Yh of the contact holes 30 and 40 in the column direction (the direction in which the bit line 33 extends) is wider than the width Xh of the contact holes 30 and 40 in the row direction (the direction in which the word line 18 extends). .
[0146]
The contact holes 30 are arranged in a row in the row direction, and the pitch Xpitch thereof is equal to the width Xh of the contact holes 30 in the row direction and the interval Xb between the contact holes 30. Similarly, the contact holes 40 are arranged in a row in the row direction, and the pitch Xpitch thereof is equal to the width Xh of the contact holes 40 in the row direction and the interval Xb between the contact holes 40.
[0147]
Further, the pitch Xpitch of the contact holes 30 and 40 is naturally equal to the repetitive pitch (pitch of the bit line 33) Xi + Xe between the element region and the element isolation region. This is for associating the positions of the contact holes 30 and 40 with the positions of the source / drain diffusion layers 19s and 19d.
[0148]
The size of the contact hole 30 and the size of the contact hole 40 are preferably set to be equal to each other in consideration of processing controllability and reliability. However, if the shape of the contact hole is rectangular, the effects of the present invention can be obtained, so it goes without saying that the sizes of the two may be different from each other.
[0149]
A contact plug 32 made of a conductive material is embedded in the contact hole 30. Similarly, a contact plug 42 made of a conductive material is embedded in the contact hole 40. A common source line 43 that is electrically connected to the source diffusion layer 19s of the NAND string is formed on the interlayer insulating film 31.
[0150]
The common source line 43 is composed of, for example, a refractory metal (such as tungsten), polysilicon containing impurities, or a structure in which these are stacked.
[0151]
An interlayer insulating film (for example, silicon oxide) 41 that covers the common source line 43 is formed on the interlayer insulating film 31. A contact hole 44 reaching the contact plug 32 is formed in the interlayer insulating film 41.
[0152]
The contact hole 44 is also rectangular like the contact hole 30. That is, the width of the contact hole 44 in the column direction (direction in which the bit line 33 extends) is wider than the width of the contact hole 44 in the row direction (direction in which the word line 18 extends).
[0153]
Since the contact hole 44 is formed on the memory cell, the width of the contact hole 44 in the column direction is not particularly limited. Therefore, the contact hole 30 may have a longer side (column-direction width) longer than the column-direction width Yh of the contact hole 30 to form a further elongated contact hole. Naturally, the size of the contact hole 44 and the size of the contact hole 30 may be set to be the same.
[0154]
Since the contact holes 44 are also arranged in a row in the row direction like the contact holes 30, the pitch is equal to the pitch Xpitch of the contact holes 30. That is, the width of the contact hole 44 in the row direction and the interval between the contact holes 44 are equal to the width Xh of the contact hole 30 in the row direction and the interval Xb between the contact holes 30.
[0155]
A contact plug 45 made of a conductive material is embedded in the contact hole 44. A bit line 33 is formed on the interlayer insulating film 41. Bit line 33 is electrically connected to drain diffusion layer 19d of the memory cell via contact plugs 32 and 45.
[0156]
In this example, the contact hole 30 and the contact hole 44 on the drain diffusion layer 19d are separately formed by different processes, but instead, both contact holes are simultaneously formed as one contact hole by the same process. May be. In this case, naturally, the contact holes 30 and 44 have the same size, and the contact plugs 32 and 45 are simultaneously formed and integrated as one contact plug.
[0157]
17 and 18 show the shapes of contact holes (bit line contacts) 30 and 40 when the devices of FIGS. 13 to 16 are actually manufactured.
[0158]
That is, when the memory cell is miniaturized and the contact hole (bit line contact) 30 and the contact hole (source line contact) 40 are also miniaturized, even when the contact holes 30 and 40 are laid out in a rectangular shape, The shape of the resist film serving as a mask is a shape with rounded rectangular corners (close to an ellipse), and the contact holes 30 and 40 formed by etching using this as a mask are also rounded with rectangular corners. It may become.
[0159]
Note that this example simply explains that the shape of the contact holes 30 and 40 may be not only a rectangle but also a rounded corner of the rectangle.
[0160]
Also in the device of this example, the width Yh of the contact holes 30 and 40 in the column direction (the direction in which the bit line 33 extends) is wider than the width Xh of the contact holes 30 and 40 in the row direction (the direction in which the word line 18 extends). It has become. Therefore, in this example as well, as described in the first and second embodiments, the contact holes 30 and 40 are formed in a rectangle (or a shape in which the corners of the rectangle are rounded). It is possible to obtain the shape characteristics, that is, the processing margin can be improved by the proximity effect.
[0161]
That is, since the contact holes 30 and 40 are arranged in a row in the row direction (the direction in which the word line 18 extends), the width Xh of the contact holes 30 and 40 in the row direction is shortened and the contact holes 30 and 40 are arranged in the column direction. Is made longer than the width Xh in the row direction. As a result, the pitch Xpitch of the contact holes 30 and 40 can be reduced, and at the same time, the width Xe of the element region and the width Xi of the element isolation region can be reduced to the minimum processing dimension of the line and space.
[0162]
Even if the width Xh in the row direction of the contact holes 30 and 40 is shortened, if the width Yh in the column direction is increased, the contact area is not reduced compared to the conventional square contact hole. Resistance can be kept low.
[0163]
In this example, the memory cell array has a NAND cell structure. In the NAND cell structure, one contact hole (bit line contact) 30 and one contact hole (source line contact) 40 are provided for one NAND string. That is, the memory cell array having the NAND cell structure can reduce the number of contact holes provided in the column direction as compared with the memory cell array having the NOR cell structure.
[0164]
In the present invention, the width Xh of the contact holes 30 and 40 in the row direction is narrowed, and the width Yh of the contact holes 30 and 40 in the column direction is increased, so that the number of contact holes provided in the column direction is reduced. This means that the increase in area of the memory cell array due to the increase in the column width Yh of the contact holes 30 and 40 is reduced. That is, the effect of reducing the area of the memory cell array by reducing the width Xh of the contact holes 30 and 40 in the row direction becomes significant.
[0165]
Furthermore, in the present invention, the common source line 43 made of metal (including a refractory metal) or polysilicon is provided on the silicon substrate 11 without providing the common source line in the silicon substrate 11. Therefore, in the memory cell array region in the silicon substrate 11, the element isolation region (element isolation insulating material) 14 can be completely formed in a line and space shape, and the accuracy of dimensional control and processing control can be improved. it can. In addition, the resistance of the common source line can be reduced.
[0166]
[Fourth embodiment]
19 to 24 show a memory cell array of a NAND cell type nonvolatile semiconductor memory device according to the fourth embodiment of the present invention. 19 and 20 are plan views of the memory cell array, FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIGS. 19 and 20, and FIG. 22 is a line XXII-XXII in FIGS. FIG.
[0167]
For easy understanding of the drawing, FIG. 19 omits the wiring layer in which the bit line is formed, and FIG. 20 shows only the wiring layer in which the bit line is formed. That is, the bit line of FIG. 20 is formed on the device of FIG.
[0168]
Compared with the device of the third embodiment (FIGS. 13 to 18), the device of this example is different in the structure of the memory cell and the select transistor, and is otherwise exactly the same. . That is, in this example, the memory cell and the select transistor are configured by single gate type MOS transistors.
[0169]
Hereinafter, a specific device structure will be described.
An N well region 12 and a P well region 13 are formed in the P type silicon substrate 11. The memory cell and the select transistor are formed in the P-type well region 13. In addition, a trench for element isolation is formed in the silicon substrate 11, and an element isolation insulating material (for example, silicon oxide) 14 is embedded in the trench.
[0170]
The trench for obtaining the STI structure is formed in a straight line without interruption in the column direction (see FIG. 14B). That is, the element isolation region (element isolation insulating material) 14 has a completely line and space shape in the memory cell array region. Accordingly, it is possible to improve the accuracy of processing control and dimensional control of the element isolation region and the element region.
[0171]
A region sandwiched between the element isolation insulating materials 14 is an element region. On the silicon substrate 11 (P well region 13) in the element region, a thin tunnel insulating film (for example, silicon oxide) 15 capable of flowing a minute tunnel current at the time of writing / erasing is formed. The thickness of the tunnel insulating film 15 is set to about several nm, for example.
[0172]
On the tunnel insulating film 15, a charge holding insulating film 51 is formed. The charge holding insulating film 51 is made of, for example, silicon nitride of about several tens of nm. A charge trap level is formed at the interface between the tunnel insulating film 15 and the charge holding insulating film 51, and the state of the memory cell is determined by the amount of charges trapped in the charge trap level.
[0173]
A control gate layer (word line) 52 and select gate lines SG1, SG2 are formed on the charge holding insulating film 51. In the element region, the surface region of the silicon substrate 11 immediately below the control gate layer 52 is a channel region. N-type diffusion layers (source region or drain region) 19 are formed on both sides of the channel region. The surface region of the silicon substrate 11 immediately below the select gate lines SG1 and SG2 is also a channel region. N-type diffusion layers 19, 19s, 19d are formed on both sides of the channel region.
[0174]
Both the control gate layer (word line) 18 and select gate lines SG1, SG2 of the memory cell extend in the row direction. On the memory cell, an interlayer insulating film (for example, silicon oxide) 31 covering the memory cell is formed. In the interlayer insulating film 31, a contact hole (bit line contact) 30 reaching the drain diffusion layer 19d of the NAND string is formed.
[0175]
In the interlayer insulating film 31, a contact hole (source line contact) 40 reaching the source diffusion layer 19s of the NAND string is formed.
[0176]
The contact holes 30 and 40 are not rectangular but rectangular. In this example, the width Yh of the contact holes 30 and 40 in the column direction (the direction in which the bit line 33 extends) is wider than the width Xh of the contact holes 30 and 40 in the row direction (the direction in which the word line 18 extends). .
[0177]
The contact holes 30 are arranged in a row in the row direction, and the pitch Xpitch thereof is equal to the width Xh of the contact holes 30 in the row direction and the interval Xb between the contact holes 30. Similarly, the contact holes 40 are arranged in a row in the row direction, and the pitch Xpitch thereof is equal to the width Xh of the contact holes 40 in the row direction and the interval Xb between the contact holes 40.
[0178]
Further, the pitch Xpitch of the contact holes 30 and 40 is naturally equal to the repetitive pitch (pitch of the bit line 33) Xi + Xe between the element region and the element isolation region. This is for associating the positions of the contact holes 30 and 40 with the positions of the source / drain diffusion layers 19s and 19d.
[0179]
The size of the contact hole 30 and the size of the contact hole 40 are preferably set to be equal to each other in consideration of processing controllability and reliability. However, if the shape of the contact hole is rectangular, the effects of the present invention can be obtained, so it goes without saying that the sizes of the two may be different from each other.
[0180]
A contact plug 32 made of a conductive material is embedded in the contact hole 30. Similarly, a contact plug 42 made of a conductive material is embedded in the contact hole 40. A common source line 43 that is electrically connected to the source diffusion layer 19s of the NAND string is formed on the interlayer insulating film 31.
[0181]
An interlayer insulating film (for example, silicon oxide) 41 that covers the common source line 43 is formed on the interlayer insulating film 31. A contact hole 44 reaching the contact plug 32 is formed in the interlayer insulating film 41.
[0182]
The contact hole 44 is also rectangular like the contact hole 30. That is, the width of the contact hole 44 in the column direction (direction in which the bit line 33 extends) is wider than the width of the contact hole 44 in the row direction (direction in which the word line 18 extends).
[0183]
Since the contact hole 44 is formed on the memory cell, the width of the contact hole 44 in the column direction is not particularly limited. Therefore, the contact hole 30 may have a longer side (column-direction width) longer than the column-direction width Yh of the contact hole 30 to form a further elongated contact hole. Naturally, the size of the contact hole 44 and the size of the contact hole 30 may be set to be the same.
[0184]
Since the contact holes 44 are also arranged in a row in the row direction like the contact holes 30, the pitch is equal to the pitch Xpitch of the contact holes 30. That is, the width of the contact hole 44 in the row direction and the interval between the contact holes 44 are equal to the width Xh of the contact hole 30 in the row direction and the interval Xb between the contact holes 30.
[0185]
A contact plug 45 made of a conductive material is embedded in the contact hole 44. A bit line 33 is formed on the interlayer insulating film 41. Bit line 33 is electrically connected to drain diffusion layer 19d of the memory cell via contact plugs 32 and 45.
[0186]
In this example as well, the contact hole 30 and the contact hole 44 on the drain diffusion layer 19d are formed separately by different processes. Instead, both contact holes are simultaneously formed as one contact hole by the same process. It may be formed. In this case, naturally, the contact holes 30 and 44 have the same size, and the contact plugs 32 and 45 are simultaneously formed and integrated as one contact plug.
[0187]
23 and 24 show the shapes of contact holes (bit line contacts) 30 and 40 when the devices of FIGS. 19 to 22 are actually manufactured.
[0188]
That is, when the memory cell is miniaturized and the contact hole (bit line contact) 30 and the contact hole (source line contact) 40 are also miniaturized, even when the contact holes 30 and 40 are laid out in a rectangular shape, The shape of the resist film serving as a mask is a shape with rounded rectangular corners (close to an ellipse), and the contact holes 30 and 40 formed by etching using this as a mask are also rounded with rectangular corners. It may become.
[0189]
Note that this example simply explains that the shape of the contact holes 30 and 40 may be not only a rectangle but also a rounded corner of the rectangle.
[0190]
As described above, the device of this example is different from the device of the third embodiment only in the structure of the memory cell and the select transistor. Therefore, as a matter of course, the same effect as that of the device of the third embodiment can be obtained in the device of this example.
[0191]
[Fifth Embodiment]
25 to 30 show a memory cell array of a NAND cell type nonvolatile semiconductor memory device according to the fifth embodiment of the present invention. 25 and 26 are plan views of the memory cell array, FIG. 27 is a cross-sectional view taken along line XXVII-XXVII in FIGS. 25 and 26, and FIG. 28 is a line XXVIII-XXVIII in FIGS. FIG.
[0192]
In order to make the drawing easy to understand, FIG. 25 omits a wiring layer in which a bit line is formed, and FIG. 26 shows only a wiring layer in which a bit line is formed. That is, the bit line of FIG. 26 is formed on the device of FIG.
[0193]
Compared with the device of the third embodiment described above (FIGS. 13 to 18), the device of this example is such that the position of the contact holes 30, 40 in the column direction is self-aligned in the manufacturing process of the contact holes 30, 40. It is characterized in that a so-called self-alignment contact technique for determining is applied.
[0194]
Hereinafter, a specific device structure will be described.
An N well region 12 and a P well region 13 are formed in the P type silicon substrate 11. The memory cell and the select transistor are formed in the P-type well region 13. In addition, a trench for element isolation is formed in the silicon substrate 11, and an element isolation insulating material (for example, silicon oxide) 14 is embedded in the trench.
[0195]
In this example, the trench for obtaining the STI structure is formed linearly without being interrupted in the column direction (see FIG. 14B). That is, the element isolation region (element isolation insulating material) 14 is completely in a line and space shape in the memory cell array region, and the accuracy of processing control and dimension control of the element isolation region and element region can be improved. .
[0196]
A region sandwiched between the element isolation insulating materials 14 is an element region. On the silicon substrate 11 (P well region 13) in the element region, a thin tunnel insulating film (for example, silicon oxide) 15 capable of flowing a minute tunnel current at the time of writing / erasing is formed.
[0197]
A charge transfer layer 16 is formed on the tunnel insulating film 15. The charge transfer layer 16 is composed of an electrically floating conductive layer (for example, a polysilicon layer containing impurities).
[0198]
A control gate layer 18 is formed on the charge transfer layer 16 via an intergate insulating layer 17. Since the charge transfer layer 16 and the control gate layer 18 are capacitively coupled, when the potential of the control gate layer 18 varies, the potential of the charge transfer layer 16 also varies.
[0199]
Since the charge transfer layer 16 and the control gate layer 18 are simultaneously processed in a self-aligning manner, the side edges in the direction (column direction) perpendicular to the direction (row direction) in which the control gate layer (word line) 18 extends are mutually aligned. Match. Further, the side end in the row direction of the charge transfer layer 16 exists on the element isolation insulating material 14.
[0200]
In the element region, the surface region of the silicon substrate 11 immediately below the charge transfer layer 16 is a channel region. Further, N-type diffusion layers (source region or drain region) 19 are formed on both sides of the channel region.
[0201]
The structure of the select transistor has a stack gate structure as in the memory cell. However, the select transistor does not have a charge transfer layer. For example, an upper gate and a lower gate are connected to each other and function as one gate electrode (select gate line) SG1, SG2.
[0202]
The charge transfer layer 16 and the control gate layer (word line) 18 and the select gate lines SG1 and SG2 of the memory cell are insulating films made of a material having etching selectivity with respect to the interlayer insulating film (for example, silicon oxide) 31. (For example, silicon nitride) 60 is covered.
[0203]
On the insulating film 60, an interlayer insulating film (for example, silicon oxide) 31 that completely covers the memory cell is formed. A contact hole (bit line contact) 30 reaching the drain diffusion layer 19d of the NAND string is formed in the interlayer insulating film 31. In the interlayer insulating film 31, a contact hole (source line contact) 40 reaching the source diffusion layer 19s of the NAND string is formed.
[0204]
The contact holes 30 and 40 are not rectangular but rectangular. In this example, the width Yh1 of the contact holes 30 and 40 in the column direction (in which the bit line 33 extends) is wider than the width Xh of the contact holes 30 and 40 in the row direction (in which the word line 18 extends). .
[0205]
The contact holes 30 are arranged in a row in the row direction, and the pitch Xpitch thereof is equal to the width Xh of the contact holes 30 in the row direction and the interval Xb between the contact holes 30. Similarly, the contact holes 40 are arranged in a row in the row direction, and the pitch Xpitch thereof is equal to the width Xh of the contact holes 40 in the row direction and the interval Xb between the contact holes 40.
[0206]
Further, the pitch Xpitch of the contact holes 30 and 40 is naturally equal to the repetitive pitch (pitch of the bit line 33) Xi + Xe between the element region and the element isolation region. This is for associating the positions of the contact holes 30 and 40 with the positions of the source / drain diffusion layers 19s and 19d.
[0207]
The size of the contact hole 30 and the size of the contact hole 40 are preferably set to be equal to each other in consideration of processing controllability and reliability. However, if the shape of the contact hole is rectangular, the effects of the present invention can be obtained, so it goes without saying that the sizes of the two may be different from each other.
[0208]
The important point in this example is that the width in the column direction of the contact holes 30 and 40 is set to Yh1, but since the self-aligned contact technique is adopted, the column direction at the bottom of the contact holes 30 and 40 is used. The width Yh2 is narrower than Yh1 (Yh1 needs to be larger than Xh, but Yh2 may be larger, smaller or equal to Xh. ).
[0209]
That is, according to the present example, by making Yh1 sufficiently larger than Xh, the precision of the dimensional control and processing control of the contact holes 30 and 40 due to the proximity effect during exposure is improved, and the contact hole 30 in the row direction is improved. , 40 pitch X pitch can be narrowed to contribute to the reduction in the size of the memory cell array in the row direction.
[0210]
Further, in this example, since the self-alignment contact technique is adopted, the width Yh2 in the column direction at the bottom of the contact holes 30 and 40 is smaller than Yh1. Therefore, the distance between the select gate lines SG1 on the source side can be reduced, which can contribute to the reduction in the size of the memory cell array in the column direction.
[0211]
Needless to say, such a self-alignment contact technique can also be applied to the devices of the first, second, and fourth embodiments described above.
[0212]
A contact plug 32 made of a conductive material is embedded in the contact hole 30. Similarly, a contact plug 42 made of a conductive material is embedded in the contact hole 40. A common source line 43 that is electrically connected to the source diffusion layer 19s of the NAND string is formed on the interlayer insulating film 31.
[0213]
The common source line 43 is composed of, for example, a refractory metal (such as tungsten), polysilicon containing impurities, or a structure in which these are stacked.
[0214]
An interlayer insulating film (for example, silicon oxide) 41 that covers the common source line 43 is formed on the interlayer insulating film 31. A contact hole 44 reaching the contact plug 32 is formed in the interlayer insulating film 41.
[0215]
The contact hole 44 is also rectangular like the contact hole 30. That is, the width of the contact hole 44 in the column direction (direction in which the bit line 33 extends) is wider than the width of the contact hole 44 in the row direction (direction in which the word line 18 extends).
[0216]
Since the contact hole 44 is formed on the memory cell, the width of the contact hole 44 in the column direction is not particularly limited as in the third and fourth embodiments described above. .
[0217]
A contact plug 45 made of a conductive material is embedded in the contact hole 44. A bit line 33 is formed on the interlayer insulating film 41. Bit line 33 is electrically connected to drain diffusion layer 19d of the memory cell via contact plugs 32 and 45.
[0218]
In this example, the contact hole 30 and the contact hole 44 on the drain diffusion layer 19d are separately formed by different processes, but instead, both contact holes are simultaneously formed as one contact hole by the same process. May be. In this case, naturally, the contact holes 30 and 44 have the same size, and the contact plugs 32 and 45 are simultaneously formed and integrated as one contact plug.
[0219]
29 and 30 show the shapes of the contact holes (bit line contacts) 30 and 40 when the devices of FIGS. 25 to 28 are actually manufactured.
[0220]
That is, when the memory cell is miniaturized and the contact hole (bit line contact) 30 and the contact hole (source line contact) 40 are also miniaturized, even when the contact holes 30 and 40 are laid out in a rectangular shape, The shape of the resist film serving as a mask is a shape with rounded rectangular corners (close to an ellipse), and the contact holes 30 and 40 formed by etching using this as a mask are also rounded with rectangular corners. It may become.
[0221]
Note that this example simply explains that the shape of the contact holes 30 and 40 may be not only a rectangle but also a rounded corner of the rectangle.
[0222]
Also in the device of this example, the same effect as the device of the first to fourth embodiments described above can be obtained.
[0223]
Further, in this example, since the self-alignment contact technique is adopted, the column-direction width Yh2 at the bottom of the contact holes 30 and 40 is smaller than the column-direction width Yh1 at the top of the contact holes 30 and 40. Yes.
[0224]
That is, according to the present example, by making Yh1 sufficiently larger than Xh, the precision of the dimensional control and processing control of the contact holes 30 and 40 due to the proximity effect during exposure is improved, and the contact hole 30 in the row direction is improved. , 40 pitch X pitch can be narrowed to contribute to the reduction in the size of the memory cell array in the row direction.
[0225]
In this example, the column width Yh2 at the bottom of the contact holes 30 and 40 is smaller than the column width Yh1 at the top of the contact holes 30 and 40. For this reason, the interval between the select gate lines SG1 on the source side can be narrowed, which can contribute to the reduction in the size of the memory cell array in the column direction.
[0226]
[Relationship between Xh and Yh]
The present invention has been described based on the first to fifth embodiments. According to the present invention, the short side Xh can be opened in the case of a square by making the contact hole rectangular (including a shape with rounded corners of the rectangle; the same applies hereinafter) (Xh <Yh). It is possible to make it shorter than the length of one side of the contact hole.
[0227]
For example, assuming that the same exposure technique is used, experimentally, when the minimum exposure dimension in a line and space shape (simple repetitive pattern) is 0.2 μm, the minimum exposure dimension of a square contact hole is 0.3 μm. It becomes.
[0228]
Therefore, even if the minimum hole size that can be opened in the case of a square is 0.3 μm, the short side that can be opened has a maximum size of 0. It can be reduced to 2 μm (about 66% of the square hole size).
[0229]
Similarly, assuming that the same exposure technique is used, experimentally, when the minimum exposure size in a line and space shape (simple repetitive pattern) is 0.13 μm, the minimum exposure size of a square contact hole is 0. 2 μm.
[0230]
Therefore, even if the minimum hole size that can be opened in the case of a square is 0.2 μm, the short side that can be opened has a maximum size of 0. It can be reduced to 13 μm (about 66% of the square hole size).
[0231]
As described above, according to the present invention, by making the contact hole rectangular, the short side Xh is about 66% (about 2/3) of the minimum hole size that can be opened in the case of a square. It can be narrowed. Accordingly, the pitch of the contact holes, that is, the pitch (period) of the repeated pattern of the element region and the element isolation region can be reduced, so that the area of the memory cell array region can be greatly reduced.
[0232]
In other words, considering the row direction (the direction in which the word lines extend), the effect of reducing the area of the memory cell array region is to reduce the length of one side of the square contact hole to about 66% (about 2/3 times). When the hole shape is a rectangle that is long in the column direction (the direction in which the bit lines extend) (the length of one side of the contact hole in the column direction is not changed), that is, Yh is about 1.5 of Xh. It becomes maximum when it is doubled (about 3/2 times).
[0233]
However, if the short side Xh of the rectangular contact hole is narrowed to about 66% (about 2/3 times) the minimum hole size that can be opened in the case of a square, the long side Yh is changed to a square If the minimum hole size that can be opened is fixed (fixed value), the contact area in the case of the rectangle is reduced by about 66% compared to the case of the square, and as a result, the contact in the case of the rectangle The resistance increases to about 1.5 times (about 3/2 times) the contact resistance in the case of a square.
[0234]
Therefore, after the short side Xh becomes the minimum value (minimum exposure dimension of the line & space shape), if the long side Yh is made larger than the minimum hole size that can be opened in the case of a square, contact It is possible to suppress an increase in resistance.
[0235]
For example, when only the size of the square contact hole in the row direction (X direction) is reduced to about 66% (about 2/3 times), the contact area is also reduced to about 66% (about 2/3 times). The contact resistance increases about 3/2 times.
[0236]
Therefore, in order to maintain the same contact resistance as that of the square contact hole, it is necessary to increase the size of the contact hole in the column direction (Y direction) to about 3/2 times. At this time, Yh is approximately 2.25 times Xh ({3/2} / {2/3} = {9/4} times).
[0237]
Moreover, it is difficult to completely match Yh to 2.25 times Xh due to processing variations during manufacturing. Therefore, in consideration of such processing variations during manufacturing, when Yh is not less than 2 times and not more than 2.5 times Xh, the effect of area reduction can be maximized without increasing contact resistance. .
[0238]
By the way, the size Yh of the contact hole in the column direction cannot be increased infinitely (when Yh becomes infinite, a complete line and space is obtained). Actually (considering self-alignment contact), the maximum value of Yh is considered to be about three times the minimum processing dimension of the line and space (for example, equal to the width of the word line).
[0239]
Here, assuming that Xh is set to the minimum processing dimension of the line and space (for example, the width of the element region and the width of the element isolation region are also set to this minimum processing dimension), the maximum value of Yh Is three times Xh.
[0240]
In summary, when Yh is in the practical range of 1.5 to 3 times Xh and Yh is 2 to 2.5 times Xh, the contact resistance The effect of area reduction can be maximized without an increase.
However, if the chip size in the column direction is ignored and the chip layout allows, Yh may exceed 3 times Xh if possible.
[0241]
[Others]
The present invention is not limited to the NOR cell type and NAND cell type non-volatile semiconductor memory devices as described above. In particular, the bit line pitch (period) or the repetition pitch (period) between the element region and the element isolation region is 0. The effect is great when applied to a nonvolatile semiconductor memory device of 5 μm or less.
[0242]
The present invention also relates to all nonvolatile semiconductor memory devices in which contact holes (bit line contacts or source line contacts) are arranged in a line at the same pitch as the pitch of bit lines (or a repetition pitch of element regions and element isolation regions). It is applicable to.
[0243]
Further, according to the present invention, as shown in the above-described embodiment, the size Xh of the contact hole in the row direction is equal to the size Xe of the element region in the row direction, the distance Xb between the contact holes and the row direction of the element isolation region Not only when the sizes Xi are equal, but also as shown in FIGS. 31 and 32, the size Xh of the contact holes in the row direction is larger than the size Xe of the element regions in the row direction, and the distance Xb between the contact holes is the element isolation region. It can also be applied to a case where the size is smaller than the row size Xi.
[0244]
The present invention is also applicable to the case where the size Xh of the contact hole in the row direction is smaller than the size Xe of the element region in the row direction, and the distance Xb between the contact holes is larger than the size Xi of the element isolation region in the row direction. it can.
The present invention can be variously modified without departing from the gist thereof.
[0245]
【The invention's effect】
As described above, according to the present invention, in the nonvolatile semiconductor memory device in which the contact holes need to be arranged in a line in one direction at a constant pitch (period), the shape of the contact holes is rectangular or rectangular. And the width of one direction (row direction) of the contact hole is narrower than the width of the direction perpendicular to the one direction (column direction).
[0246]
In this case, the width (short side) in one direction of the contact hole can be narrower than the minimum processing size of the square contact hole, and can be reduced to the maximum processing size of the line and space at the maximum. Accordingly, the contact hole pitch in one direction can be narrowed while maintaining the precision of contact hole dimensional control and processing control, thereby contributing to the reduction of the element region and the reduction of the chip area.
[0247]
Further, regarding the width of the contact hole in the direction perpendicular to the one direction, in particular, by adopting the self-alignment contact technology, even if the width in the direction perpendicular to the one direction is increased, While maintaining the accuracy of processing control, it is possible to reduce the element region and the chip area in the direction orthogonal to the one direction.
[0248]
Furthermore, if the width of the contact hole in the direction perpendicular to the one direction is 1.5 times or more the width of the contact hole in the one direction, the phenomenon of contact resistance increase due to the effect of area reduction can be prevented. Therefore, it is possible to take measures to reduce the contact resistance by increasing the contact area while maintaining the effect of reducing the area.
[Brief description of the drawings]
FIG. 1 is a plan view showing a memory cell array of a NOR cell type nonvolatile semiconductor memory device according to a first embodiment of the present invention.
2 is a plan view showing a bit line formed on the device of FIG. 1; FIG.
3 is a cross-sectional view taken along line III-III in FIGS. 1 and 2. FIG.
4 is a cross-sectional view taken along line IV-IV in FIGS. 1 and 2. FIG.
5 is a view showing a shape of a contact hole when the device of FIGS. 1 and 2 is actually manufactured. FIG.
6 is a view showing a shape of a contact hole when the device of FIGS. 1 and 2 is actually manufactured. FIG.
FIG. 7 is a plan view showing a memory cell array of a NAND cell nonvolatile semiconductor memory device according to a second embodiment of the present invention.
8 is a plan view showing a bit line formed on the device of FIG. 7;
9 is a cross-sectional view taken along line IX-IX in FIGS. 7 and 8. FIG.
10 is a cross-sectional view taken along line XX in FIGS. 7 and 8. FIG.
11 is a view showing the shape of a contact hole when the device of FIGS. 7 and 8 is actually manufactured. FIG.
12 is a view showing a shape of a contact hole when the device of FIGS. 7 and 8 is actually manufactured. FIG.
FIG. 13 is a plan view showing a memory cell array of a NAND cell type nonvolatile semiconductor memory device according to a third embodiment of the present invention.
14 is a plan view showing a bit line and an element isolation region in the device of FIG.
15 is a cross-sectional view taken along line XV-XV in FIGS. 13 and 14. FIG.
16 is a cross-sectional view taken along line XVI-XVI in FIGS. 13 and 14. FIG.
17 is a view showing a shape of a contact hole when the device shown in FIGS. 13 and 14 is actually manufactured. FIG.
18 is a view showing a shape of a contact hole when the device of FIGS. 13 and 14 is actually manufactured. FIG.
FIG. 19 is a plan view showing a memory cell array of a NAND cell type nonvolatile semiconductor memory device according to a fourth embodiment of the present invention.
20 is a plan view showing a bit line formed on the device of FIG. 19;
21 is a sectional view taken along line XXI-XXI in FIGS. 19 and 20. FIG.
22 is a sectional view taken along line XXII-XXII in FIGS. 19 and 20. FIG.
23 is a view showing a shape of a contact hole when the device of FIGS. 19 and 20 is actually manufactured. FIG.
24 is a view showing the shape of a contact hole when the device of FIGS. 19 and 20 is actually manufactured. FIG.
FIG. 25 is a plan view showing a memory cell array of a NAND cell nonvolatile semiconductor memory device according to a fifth embodiment of the present invention.
26 is a plan view showing a bit line formed on the device of FIG. 25. FIG.
27 is a sectional view taken along line XXVII-XXVII in FIGS. 25 and 26. FIG.
28 is a sectional view taken along line XXVIII-XXVIII in FIGS. 25 and 26. FIG.
29 is a view showing a shape of a contact hole when the device of FIGS. 25 and 26 is actually manufactured. FIG.
30 is a view showing a shape of a contact hole when the device of FIGS. 25 and 26 is actually manufactured. FIG.
FIG. 31 is a plan view showing a modification of the memory cell array of the NOR cell type nonvolatile semiconductor memory device of the present invention.
FIG. 32 is a plan view showing a modification of the memory cell array of the NAND cell nonvolatile semiconductor memory device of the present invention.
FIG. 33 is a plan view showing a device structure of a stacked gate type memory cell;
34 is a sectional view taken along line XXXIV-XXXIV in FIG. 33. FIG.
35 is a sectional view taken along line XXXV-XXXV in FIG. 33. FIG.
FIG. 36 is a plan view showing a device structure of a single gate type memory cell;
FIG. 37 is a cross-sectional view taken along line XXXVII-XXXVII in FIG.
38 is a sectional view taken along line XXXVIII-XXXVIII in FIG. 36. FIG.
FIG. 39 is a plan view showing a memory cell array of a conventional NOR cell type nonvolatile semiconductor memory device.
40 is a plan view showing a bit line formed on the device of FIG. 39. FIG.
41 is a cross-sectional view taken along line XLI-XLI in FIGS. 39 and 40. FIG.
42 is a sectional view taken along line XLII-XLII in FIGS. 39 and 40. FIG.
43 is a view showing a shape of a contact hole when the device of FIGS. 39 and 40 is actually manufactured. FIG.
44 is a view showing the shape of a contact hole when the device of FIGS. 39 and 40 is actually manufactured. FIG.
FIG. 45 is a plan view showing a memory cell array of a conventional NAND cell type nonvolatile semiconductor memory device.
46 is a plan view showing a bit line formed on the device of FIG. 45. FIG.
47 is a sectional view taken along line XLVII-XLVII in FIGS. 45 and 46. FIG.
48 is a sectional view taken along the line XLVIII-XLVIII in FIGS. 45 and 46. FIG.
49 is a view showing the shape of a contact hole when the device of FIGS. 45 and 46 is actually manufactured. FIG.
50 is a view showing the shape of a contact hole when the device of FIGS. 45 and 46 is actually manufactured. FIG.
[Explanation of symbols]
11, 21: P-type silicon substrate,
12, 22: N-type well region,
13, 23: P-type well region,
14, 24: Insulating material for element isolation (element isolation region),
15, 25: Tunnel insulating film,
16: charge transfer layer,
17: Insulating layer between gates,
18, 27, 52: control gate layer,
19, 28: N-type diffusion layer,
19d: drain diffusion layer,
19s: source diffusion layer,
26: an insulating film for charge retention,
30, 44: contact hole (bit line contact),
31, 41: Interlayer insulating film,
32, 42, 45: contact plug,
33: bit line,
40: contact hole (source line contact),
43: Common source line,
51: An insulating film for charge retention.

Claims (5)

An element region and an element isolation region that are repeatedly arranged in one direction at a constant period; a memory cell formed in the element region; a contact hole that is disposed in the one direction at the same period as the constant period; through a contact hole and a wiring for transferring the memory cell and the data, the other direction of the width orthogonal to the one direction in the upper portion of the contact hole is than the one direction of the width at the top of the contact hole widely, wherein the upper portion of the contact hole other direction width Y1, when the other direction of the width Y2 at the bottom of the contact hole, a Y1> Y2, the other direction in an upper portion of the contact hole wherein the width and the bottom of the contact hole other direction width, nonvolatile semiconductive, characterized in that changes discontinuously Storage device. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the width in the other direction at the upper part of the contact hole is 1.5 times or more the width in the one direction at the upper part of the contact hole. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the width in the other direction at the upper part of the contact hole is not more than three times the width in the one direction at the upper part of the contact hole. 2. The non-volatile semiconductor memory according to claim 1, wherein the width in the other direction at the upper part of the contact hole is not less than 2 times and not more than 2.5 times the width in the one direction at the upper part of the contact hole. apparatus. The memory cell includes a gate insulating film formed on the element region, a charge transfer layer formed on the gate insulating film, an inter-gate insulating layer formed on the charge transfer layer, and the gate The nonvolatile semiconductor memory device according to claim 1, further comprising a control gate layer formed on the insulating layer .

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