JP2001168304A - Non-volatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make bit lines narrow in pitch go as to enhance a cell array in degree of integration. SOLUTION: Element isolation regions 14 extend in the column direction, and control gate layers (word line) 18 extend in the row direction. Contact holes 30 are each formed like a rectangle, where the long side and short, side of the rectangle are parallel to the column direction and the row direction respectively. The width Xh of the hole 30 in the row direction is shortened, by which the pitch Xpitch of the contact holes can be shortened. The contact hole 30 is rectangular itself, so that it can be more accurately controlled in dimension and processing than a case in which it is square. Xpitch is equal to the repetitive pitch Xe and Xi of an element region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to an improvement in a cell layout of a high-density type and highly integrated nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art An electrically rewritable nonvolatile semiconductor memory device is widely used for high-speed ROM and mass storage. In addition, a memory cell of a nonvolatile semiconductor memory device is generally formed of a MOS transistor. As a memory cell structure, a stack gate structure having a charge transfer layer and a control gate layer, and a single gate structure including only a control gate layer are generally used.

FIGS. 33 to 35 show an example of a memory cell having a stack gate structure. FIG. 33 is a plan view of a memory cell, and FIG. 34 is a XXXI of FIG.
35 is a sectional view taken along a line V-XXXIV, and FIG.
FIG. 3 is a sectional view taken along line XXXV-XXXV of FIG.

In this example, a memory cell is an N-channel type M
It is composed of an OS transistor. In this case, the memory cell is formed in the P-type silicon substrate or the P-type well region. In this example, the memory cells are formed in the P-type well region.

Specifically, an N-well region 12 and a P-well region 13 are formed in a P-type silicon substrate 11. A trench for element isolation is formed in the silicon substrate 11, and an insulating material for element isolation (for example, silicon oxide) 14 is embedded in the trench.

The region sandwiched between the element isolation insulating materials 14 is an element region. Silicon substrate 1 in element region
On the 1 (P-well region 13), a thin tunnel insulating film (for example, silicon oxide) 15 that allows a small tunnel current to flow at the time of writing / erasing is formed.

The charge transfer layer 1 is formed on the tunnel insulating film 15.
6 are formed. The charge transfer layer 16 is formed of an electrically floating conductive layer (for example, a polysilicon layer containing impurities).

On the charge transfer layer 16, an inter-gate insulating layer 1
Through 7, the control gate layer 18 is formed. Since the charge transfer layer 16 and the control gate layer 18 are capacitively coupled, when the potential of the control gate layer 18 changes, the potential of the charge transfer layer 16 also changes.

The charge transfer layer 16 and the control gate layer 18 are
Since they are simultaneously processed in a self-aligned manner, the side ends in the direction (column direction) perpendicular to the direction (row direction) in which the control gate layer (word line) 18 extends coincide with each other. Also,
The side end in the row direction of the charge transfer layer 16 is present on the element isolation insulating material 14.

In the element region, a surface region of the silicon substrate 11 immediately below the charge transfer layer 16 is a channel region. An N-type diffusion layer (source region or drain region) 19 is formed on both sides of the channel region.

In the memory cell having the above-described stack gate structure, data of the memory cell is stored in the charge transfer layer 16.
Is determined by the amount of charge in In other words, the threshold value of the memory cell is such that if the amount of negative charges (electrons) in the charge
It becomes higher and increases as the number of positive charges (holes) in the charge transfer layer 16 increases.

A state in which the charge transfer layer 16 has a large amount of negative charges is called a write state, and a state in which the charge transfer layer 16 has a large amount of positive charges is called an erased state.

The amount of charge in the charge transfer layer 16 is determined by
At the time of the erase operation, it can be adjusted by flowing a tunnel current through the tunnel insulating film 15. Whether or not a tunnel current flows is determined by a voltage applied between the control gate layer (charge transfer layer) and the channel. That is, when a high voltage is applied to the tunnel insulating film 15, a tunnel current flows.

For example, when a high voltage is applied to the tunnel insulating film 15 and the potential of the channel is higher than the potential of the charge transfer layer, the tunnel current flows from the channel toward the charge transfer layer. When a high voltage is applied to the tunnel insulating film 15 and the potential of the charge transfer layer is higher than the potential of the channel, the tunnel current flows from the charge transfer layer toward the channel.

FIGS. 36 to 38 show an example of a memory cell having a single gate structure. FIG. 36 is a plan view of a memory cell, and FIG. 37 is a XXXV of FIG.
FIG. 38 is a cross-sectional view taken along the line II-XXXVII,
FIG. 37 is a cross-sectional view of FIG. 36 taken along the line XXXVIII-XXXVIII.

Also in this example, the memory cell is formed of an N-channel MOS transistor. In this case, the memory cell is formed in the P-type silicon substrate or the P-type well region. However, in this example, the memory cells are formed in the P-type well region.

Specifically, an N-well region 22 and a P-well region 23 are formed in a P-type silicon substrate 21. A trench for element isolation is formed in the silicon substrate 21, and an insulating material for element isolation (for example, silicon oxide) 24 is buried in the trench.

The region sandwiched between the element isolation insulating materials 24 is an element region. Silicon substrate 2 in element region
On the 1 (P-well region 23), a thin tunnel insulating film (for example, silicon oxide) 25 capable of flowing a small tunnel current at the time of writing / erasing is formed.

On the tunnel insulating film 25, a charge holding insulating layer 2 for holding a charge and suppressing a charge loss.
6 are formed. The charge retaining insulating layer 26 is formed, for example, by stacking a plurality of insulating materials.

On the charge retaining insulating layer 26, a control gate layer 27 is formed. In the element region, the surface region of the silicon substrate 21 immediately below the control gate layer 27 is a channel region. On both sides of the channel region, an N-type diffusion layer (source region or drain region) 28 is formed.

In the memory cell having the single gate structure described above, the data of the memory cell is determined by the amount of charge trapped at the charge trap level formed at the interface between the tunnel insulating film 25 and the charge retaining insulating layer 26. You.
That is, the threshold value of the memory cell increases as the number of negative charges (electrons) trapped in the charge trap level increases, and decreases as the number of positive charges (holes) trapped in the charge trap level increases. .

A state in which a large amount of negative charges are trapped in the charge trap level is called a write state, and a state in which a large amount of positive charges are trapped in the charge trap level is called an erase state.

Tunnel insulating film 25 and charge retaining insulating layer 2
The charge amount of the charge trap level formed at the interface of No. 6 can be adjusted by flowing a tunnel current through the tunnel insulating film 25 during a write / erase operation. Whether or not the tunnel current flows is determined by the voltage applied between the control gate layer and the channel. That is, when a high voltage is applied to the tunnel insulating film 25, a tunnel current flows.

For example, when a high voltage is applied to the tunnel insulating film 25 and the potential of the channel is higher than the potential of the control gate layer, the tunnel current flows from the channel to the charge holding insulating layer. When a high voltage is applied to the tunnel insulating film 25 and the potential of the control gate layer is higher than the potential of the channel, the tunnel current flows from the charge holding insulating layer toward the channel.

In the memory cell having the single gate structure, a charge transfer insulating layer is provided between the tunnel insulating film 25 and the charge holding insulating layer 26, and the state (data) of the memory cell is transferred to the charge transfer insulating layer. The determination may be made based on the trapped charge amount.

FIGS. 39 to 42 show a memory cell array of a NOR cell type nonvolatile semiconductor memory device. 39 and 40 are plan views of the memory cell array.
FIG. 41 is a cross-sectional view taken along the line XLI-XLI in FIGS. 39 and 40, and FIG. 42 is a XLII in FIGS. 39 and 40.
It is sectional drawing which follows the -XLII line.

In order to make the drawing easier to understand, FIG.
In FIG. 40, a wiring layer on which bit lines are formed is omitted, and FIG. 40 shows only a wiring layer on which bit lines are formed. That is, the bit line in FIG. 40 is formed on the device in FIG.

In this example, a case where a memory cell array is formed using memory cells having a stack gate structure will be described. Naturally, a similar layout can be adopted even for a memory cell having a single gate structure. it can.

The structure of the memory cell has been described with reference to FIGS.

Control gate layer (word line) 1 of memory cell
8 extends in the row direction. On the memory cell, an interlayer insulating film (for example, silicon oxide) 31 covering the memory cell 31
Is formed. A contact hole (bit line contact) 30 reaching the drain diffusion layer 19d of the memory cell is formed in the interlayer insulating film 31.

In the contact hole 30, a contact plug 32 made of a conductive material is buried. Then, a bit line 33 is formed on the interlayer insulating film 31. The bit line 33 is electrically connected to the drain diffusion layer 19d of the memory cell via the contact plug 32.

The bit line 33 extends in the column direction. That is, the control gate layer 18 and the bit line 33 are arranged so as to intersect each other vertically or substantially vertically. One memory cell is arranged at the intersection of the control gate layer 18 and the bit line 33.

The drain diffusion layer 19d has a width of 2 in the column direction.
One memory cell is shared, and the memory cells in the row direction are independent of each other. The source diffusion layer 19 s
It extends in the row direction and serves as a common source line. Therefore,
The source diffusion layer 19s is shared by two memory cells in the column direction, and is also shared by a plurality of memory cells in the row direction adjacent to the source diffusion layer 19s.

The element isolation insulating material 14 is not formed in a region where the source diffusion layer 19s is formed. That is, the element isolation region (element isolation insulating material) 14 is formed so as to extend in the column direction.
Is interrupted at the part. The drain diffusion layer 19d of the memory cell existing in one column is connected to the bit line 33.
Are electrically connected to each other.

FIGS. 43 and 44 show the shapes of the contact holes (bit line contacts) when the device shown in FIGS. 39 to 42 is actually manufactured.

That is, when memory cells are miniaturized and contact holes (bit line contacts) are also miniaturized, the shape of the resist film serving as a mask becomes circular even when the contact holes are laid out in a square shape. The shape of the contact hole formed by etching using this as a mask may be circular.

This example explains that the shape of the contact hole may be not only a square but also a circle.

FIGS. 45 to 48 show a memory cell array of a NAND cell type nonvolatile semiconductor memory device.
45 and 46 are plan views of the memory cell array, and FIG. 47 is a XLVII-XLV of FIG. 45 and FIG.
FIG. 48 is a sectional view taken along a line II, and FIGS.
FIG. 6 is a sectional view taken along line XLVIII-XLVIII of FIG.

In order to make the drawing easier to understand, FIG.
In FIG. 46, the wiring layer on which the bit line is formed is omitted, and FIG. 46 shows only the wiring layer on which the bit line is formed. That is, the bit line of FIG. 46 is formed on the device of FIG.

In this example, a case will be described in which a memory cell array is formed by using memory cells having a stacked gate structure. Naturally, a similar layout can be adopted even for a memory cell having a single gate structure. it can.

A NAND cell type memory cell array is composed of a plurality of NAND strings (or NAND cell units).
Have a structure connected to a bit line. One NAND
The string includes a plurality of memory cells connected in series and two select transistors connected one at each end.

The structure of the memory cell has been described with reference to FIGS. The structure of the select transistor has a stack gate structure, like the memory cell. However, the select transistor does not have a charge transfer layer. For example, the upper gate and the lower gate are connected to each other, and function as one gate electrode (select gate line) SG1, SG2.

Control gate layer (word line) 1 of memory cell
8 and select gate lines SG1 and SG2 both extend in the row direction. On the memory cell, an interlayer insulating film (for example, silicon oxide) 31 covering the memory cell is formed. A contact hole (bit line contact) 30 reaching the drain diffusion layer 19d of the memory cell is formed in the interlayer insulating film 31.

In the contact hole 30, a contact plug 32 made of a conductive material is buried. Then, a bit line 33 is formed on the interlayer insulating film 31. The bit line 33 is electrically connected to the drain diffusion layer 19d of the memory cell via the contact plug 32.

The bit line 33 extends in the column direction. That is, the control gate layer 18 and the bit line 33 are arranged so as to intersect each other vertically or substantially vertically. One memory cell is arranged at the intersection of the control gate layer 18 and the bit line 33.

In the NAND string, two adjacent transistors (memory cells and select transistors) share one diffusion layer 19. The drain diffusion layer 19d closest to the bit line 33 in the NAND string is shared by the two NAND strings in the column direction, and is independent of the NAND strings in the row direction. The source diffusion layer 19 s
It extends in the row direction and serves as a common source line. Therefore,
The source diffusion layer 19s is shared by two NAND strings in the column direction and is also shared by a plurality of NAND strings in the row direction adjacent to the source diffusion layer 19s.

The element isolation insulating material 14 is not formed in a region where the source diffusion layer 19s is formed. That is, the element isolation region (element isolation insulating material) 14 is formed so as to extend in the column direction.
Is interrupted at the part. Further, the drain diffusion layers 19 d of the NAND strings existing in one column are electrically connected to each other by the bit line 33.

FIGS. 49 and 50 show the shapes of the contact holes (bit line contacts) when the device shown in FIGS. 45 to 48 is actually manufactured.

That is, when memory cells are miniaturized and contact holes (bit line contacts) are also miniaturized, the resist film serving as a mask has a circular shape even when the contact holes are laid out in a square shape. The shape of the contact hole formed by etching using this as a mask may be circular.

This example explains that the shape of the contact hole may be not only a square but also a circle.

[0051]

Although the NOR cell type and the NAND cell type non-volatile semiconductor memory devices have been described above, the contact hole (bit line contact) 30 is formed in the row direction in any structure. They are arranged in a line.

This is because the element regions and the element isolation regions alternately arranged in the row direction extend in the column direction, and the control gate layer extends in the row direction orthogonal to the element region.
This is because the memory cells can be laid out at the highest density. That is, if such a layout is adopted, the contact holes (bit line contacts) 30
Are inevitably arranged in a row in the row direction.

In this case, as shown in FIGS. 39, 40, 45 and 46, the contact hole (bit line contact) 30 has a constant pitch (or constant period) Xpitc.
h and are arranged at equal intervals. And this constant pitch Xp
Itch is a repetition pitch (or repetition period) Xi of element regions and element isolation regions alternately arranged in the row direction.
+ Xe. This is because if the pitch is not the same, the contact hole and the drain of the cell gradually shift.

Here, the element region and the element isolation region alternately arranged in the row direction include a so-called line (element region, ie, silicon substrate 11) and a space (element isolation region, ie, STI (Shallow Trench Isolation)). And its repetition pitch (or repetition period) Xi
+ Xe can be narrowed according to the performance of the exposure apparatus and the processing technique.

Contact hole (bit line contact)
30 is formed by opening a hole (hole) in an interlayer insulating film made of silicon dioxide (SiO ₂ ) or the like. If the diameter of this hole itself is small, it cannot be opened well,
If the diameter is large, the distance between adjacent holes will be narrow,
It cannot be processed well.

Therefore, unlike the repetition period of the line and space determined by the exposure processing technique, the pitch Xpitch of the contact hole (bit line contact) 30 is different.
Is determined not only by the exposure processing technique but also by the size of the contact holes 30 themselves and the distance between the contact holes 30.

The shape of the contact hole (bit line contact) 30 is set to a square (it may be circular after manufacture). It is known that a square hole is more difficult to miniaturize than a line and space in terms of processing technology. In other words, even if the size of the memory cell is reduced and the repetition pitch Xi + Xe between the element region and the element isolation region can be reduced, the contact hole 30 itself cannot be reduced. As a result, the contact hole ( This means that the pitch Xpitch of the bit line contact 30 (the repetition pitch Xi + Xe between the element region and the element isolation region) cannot be reduced.

As described above, conventionally, since the contact hole (particularly, the bit line contact) is square,
It was difficult to miniaturize the contact hole. For this reason,
The repetition pitch (equal to the pitch of the bit lines) Xi + Xe between the element region and the element isolation region is limited by the pitch Xpitch of the contact holes, and there is a problem that a high density of memory cells cannot be achieved.

The present invention has been made in order to solve the above-mentioned drawbacks. The object of the present invention is to improve the shape of the contact hole so that the pitch of the contact hole, that is, the repetition pitch of the element region and the element isolation region (bit (Equal to the line pitch), thereby achieving high density, large capacity, and low cost memory cells.

[0060]

According to the present invention, there is provided a nonvolatile semiconductor memory device comprising: an element region and an element isolation region which are repeatedly arranged in one direction at a constant period; a memory cell formed in the element region; A contact hole arranged in the one direction at the same period as the constant period, and a wiring for transmitting and receiving data to and from the memory cell through the contact hole, wherein the contact hole is provided in the other direction orthogonal to the one direction. The width is wider than the width of the contact hole in the one direction.

The width of the contact hole in the other direction is at least 1.5 times the width of the contact hole in the one direction. Further, the width of the contact hole in the other direction is not more than three times the width of the contact hole in the one direction, and the width of the contact hole in the one direction is smaller than the width of the element region in the one direction. Roughly equal.

The optimal range of the size of the contact hole is such that the width of the contact hole in the other direction is at least twice and at most 2.5 times the width of the contact hole in the one direction. Range.

The wiring is a bit line, and the bit line is connected to one end of a current path of the memory cell.
The other end of the current path of the memory cell is connected to a source line, and a control gate line of the memory cell extending in the one direction is arranged between the contact hole and the source line.

The wiring is a bit line, and the bit line is connected to one end of a current path of the memory cell via at least one transistor. The other end of the current path of the memory cell is connected to a source line via at least one transistor, and at least one control gate line extending in the one direction is arranged between the contact hole and the source line. Is done.

The memory cell is composed of a MOS transistor having a stack gate structure, and the MOS transistor has a charge transfer layer for transferring charges to and from a channel.

The memory cell is constituted by a MOS transistor having a single gate structure. The MOS transistor includes a gate insulating film in which two layers are stacked, and charges are stored between the two layers.

The wiring is a source line, and the source line is connected to one end of a current path of the memory cell.

The wiring is a source line, and the source line is connected to one end of a current path of the memory cell via at least one transistor.

The width in the other direction of the contact hole is the width in the other direction above the contact hole, the width in the other direction above the contact hole is Y1, and the width in the bottom of the contact hole is Y1. When the width in the direction is Y2, Y1> Y2, and
Further, the width in the other direction at the top of the contact hole and the width in the other direction at the bottom of the contact hole vary discontinuously.

The device region and the device isolation region extend in the other direction, and the width of the device region and the device isolation region in the one direction is substantially equal to the width of the contact hole in the one direction.

The width in the one direction of the element region and the element isolation region is substantially equal to the width of a control gate line of the memory cell.

A nonvolatile semiconductor memory device according to the present invention includes an element region and an element isolation region that are repeatedly arranged in one direction at a constant period, a memory cell formed in the element region, A first contact hole arranged at substantially the same cycle as a cycle, a bit line connected to one end of a current path of the memory cell via the first contact hole and at least one transistor, and the constant in the one direction. A second contact hole arranged at substantially the same cycle as a cycle; and a source line connected to the other end of the current path of the memory cell via the second contact hole and at least one transistor. The width of the second contact hole in the other direction orthogonal to the one direction is larger than the width of the second contact hole in the one direction.

The size of the first contact hole is substantially equal to the size of the second contact hole.

[0074]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a nonvolatile semiconductor memory device according to the present invention will be described in detail with reference to the drawings.

[First Embodiment] FIGS. 1 to 4 show a memory cell array of a NOR cell type nonvolatile semiconductor memory device according to a first embodiment of the present invention. 1 and 2 are plan views of a memory cell array, and FIG.
FIG. 4 is a sectional view taken along line III-III of FIG.
FIG. 4 is a sectional view taken along the line IV-IV in FIGS. 1 and 2.

For simplicity of the drawing, a wiring layer in which bit lines are formed is omitted in FIG. 1, and FIG.
Only the wiring layer where the bit lines are formed is shown. That is, the bit line of FIG. 2 is formed on the device of FIG.

In this example, a case where a memory cell array is formed using memory cells having a stack gate structure will be described. However, it goes without saying that the present invention can also be applied to a memory cell having a single gate structure. In this example, the memory cell is an N-channel type M
It is assumed that it is composed of an OS transistor.

Hereinafter, a specific device structure will be described. An N-well region 12 is provided in a P-type silicon substrate 11.
And a P-well region 13 are formed. Then, the memory cell is formed in the P-type well region 13. However, the memory cells may be formed in the silicon substrate 11. A trench for element isolation is formed in the silicon substrate 11, and an insulating material for element isolation (for example, silicon oxide) 14 is embedded in the trench.

The region sandwiched between the element isolation insulating materials 14 becomes the element region. Silicon substrate 1 in element region
On the 1 (P-well region 13), a thin tunnel insulating film (for example, silicon oxide) 15 that allows a small tunnel current to flow at the time of writing / erasing is formed.

The charge transfer layer 1 is formed on the tunnel insulating film 15.
6 are formed. The charge transfer layer 16 is formed of an electrically floating conductive layer (for example, a polysilicon layer containing impurities).

On the charge transfer layer 16, the inter-gate insulating layer 1
Through 7, the control gate layer 18 is formed. Since the charge transfer layer 16 and the control gate layer 18 are capacitively coupled, when the potential of the control gate layer 18 changes, the potential of the charge transfer layer 16 also changes.

The charge transfer layer 16 and the control gate layer 18
Since they are simultaneously processed in a self-aligned manner, the side ends in the direction (column direction) perpendicular to the direction (row direction) in which the control gate layer (word line) 18 extends coincide with each other. Also,
The side end in the row direction of the charge transfer layer 16 is present on the element isolation insulating material 14.

In the element region, the surface region of the silicon substrate 11 immediately below the charge transfer layer 16 is a channel region. A source diffusion layer 19s and a drain diffusion layer 19d are formed on both sides of the channel region.

Control gate layer (word line) 1 of memory cell
8 extends in the row direction. On the memory cell, an interlayer insulating film (for example, silicon oxide) 31 covering the memory cell 31
Is formed. A contact hole (bit line contact) 30 reaching the drain diffusion layer 19d of the memory cell is formed in the interlayer insulating film 31.

The contact hole 30 is not a square but a rectangle. In this example, the width Y of the contact hole 30 in the column direction (the direction in which the bit line 33 extends)
h is in the row direction of the contact hole 30 (word line 18).
(Extending direction) is wider than the width Xh.

The contact holes 30 are arranged in a row in the row direction. The pitch Xpitch is determined by the width Xh of the contact hole 30 in the row direction and the contact hole 30.
It is equal to the interval Xb between them. Also, the pitch Xpitch of the contact hole 30 is naturally equal to the repetition pitch (pitch of the bit line 33) Xi + Xe between the element region and the element isolation region.

In the contact hole 30, a contact plug 32 made of a conductive material is buried. Then, a bit line 33 is formed on the interlayer insulating film 31. The bit line 33 is electrically connected to the drain diffusion layer 19d of the memory cell via the contact plug 32.

The bit line 33 extends in the column direction. That is, the control gate layer 18 and the bit line 33 are arranged so as to intersect each other vertically or substantially vertically. One memory cell is arranged at the intersection of the control gate layer 18 and the bit line 33.

The drain diffusion layer 19d is shared by two memory cells in the column direction, and is independent of the memory cells in the row direction. Source diffusion layer 19
s extends in the row direction and is a common source line. Therefore, the source diffusion layer 19s is shared by two memory cells in the column direction, and is also shared by a plurality of memory cells in the row direction adjacent to the source diffusion layer 19s.

In the region where the source diffusion layer 19s is formed, the element isolation insulating material 14 is not formed. That is, the element isolation region (element isolation insulating material) 14 is formed so as to extend in the column direction.
Is interrupted at the part. The drain diffusion layer 19d of the memory cell existing in one column is connected to the bit line 33.
Are electrically connected to each other.

FIGS. 5 and 6 show the shapes of the contact holes (bit line contacts) 30 when the device shown in FIGS. 1 to 4 is actually manufactured.

That is, when memory cells are miniaturized and contact holes (bit line contacts) are also miniaturized, the resist film serving as a mask has a rectangular shape even if the contact holes are laid out in a rectangular shape. In some cases, the corners are rounded (a shape close to an ellipse), and the shape of the contact hole formed by etching using the mask as a mask may be a rectangle with rounded corners.

This example explains that the shape of the contact hole is not limited to a rectangle, and that the rectangle may have rounded corners.

As shown in FIGS. 1 to 6, a feature of the present invention resides in the shape of the contact hole (bit line contact) 30. That is, in the present invention, the width Yh of the contact hole 30 in the column direction (the direction in which the bit line 33 extends) is
It is wider than the width Xh of the contact hole 30 in the row direction (the direction in which the word line 18 extends).

In general, with respect to the light exposure technique, when a resist pattern having a hole (for example, a contact hole) shape is formed, it is necessary to expose the resist more than when a resist pattern having a line and space shape is formed. The light amount (exposure amount) becomes large, and the exposure conditions for obtaining the optimal dimensions become very strict.

For example, if the pitch Xpitch of the contact hole (bit line contact) 30 is very short, and if the exposure amount is increased, the adjacent contact hole 30
When the exposure amount is reduced, the exposure is not sufficiently performed, and a problem such that a hole is not formed occurs.

On the other hand, when forming a line-and-space-shaped resist pattern, a so-called proximity effect occurs. Therefore, the light amount (exposure amount) required to expose the resist is determined by changing the hole-shaped resist pattern. It requires less than forming. In other words, under the same conditions,
The line and space shape can be made finer than the hole shape.

The present invention pays attention to this point, and makes the contact hole 30 which has conventionally been a square (or a circle) into a rectangle (or a shape in which the corner of the rectangle is rounded), and has the feature of the line & space shape, that is, The processing margin is improved by the proximity effect.

Specifically, in the case of a nonvolatile semiconductor memory device, the contact hole (bit line contact) 30
Since the contact holes 30 are arranged in a row in the row direction (the direction in which the word lines 18 extend), the width Xh of the contact holes 30 in the row direction is reduced, and the width Yh of the contact holes 30 in the column direction is reduced.
Is longer than the width Xh in the row direction. Thereby, the pitch Xpitch of the contact hole 30 can be reduced, and at the same time, the width Xe of the element region and the width Xi of the element isolation region can be reduced to about the minimum processing dimension of line & space.

That is, conventionally, the line and space pitch Xe + Xi is limited by the diameter of the contact hole 30 and the interval between the contact holes 30, and the line and space pitch Xe + Xi cannot be reduced to the minimum processing size. On the other hand, according to the present invention, the line & space pitch Xe + Xi is not limited by the diameter of the contact hole 30 and the interval between the contact holes 30, and the line & space pitch Xe + Xi can be reduced to the minimum processing size.

Further, even if the width Xh of the contact hole 30 in the row direction is shortened and the width Yh in the column direction is increased, the contact area is not reduced as compared with the conventional square contact hole. The contact resistance can also be kept low.

[Second Embodiment] FIGS. 7 to 10 show a memory cell array of a NAND cell type nonvolatile semiconductor memory device according to a second embodiment of the present invention. FIG.
8 is a plan view of the memory cell array, and FIG.
FIG. 9 is a sectional view taken along line IX-IX in FIGS. 7 and 8,
FIG. 10 is a cross-sectional view taken along line XX of FIGS. 7 and 8.

Note that, for the sake of simplicity, the wiring layer on which the bit lines are formed is omitted in FIG.
Only the wiring layer where the bit lines are formed is shown. That is, the bit line in FIG. 8 is formed on the device in FIG.

In this example, a case where a memory cell array is formed using memory cells having a stacked gate structure will be described. However, it is needless to say that the present invention can be applied to a memory cell having a single gate structure.

The NAND cell type memory cell array is composed of a plurality of NAND strings (or NAND cell units).
Have a structure connected to a bit line. One NAND
The string includes a plurality of memory cells connected in series and two select transistors connected one at each end.

Hereinafter, a specific device structure will be described. An N-well region 12 is provided in a P-type silicon substrate 11.
And a P-well region 13 are formed. Then, the memory cell and the select transistor are formed in the P-type well region 13. However, the memory cell and the select transistor may be formed in the silicon substrate 11. Also,
A trench for element isolation is formed in the silicon substrate 11, and an element isolation insulating material (for example, silicon oxide) 14 is embedded in the trench.

The region sandwiched between the element isolation insulating materials 14 is an element region. Silicon substrate 1 in element region
On the 1 (P-well region 13), a thin tunnel insulating film (for example, silicon oxide) 15 that allows a small tunnel current to flow at the time of writing / erasing is formed.

On the tunnel insulating film 15, the charge transfer layer 1
6 are formed. The charge transfer layer 16 is formed of an electrically floating conductive layer (for example, a polysilicon layer containing impurities).

On the charge transfer layer 16, the inter-gate insulating layer 1
Through 7, the control gate layer 18 is formed. Since the charge transfer layer 16 and the control gate layer 18 are capacitively coupled, when the potential of the control gate layer 18 changes, the potential of the charge transfer layer 16 also changes.

The charge transfer layer 16 and the control gate layer 18
Since they are simultaneously processed in a self-aligned manner, the side ends in the direction (column direction) perpendicular to the direction (row direction) in which the control gate layer (word line) 18 extends coincide with each other. Also,
The side end in the row direction of the charge transfer layer 16 is present on the element isolation insulating material 14.

In the element region, the surface region of the silicon substrate 11 immediately below the charge transfer layer 16 is a channel region. An N-type diffusion layer (source region or drain region) 19 is formed on both sides of the channel region.

The structure of the select transistor has a stack gate structure, like the memory cell. However, the select transistor does not have a charge transfer layer. For example, the upper gate and the lower gate are connected to each other, and one gate electrode (select gate line) SG1, S1
It functions as G2.

Control gate layer (word line) 1 of memory cell
8 and select gate lines SG1 and SG2 both extend in the row direction. On the memory cell, an interlayer insulating film (for example, silicon oxide) 31 covering the memory cell is formed. In the interlayer insulating film 31, a contact hole (bit line contact) 30 reaching the drain diffusion layer 19d of the NAND string is formed.

The contact hole 30 is not a square but a rectangle. In this example, the width Y of the contact hole 30 in the column direction (the direction in which the bit line 33 extends)
h is in the row direction of the contact hole 30 (word line 18).
(Extending direction) is wider than the width Xh.

The contact holes 30 are arranged in a row in the row direction. The pitch Xpitch is determined by the width Xh of the contact hole 30 in the row direction and the contact hole 30.
It is equal to the interval Xb between them. Also, the pitch Xpitch of the contact hole 30 is naturally equal to the repetition pitch (pitch of the bit line 33) Xi + Xe between the element region and the element isolation region.

In the contact hole 30, a contact plug 32 made of a conductive material is buried. Then, a bit line 33 is formed on the interlayer insulating film 31. The bit line 33 is electrically connected to the drain diffusion layer 19d of the memory cell via the contact plug 32.

The bit line 33 extends in the column direction. That is, the control gate layer 18 and the bit line 33 are arranged so as to intersect each other vertically or substantially vertically. One memory cell is arranged at the intersection of the control gate layer 18 and the bit line 33.

In the NAND string, two transistors (memory cells and select transistors) adjacent to each other share one diffusion layer 19. The drain diffusion layer 19d closest to the bit line 33 in the NAND string is shared by the two NAND strings in the column direction, and is independent of the NAND strings in the row direction. The source diffusion layer 19 s
It extends in the row direction and serves as a common source line. Therefore,
The source diffusion layer 19s is shared by two NAND strings in the column direction and is also shared by a plurality of NAND strings in the row direction adjacent to the source diffusion layer 19s.

In the region where the source diffusion layer 19s is formed, the element isolation insulating material 14 is not formed. That is, the element isolation region (element isolation insulating material) 14 is formed so as to extend in the column direction.
Is interrupted at the part. Further, the drain diffusion layers 19 d of the NAND strings existing in one column are electrically connected to each other by the bit line 33.

FIGS. 11 and 12 show the shapes of the contact holes (bit line contacts) 30 when the device shown in FIGS. 7 to 10 is actually manufactured.

That is, when memory cells are miniaturized and contact holes (bit line contacts) are miniaturized, the resist film serving as a mask has a rectangular shape even when the contact holes are laid out in a rectangular shape. In some cases, the corners are rounded (a shape close to an ellipse), and the shape of the contact hole formed by etching using the mask as a mask may be a rectangle with rounded corners.

This example explains that the shape of the contact hole is not limited to a rectangle, and that the corner of the rectangle may be rounded.

Also in the device of this example, the width Yh of the contact hole (bit line contact) 30 in the column direction (the direction in which the bit line 33 extends) is equal to that of the contact hole 3.
The width Xh is larger than the width Xh in the row direction of 0 (the direction in which the word line 18 extends). Therefore, also in this example, as described in the above-described first embodiment, by forming the contact hole 30 as a rectangle (or a rectangle with rounded corners), the feature of the line & space shape, that is, the feature, is obtained. In addition, the processing margin can be improved by the proximity effect.

That is, since the contact holes (bit line contacts) 30 are arranged in a row in the row direction (the direction in which the word lines 18 extend), the width Xh of the contact holes 30 in the row direction is reduced, and The width Yh in the column direction is longer than the width Xh in the row direction. As a result, the pitch Xpit of the contact hole 30
The channel can be narrowed, and at the same time, the width Xe of the element region and the width Xi of the element isolation region can be reduced to about the minimum processing dimension of line & space.

Further, even if the width Xh in the row direction of the contact hole 30 is reduced, if the width Yh in the column direction is increased, the contact area is not reduced as compared with the conventional square contact hole. The contact resistance can also be kept low.

In the case of this example, the memory cell array is N
It has an AND cell structure. In the NAND cell structure,
One contact hole (bit line contact) 30 is provided for one NAND string.
One NAND string is composed of a plurality of memory cells connected in series in the column direction. That is, NAND
The memory cell array having the cell structure can reduce the number of contact holes provided in the column direction as compared with the memory cell array having the NOR cell structure.

In the present invention, since the width Xh of the contact hole 30 in the row direction is reduced and the width Yh of the contact hole 30 in the column direction is increased, the number of contact holes provided in the column direction is reduced. This means that the increase in the area of the memory cell array caused by increasing the width Yh of the hole 30 in the column direction is reduced. That is, the width Xh of the contact hole 30 in the row direction is obtained.
, The effect of reducing the area of the memory cell array becomes remarkable.

As described above, when the present invention is applied to a NAND cell type nonvolatile semiconductor memory device, the effect of the present invention is remarkably exhibited. Although the NOR cell type shown in the first embodiment can provide an effect of reducing the area, the arrangement of the memory cells and a process (self-aligned contact) described later can be applied to the NOR cell type.
The effect can be increased.

[Third Embodiment] FIG. 13 to FIG.
14 shows a memory cell array of a NAND cell type nonvolatile semiconductor memory device according to a third embodiment of the present invention. 13 and 14 are plan views of the memory cell array.
FIG. 15 is a sectional view taken along the line XV-XV in FIGS. 13 and 14, and FIG. 16 is a sectional view taken along the line XVI-XV in FIGS.
It is sectional drawing which follows the I line.

Note that in order to make the drawing easier to understand, FIG.
In FIG. 14, the wiring layer on which the bit line is formed is omitted, and FIG. 14A shows only the wiring layer on which the bit line is formed.
FIG. 14B shows only the element isolation insulating material (element isolation region) 14 and the element region sandwiched therebetween.

In this example, a case where a memory cell array is formed using memory cells having a stacked gate structure will be described. However, it is needless to say that the present invention can be applied to a memory cell having a single gate structure.

The NAND cell type memory cell array is composed of a plurality of NAND strings (or NAND cell units).
Have a structure connected to a bit line. One NAND
The string includes a plurality of memory cells connected in series and two select transistors connected one at each end.

Hereinafter, a specific device structure will be described. An N-well region 12 is provided in a P-type silicon substrate 11.
And a P-well region 13 are formed. Then, the memory cell and the select transistor are formed in the P-type well region 13. However, the memory cell and the select transistor may be formed in the silicon substrate 11. Also,
A trench for element isolation is formed in the silicon substrate 11, and an element isolation insulating material (for example, silicon oxide) 14 is embedded in the trench.

In this example, the trench for obtaining the STI structure is formed linearly without interruption in the column direction (see FIG. 14B). That is, the element isolation region (insulating material for element isolation) 14 has a completely line-and-space shape in the memory cell array region, and the precision of processing control and dimensional control of the element isolation region and the element region can be improved. .

This is because the silicon substrate 1
1 is provided by providing the common source line 43 on the source diffusion layer 1.
9s is not shared with the NAND strings in the row direction (shared with two adjacent NAND strings in the column direction).

In the second embodiment (FIGS. 7 to 12), a common source line extending in the row direction is formed as an N-type diffusion layer 19s in the silicon substrate 11, and a plurality of NANDs in the row direction are formed. In this portion, the element isolation region extending in the column direction is interrupted because it is shared by the strings. As a whole, a plurality of rectangular element isolation regions are regularly arranged in the memory cell array region. It has a shape.

The region sandwiched between the element isolation insulating materials 14 becomes the element region. Silicon substrate 1 in element region
On the 1 (P-well region 13), a thin tunnel insulating film (for example, silicon oxide) 15 that allows a small tunnel current to flow at the time of writing / erasing is formed.

On the tunnel insulating film 15, the charge transfer layer 1
6 are formed. The charge transfer layer 16 is formed of an electrically floating conductive layer (for example, a polysilicon layer containing impurities).

On the charge transfer layer 16, the inter-gate insulating layer 1
Through 7, the control gate layer 18 is formed. Since the charge transfer layer 16 and the control gate layer 18 are capacitively coupled, when the potential of the control gate layer 18 changes, the potential of the charge transfer layer 16 also changes.

The charge transfer layer 16 and the control gate layer 18
Since they are simultaneously processed in a self-aligned manner, the side ends in the direction (column direction) perpendicular to the direction (row direction) in which the control gate layer (word line) 18 extends coincide with each other. Also,
The side end in the row direction of the charge transfer layer 16 is present on the element isolation insulating material 14.

In the element region, the surface region of the silicon substrate 11 immediately below the charge transfer layer 16 is a channel region. An N-type diffusion layer (source region or drain region) 19 is formed on both sides of the channel region.

The structure of the select transistor has a stack gate structure, like the memory cell. However, the select transistor does not have a charge transfer layer. For example, the upper gate and the lower gate are connected to each other, and one gate electrode (select gate line) SG1, S1
It functions as G2.

Control gate layer (word line) 1 of memory cell
8 and select gate lines SG1 and SG2 both extend in the row direction. On the memory cell, an interlayer insulating film (for example, silicon oxide) 31 covering the memory cell is formed. In the interlayer insulating film 31, a contact hole (bit line contact) 30 reaching the drain diffusion layer 19d of the NAND string is formed.

In the interlayer insulating film 31, a contact hole (source line contact) 40 reaching the source diffusion layer 19s of the NAND string is formed.

Each of the contact holes 30 and 40 is not a square but a rectangle. In this example, the width Yh of the contact holes 30, 40 in the column direction (the direction in which the bit lines 33 extend) is wider than the width Xh of the contact holes 30, 40 in the row direction (the direction in which the word lines 18 extend). .

The contact holes 30 are arranged in a row in the row direction. The pitch Xpitch is determined by the width Xh of the contact holes 30 in the row direction and the contact hole 30.
It is equal to the interval Xb between them. Similarly, the contact holes 40 are arranged in a row in the row direction, and the pitch Xpitch thereof is equal to the width Xh of the contact holes 40 in the row direction and the distance Xb between the contact holes 40.

The pitch Xpitch of the contact holes 30 and 40 is naturally also equal to the repetition pitch (pitch of the bit line 33) Xi + Xe between the element region and the element isolation region. This is for associating the positions of the contact holes 30, 40 with the positions of the source / drain diffusion layers 19s, 19d.

The size of the contact hole 30 and the size of the contact hole 40 are preferably set to be equal to each other in consideration of processing controllability and reliability. However, if the shape of the contact hole is rectangular, the effect of the present invention can be obtained, and it is needless to say that the sizes of the two may be different from each other.

In the contact hole 30, a contact plug 32 made of a conductive material is buried. Similarly, a contact plug 42 made of a conductive material is buried in the contact hole 40. Then, on the interlayer insulating film 31, a common source line 43 electrically connected to the source diffusion layer 19s of the NAND string is formed.

The common source line 43 is made of, for example, a high melting point metal (such as tungsten), polysilicon containing impurities, or a stack of these.

An interlayer insulating film (for example, silicon oxide) 41 covering the common source line 43 is formed on the interlayer insulating film 31.
Is formed. A contact hole 44 reaching the contact plug 32 is formed in the interlayer insulating film 41.

The contact hole 44 is also rectangular as in the case of the contact hole 30. That is,
The width of the contact hole 44 in the column direction (the direction in which the bit line 33 extends) is wider than the width of the contact hole 44 in the row direction (the direction in which the word line 18 extends).

Since the contact hole 44 is formed on the memory cell, the width of the contact hole 44 in the column direction is not particularly limited. Therefore, the longer side (the width in the column direction) of the contact hole may be longer than the width Yh of the contact hole 30 in the column direction, and the contact hole 30 may be formed as an even narrower contact hole. In addition, the size of the contact hole 44 and the size of the contact hole 30 may be set to be the same.

Since the contact holes 44 are also arranged in a row in the row direction, similarly to the contact holes 30, the pitch thereof is equal to the pitch Xpitc of the contact holes 30.
h. That is, the width of the contact hole 44 in the row direction and the interval between the contact holes 44 are equal to the width Xh of the contact hole 30 in the row direction and the interval Xb between the contact holes 30.

In the contact hole 44, a contact plug 45 made of a conductive material is buried. Then, the bit line 33 is formed on the interlayer insulating film 41. The bit line 33 is connected to the contact plugs 32, 4
5, and is electrically connected to the drain diffusion layer 19d of the memory cell.

In this example, the contact holes 30 and 44 on the drain diffusion layer 19d are formed.
Are formed separately in different steps, but alternatively, both contact holes may be formed simultaneously as one contact hole in the same step. In this case, the sizes of the contact holes 30 and 44 are the same, and the contact plugs 32 and 45 are
Are formed at the same time and integrated as one contact plug.

FIGS. 17 and 18 show the shapes of the contact holes (bit line contacts) 30 and 40 when the device shown in FIGS. 13 and 16 is actually manufactured.

That is, when the memory cells are miniaturized and the contact holes (bit line contacts) 30 and the contact holes (source line contacts) 40 are miniaturized, the contact holes 30, 40 are laid out in a rectangular shape. However, the shape of the resist film serving as a mask has a shape in which the corners of a rectangle are rounded (a shape close to an ellipse), and the contact holes 30, 40 formed by etching using this as a mask have rounded corners of the rectangle. The shape may be changed.

In this example, the contact hole 3
This explains that the shape of 0, 40 is not limited to a rectangle, but may be a shape with rounded corners.

Also in the device of this example, the width Yh of the contact holes 30, 40 in the column direction (the direction in which the bit line 33 extends) is equal to the width Xh of the contact holes 30, 40 in the row direction (the direction in which the word line 18 extends). Is wider than. Therefore, also in this example, as described in the first and second embodiments, the contact hole 3
0, 40 is a rectangle (or a rectangle with rounded corners)
By doing so, the feature of the line & space shape, that is, the improvement of the processing margin by the proximity effect can be obtained.

That is, the contact holes 30 and 40
Since they are arranged in a row in the row direction (the direction in which the word lines 18 extend), the width Xh of the contact holes 30 and 40 in the row direction is shortened, and the width Yh of the contact holes 30 and 40 in the column direction is reduced to the width in the row direction. Make it longer than Xh. As a result, the pitch Xpitc of the contact holes 30 and 40 is
h can be reduced, and at the same time, the width Xe of the element region and the width Xi of the element isolation region can be reduced to about the minimum processing dimension of line & space.

Even if the width Xh of the contact holes 30 and 40 in the row direction is reduced, the contact area is smaller than that of the conventional square contact hole if the width Yh in the column direction is increased. And the contact resistance can be kept low.

In the case of this example, the memory cell array is N
It has an AND cell structure. In the NAND cell structure,
One contact hole (bit line contact) 30 and one contact hole (source line contact) 40 are provided for one NAND string. That is, the memory cell array having the NAND cell structure can reduce the number of contact holes provided in the column direction as compared with the memory cell array having the NOR cell structure.

In the present invention, the contact holes 30 and 40
Of the contact hole 30,
Since the number of contact holes provided in the column direction is reduced in order to increase the width Yh of the contact holes 40 in the column direction, the width Yh of the contact holes 30 and 40 in the column direction is reduced.
Means that the increase in the area of the memory cell array due to the increase in the size is reduced. That is, contact hole 3
The effect of reducing the area of the memory cell array by reducing the width Xh in the row direction of 0, 40 becomes remarkable.

Further, according to the present invention, a common source line 43 made of metal (including high melting point metal) or polysilicon is provided on the silicon substrate 11 without providing a common source line in the silicon substrate 11. I have. Therefore, in the memory cell array region in the silicon substrate 11, the element isolation region (element isolation insulating material) 14 is completely
The space can be formed into a shape, and the accuracy of dimensional control and processing control can be improved. Further, the resistance of the common source line can be reduced.

[Fourth Embodiment] FIG. 19 to FIG.
14 shows a memory cell array of a NAND cell type nonvolatile semiconductor memory device according to a fourth embodiment of the present invention. 19 and 20 are plan views of the memory cell array,
FIG. 21 is a cross-sectional view taken along the line XXI-XXI of FIGS. 19 and 20, and FIG.
It is sectional drawing which follows the -XXII line.

It should be noted that FIG.
In FIG. 20, the wiring layer on which the bit line is formed is omitted, and FIG. 20 shows only the wiring layer on which the bit line is formed. That is, the bit line of FIG. 20 is formed on the device of FIG.

The device of this example is different from the device of the third embodiment (FIGS. 13 to 18) in the structure of the memory cell and the select transistor.
Otherwise, they are exactly the same. That is,
In this example, the memory cell and the select transistor are constituted by single-gate MOS transistors.

Hereinafter, a specific device structure will be described. An N-well region 12 is provided in a P-type silicon substrate 11.
And a P-well region 13 are formed. Then, the memory cell and the select transistor are formed in the P-type well region 13. A trench for element isolation is formed in the silicon substrate 11, and an insulating material for element isolation (for example, silicon oxide) 14 is embedded in the trench.

The trench for obtaining the STI structure is formed linearly without interruption in the column direction (FIG. 1).
4 (b)). In other words, the element isolation region (element isolation insulating material) 14 has a completely line-and-space shape in the memory cell array region. Therefore, it is possible to improve the precision of processing control and dimensional control of the element isolation region and the element region.

The region sandwiched between the element isolation insulating materials 14 is an element region. Silicon substrate 1 in element region
On the 1 (P-well region 13), a thin tunnel insulating film (for example, silicon oxide) 15 that allows a small tunnel current to flow at the time of writing / erasing is formed.
The thickness of the tunnel insulating film 15 is set to, for example, about several nm.

A charge retaining insulating film 51 is formed on tunnel insulating film 15. The charge retaining insulating film 51 is made of, for example, silicon nitride of about several tens nm. A charge trap level is formed at the interface between the tunnel insulating film 15 and the charge retaining insulating film 51, and the state of the memory cell is determined by the amount of charge trapped at the charge trap level.

On the charge retaining insulating film 51, a control gate layer (word line) 52 and select gate lines SG1, SG
2 are formed. In the element region, the control gate layer 52
The surface region of the silicon substrate 11 immediately below is a channel region. Also, on both sides of this channel region, N
A type diffusion layer (source region or drain region) 19 is formed. The surface region of the silicon substrate 11 immediately below the select gate lines SG1 and SG2 is also a channel region.
On both sides of the channel region, N-type diffusion layers 19,
19s and 19d are formed.

Control gate layer (word line) 1 of memory cell
8 and select gate lines SG1 and SG2 both extend in the row direction. On the memory cell, an interlayer insulating film (for example, silicon oxide) 31 covering the memory cell is formed. In the interlayer insulating film 31, a contact hole (bit line contact) 30 reaching the drain diffusion layer 19d of the NAND string is formed.

A contact hole (source line contact) 40 reaching the source diffusion layer 19s of the NAND string is formed in the interlayer insulating film 31.

The contact holes 30 and 40 are not square but rectangular. In this example, the width Yh of the contact holes 30, 40 in the column direction (the direction in which the bit lines 33 extend) is wider than the width Xh of the contact holes 30, 40 in the row direction (the direction in which the word lines 18 extend). .

The contact holes 30 are arranged in a row in the row direction. The pitch Xpitch is determined by the width Xh of the contact hole 30 in the row direction and the contact hole 30.
It is equal to the interval Xb between them. Similarly, the contact holes 40 are arranged in a row in the row direction, and the pitch Xpitch thereof is equal to the width Xh of the contact holes 40 in the row direction and the distance Xb between the contact holes 40.

The pitch Xpitch of the contact holes 30 and 40 is naturally equal to the repetition pitch (pitch of the bit line 33) Xi + Xe between the element region and the element isolation region. This is for associating the positions of the contact holes 30, 40 with the positions of the source / drain diffusion layers 19s, 19d.

The size of the contact hole 30 and the size of the contact hole 40 are preferably set to be equal to each other in consideration of processing controllability and reliability. However, if the shape of the contact hole is rectangular, the effect of the present invention can be obtained, and it is needless to say that the sizes of the two may be different from each other.

In the contact hole 30, a contact plug 32 made of a conductive material is buried. Similarly, a contact plug 42 made of a conductive material is buried in the contact hole 40. Then, on the interlayer insulating film 31, a common source line 43 electrically connected to the source diffusion layer 19s of the NAND string is formed.

On the interlayer insulating film 31, an interlayer insulating film (for example, silicon oxide) 41 covering the common source line 43 is provided.
Is formed. A contact hole 44 reaching the contact plug 32 is formed in the interlayer insulating film 41.

The contact hole 44 is also rectangular as in the case of the contact hole 30. That is,
The width of the contact hole 44 in the column direction (the direction in which the bit line 33 extends) is wider than the width of the contact hole 44 in the row direction (the direction in which the word line 18 extends).

Since the contact hole 44 is formed on the memory cell, the width of the contact hole 44 in the column direction is not particularly limited. Therefore, the longer side (the width in the column direction) of the contact hole may be longer than the width Yh of the contact hole 30 in the column direction, and the contact hole 30 may be formed as an even narrower contact hole. In addition, the size of the contact hole 44 and the size of the contact hole 30 may be set to be the same.

The contact holes 44 are also arranged in a row in the row direction, similarly to the contact holes 30, so that the pitch thereof is equal to the pitch Xpitc of the contact holes 30.
h. That is, the width of the contact hole 44 in the row direction and the interval between the contact holes 44 are equal to the width Xh of the contact hole 30 in the row direction and the interval Xb between the contact holes 30.

In the contact hole 44, a contact plug 45 made of a conductive material is buried. Then, the bit line 33 is formed on the interlayer insulating film 41. The bit line 33 is connected to the contact plugs 32, 4
5, and is electrically connected to the drain diffusion layer 19d of the memory cell.

Note that, also in this example, the drain diffusion layer 1
Although the contact hole 30 and the contact hole 44 on 9d are separately formed by different processes, both contact holes may be simultaneously formed as one contact hole by the same process. In this case, of course, both contact holes 30, 44
Are the same size and the contact plug 3
2 and 45 are also formed simultaneously and integrated as one contact plug.

FIGS. 23 and 24 show the shapes of the contact holes (bit line contacts) 30 and 40 when the device shown in FIGS. 19 to 22 is actually manufactured.

That is, when the memory cell is miniaturized and the contact hole (bit line contact) 30 and the contact hole (source line contact) 40 are miniaturized, the contact holes 30, 40 are laid out in a rectangular shape. However, the shape of the resist film serving as a mask has a shape in which the corners of a rectangle are rounded (a shape close to an ellipse), and the contact holes 30, 40 formed by etching using this as a mask have rounded corners of the rectangle. The shape may be changed.

In this example, the contact hole 3
This explains that the shape of 0, 40 is not limited to a rectangle, but may be a shape with rounded corners.

As described above, the device of this example is different from the device of the third embodiment only in the structure of the memory cell and the select transistor. Therefore, the same effect as that of the device of the above-described third embodiment can be naturally obtained in the device of this example.

[Fifth Embodiment] FIG. 25 to FIG.
14 shows a memory cell array of a NAND cell type nonvolatile semiconductor memory device according to a fifth embodiment of the present invention. FIGS. 25 and 26 are plan views of the memory cell array.
FIG. 27 shows XXVII-XXVII of FIGS. 25 and 26.
FIG. 28 is a sectional view taken along the line XXVIII-XXVIII in FIGS. 25 and 26.

It should be noted that, in order to make the drawing easier to understand, FIG.
In FIG. 26, the wiring layer on which the bit line is formed is omitted, and FIG. 26 shows only the wiring layer on which the bit line is formed. That is, the bit line in FIG. 26 is formed on the device in FIG.

The device of this example is different from the device of the third embodiment (FIGS. 13 to 18) in that the positions of the contact holes 30 and 40 in the column direction in the manufacturing process of the contact holes 30 and 40 are different. It is characterized by applying a so-called self-aligned contact technique determined by self-alignment.

Hereinafter, a specific device structure will be described. An N-well region 12 is provided in a P-type silicon substrate 11.
And a P-well region 13 are formed. Then, the memory cell and the select transistor are formed in the P-type well region 13. A trench for element isolation is formed in the silicon substrate 11, and an insulating material for element isolation (for example, silicon oxide) 14 is embedded in the trench.

In this example, the trench for obtaining the STI structure is formed linearly without interruption in the column direction (see FIG. 14B). That is, the element isolation region (insulating material for element isolation) 14 has a completely line-and-space shape in the memory cell array region, and the precision of processing control and dimensional control of the element isolation region and the element region can be improved. .

The region sandwiched between the element isolation insulating materials 14 becomes the element region. Silicon substrate 1 in element region
On the 1 (P-well region 13), a thin tunnel insulating film (for example, silicon oxide) 15 that allows a small tunnel current to flow at the time of writing / erasing is formed.

The charge transfer layer 1 is formed on the tunnel insulating film 15.
6 are formed. The charge transfer layer 16 is formed of an electrically floating conductive layer (for example, a polysilicon layer containing impurities).

On the charge transfer layer 16, the inter-gate insulating layer 1
Through 7, the control gate layer 18 is formed. Since the charge transfer layer 16 and the control gate layer 18 are capacitively coupled, when the potential of the control gate layer 18 changes, the potential of the charge transfer layer 16 also changes.

The charge transfer layer 16 and the control gate layer 18
Since they are simultaneously processed in a self-aligned manner, the side ends in the direction (column direction) perpendicular to the direction (row direction) in which the control gate layer (word line) 18 extends coincide with each other. Also,
The side end in the row direction of the charge transfer layer 16 is present on the element isolation insulating material 14.

In the element region, the surface region of the silicon substrate 11 immediately below the charge transfer layer 16 is a channel region. An N-type diffusion layer (source region or drain region) 19 is formed on both sides of the channel region.

The structure of the select transistor has a stack gate structure, like the memory cell. However, the select transistor does not have a charge transfer layer. For example, the upper gate and the lower gate are connected to each other, and one gate electrode (select gate line) SG1, S1
It functions as G2.

The charge transfer layer 16 and the control gate layer (word line) 18 of the memory cell and the select gate line SG1,
The SG 2 is covered with an insulating film (for example, silicon nitride) 60 made of a material having an etching selectivity with respect to the interlayer insulating film (for example, silicon oxide) 31.

On the insulating film 60, an interlayer insulating film (for example, silicon oxide) 31 that completely covers the memory cell is formed. Then, in the interlayer insulating film 31, a contact hole (bit line contact) 30 reaching the drain diffusion layer 19d of the NAND string is formed. A contact hole (source line contact) 40 reaching the source diffusion layer 19s of the NAND string is formed in the interlayer insulating film 31.

The contact holes 30 and 40 are not square but rectangular. In this example, the width Yh1 of the contact holes 30 and 40 in the column direction (the direction in which the bit line 33 extends) is equal to the contact holes 30 and 40.
In the row direction (the direction in which the word lines 18 extend).

The contact holes 30 are arranged in a row in the row direction. The pitch Xpitch is determined by the width Xh of the contact hole 30 in the row direction and the contact hole 30.
It is equal to the interval Xb between them. Similarly, the contact holes 40 are arranged in a row in the row direction, and the pitch Xpitch thereof is equal to the width Xh of the contact holes 40 in the row direction and the distance Xb between the contact holes 40.

The pitch Xpitch of the contact holes 30 and 40 is naturally also equal to the repetition pitch (pitch of the bit line 33) Xi + Xe between the element region and the element isolation region. This is for associating the positions of the contact holes 30, 40 with the positions of the source / drain diffusion layers 19s, 19d.

The size of the contact hole 30 and the size of the contact hole 40 are preferably set to be equal to each other in consideration of processing controllability and reliability. However, if the shape of the contact hole is rectangular, the effect of the present invention can be obtained, and it is needless to say that the sizes of the two may be different from each other.

In this example, it is important that the width of the contact holes 30 and 40 in the column direction is set to Yh1, but since the self-aligned contact technique is employed, the bottoms of the contact holes 30 and 40 are formed. Is that the width Yh2 in the column direction is smaller than Yh1 (Yh1 needs to be larger than Xh,
h2 may be greater than, less than, or equal to Xh. ).

That is, according to this example, by making Yh1 sufficiently larger than Xh, the accuracy of dimensional control and processing control of the contact holes 30, 40 by the proximity effect at the time of exposure is improved, and the row direction is improved. By narrowing the pitch Xpitch of the contact holes 30, 40, it is possible to contribute to reducing the size of the memory cell array in the row direction.

Further, in this example, since the self-aligned contact technology is employed, the contact holes 30 and
The width Yh2 in the column direction at the bottom of 40 is smaller than Yh1. Therefore, the interval between the select gate lines SG1 on the source side can be reduced, which can contribute to the reduction in the size of the memory cell array in the column direction.

It is needless to say that such a self-aligned contact technique can be applied to the devices of the first, second and fourth embodiments.

A contact plug 32 made of a conductive material is buried in the contact hole 30. Similarly, a contact plug 42 made of a conductive material is buried in the contact hole 40. Then, on the interlayer insulating film 31, a common source line 43 electrically connected to the source diffusion layer 19s of the NAND string is formed.

The common source line 43 is made of, for example, a high melting point metal (such as tungsten), polysilicon containing impurities, or a stacked structure of these.

On the interlayer insulating film 31, an interlayer insulating film (for example, silicon oxide) 41 covering the common source line 43 is formed.
Is formed. A contact hole 44 reaching the contact plug 32 is formed in the interlayer insulating film 41.

[0215] The contact hole 44 is also rectangular, like the contact hole 30. That is,
The width of the contact hole 44 in the column direction (the direction in which the bit line 33 extends) is wider than the width of the contact hole 44 in the row direction (the direction in which the word line 18 extends).

The contact hole 44 is
Since the contact hole 44 is formed on the memory cell,
Is not particularly limited as in the third and fourth embodiments described above.

A contact plug 45 made of a conductive material is embedded in the contact hole 44. Then, the bit line 33 is formed on the interlayer insulating film 41. The bit line 33 is connected to the contact plugs 32, 4
5, and is electrically connected to the drain diffusion layer 19d of the memory cell.

In this example, the contact holes 30 and 44 on the drain diffusion layer 19d are formed.
Are formed separately in different steps, but alternatively, both contact holes may be formed simultaneously as one contact hole in the same step. In this case, the sizes of the contact holes 30 and 44 are the same, and the contact plugs 32 and 45 are
Are formed at the same time and integrated as one contact plug.

FIGS. 29 and 30 show the shapes of the contact holes (bit line contacts) 30 and 40 when the device shown in FIGS. 25 to 28 is actually manufactured.

That is, when the memory cells are miniaturized and the contact holes (bit line contacts) 30 and the contact holes (source line contacts) 40 are also miniaturized, the contact holes 30, 40 are laid out in a rectangular shape. However, the shape of the resist film serving as a mask has a shape in which the corners of a rectangle are rounded (a shape close to an ellipse), and the contact holes 30, 40 formed by etching using this as a mask have rounded corners of the rectangle. The shape may be changed.

In this example, the contact hole 3
This explains that the shape of 0, 40 is not limited to a rectangle, but may be a shape with rounded corners.

In the device of this example, the first
The same effects as those of the devices according to the fourth to fourth embodiments can be obtained.

Furthermore, in this example, since the self-aligned contact technology is employed, the contact holes 30 and
The width Yh2 in the column direction at the bottom of the column 40 is smaller than the width Yh1 in the column direction above the contact holes 30 and 40.

That is, according to the present example, by making Yh1 sufficiently larger than Xh, the accuracy of dimensional control and processing control of the contact holes 30, 40 by the proximity effect at the time of exposure is improved, and the row direction is improved. By narrowing the pitch Xpitch of the contact holes 30, 40, it is possible to contribute to reducing the size of the memory cell array in the row direction.

In this example, the contact holes 30 and
The width Yh2 in the column direction at the bottom of the column 40 is smaller than the width Yh1 in the column direction above the contact holes 30 and 40. Therefore, the source-side select gate line SG
The distance between the cells 1 can be reduced, and the size of the memory cell array in the column direction can be reduced.

[Relationship between Xh and Yh] The present invention has been described based on the first to fifth embodiments. According to the present invention, by forming the contact hole into a rectangle (including a shape in which the corner of the rectangle is rounded; the same applies hereinafter) (Xh <Yh), the short side Xh can be opened in the case of a square. Than the length of one side of the contact hole,
It is possible to shorten it.

For example, assuming that the same exposure technique is used, experimentally, when the minimum exposure dimension in a line & space shape (simple repetition pattern) is 0.2 μm, the minimum exposure dimension of a square contact hole is: 0.
3 μm.

Therefore, even if the minimum hole size that can be opened in the case of a square is 0.3 μm, the size of the short side that can be opened is the maximum if it is made a rectangle (limitally, a line pattern). , 0.2 μm (about 66% of the square hole size).

Similarly, assuming that the same exposure technique is used, experimentally, when the minimum exposure dimension in the line & space shape (simple repetition pattern) is 0.13 μm, the minimum exposure dimension of the square contact hole is , 0.
2 μm.

Therefore, even if the minimum hole size that can be opened in the case of a square is 0.2 μm, the size of the short side that can be opened is the maximum if it is made a rectangle (limitally, a line pattern). , 0.13 μm (about 66% of the square hole size).

As described above, according to the present invention, by making the contact hole rectangular, the short side Xh is up to about 66% of the minimum hole size that can be opened in the case of a square (about 2 / 3) can be reduced. Accordingly, the pitch of the contact holes, that is, the pitch (period) of the repetitive pattern of the element region and the element isolation region can be reduced, so that the area of the memory cell array region can be significantly reduced.

That is, considering the row direction (the direction in which the word lines extend), the effect of reducing the area of the memory cell array region is to reduce the length of one side of the square contact hole to about 66% (about 2/3 times). Therefore, when the shape of the contact hole is a rectangle long in the column direction (the direction in which the bit line extends) (the length of one side of the contact hole in the column direction is not changed), that is, Yh is approximately equal to Xh. It becomes maximum when it becomes 1.5 times (about 3/2 times).

However, if the short side Xh of the rectangular contact hole is reduced to about 66% (about 2/3 times) the minimum hole size that can be opened in the case of a square, the long side Yh is reduced. If the minimum hole size that can be opened in the case of a square is kept (fixed value), the contact area in the case of a rectangle is about 66% of that in the case of a square.
As a result, the contact resistance in the case of a rectangle is about 1.10 of the contact resistance in the case of a square.
It increases 5 times (about 3/2 times).

Then, after the short side Xh becomes the minimum value (the minimum exposure dimension of the line & space shape), the long side Yh
Is larger than the minimum hole size that can be opened in the case of a square, it is possible to suppress an increase in contact resistance.

For example, only the size of the square contact hole in the row direction (X direction) is about 66% (about 2/3 times).
When contracted, the contact area is about 66% (about 2/3
), The contact resistance increases about 3/2 times.

Therefore, in order to maintain the same contact resistance as that of a square contact hole, it is necessary to increase the size of the contact hole in the column direction (Y direction) about 3/2 times. At this time, Yh is about 2.25 times (X3 / 2) / {2/3} = {9/4} times Xh.

In addition, due to variations in processing during manufacturing, Y
It is difficult to make h exactly equal to 2.25 times Xh. In consideration of such variations in processing at the time of manufacturing, when Yh is not less than twice and not more than 2.5 times Xh, the effect of area reduction can be maximized without increasing contact resistance. .

By the way, the size Yh of the contact hole in the column direction cannot be infinitely increased (Y
When h becomes infinite, it becomes a complete line & space. ). Realistically (considering the self-aligned contact), it is considered that the maximum value of Yh is about three times the minimum processing dimension of the line and space (for example, equal to the width of the word line).

Here, assuming that Xh is set to the minimum processing dimension of line & space (for example, the width of the element region and the width of the element isolation region are also set to this minimum processing dimension), Yh Is three times Xh.

To summarize the above, Yh is 1.5 times Xh.
More than twice and less than 3 times is a realistic range, and Yh
However, when the value is not less than twice and not more than 2.5 times Xh, the effect of area reduction can be maximized without increasing contact resistance. However, ignoring the chip size in the column direction, and if possible on the chip layout, Yh is
It may be more than three times Xh.

[Others] In the present invention, the above-described NO
Not only the R cell type and the NAND cell type non-volatile semiconductor memory device but also the bit line pitch (period) or the repetition pitch (period) of the element region and the element isolation region is 0.5.
The effect is great when applied to a nonvolatile semiconductor memory device of μm or less.

The present invention also relates to a nonvolatile semiconductor device in which contact holes (bit line contacts or source line contacts) are arranged in a line at the same pitch as the bit line pitch (or the repetition pitch between the element region and the element isolation region). It is applicable to all storage devices.

Further, according to the present invention, as described in the above embodiment, the size Xh of the contact hole in the row direction is equal to the size Xe of the element region in the row direction, and the interval Xb between the contact holes and the size of the element isolation region are different. Not only when the size Xi in the row direction is equal, but also as shown in FIGS. 31 and 32, the size Xh of the contact hole in the row direction is larger than the size Xe of the element region in the row direction, and the distance Xb between the contact holes is small. The present invention can also be applied to a case where the element isolation region is smaller than the size Xi in the row direction.

In the present invention, the size Xh of the contact hole in the row direction is smaller than the size Xe of the element region in the row direction, and the interval Xb between the contact holes is larger than the size Xi of the element isolation region in the row direction. Also applicable to The present invention can be variously modified without departing from the gist thereof.

[0245]

As described above, according to the present invention, according to the present invention, in a nonvolatile semiconductor memory device in which contact holes need to be arranged in a line at a constant pitch (period) in one direction, The shape is a rectangle or a shape with rounded corners, and the width of the contact hole in one direction (row direction) is smaller than the width in the direction (column direction) orthogonal to the one direction.

In this case, the width (short side) of the contact hole in one direction can be narrower than the minimum processing size of the square contact hole, and can be reduced to the minimum processing size of line and space at the maximum. Thus, the pitch of the contact holes in the one direction can be narrowed while maintaining the accuracy of the dimension control and processing control of the contact holes, thereby contributing to a reduction in the element region and a reduction in the chip area.

Regarding the width of the contact hole in the direction orthogonal to the one direction, especially by adopting the self-aligned contact technology, even if the width in the direction orthogonal to the one direction is increased, It is possible to achieve a reduction in the element region and a reduction in the chip area in a direction orthogonal to the one direction while maintaining the accuracy of the dimensional control and the processing control.

Further, if the width of the contact hole in the direction orthogonal to the one direction is set to 1.5 times or more the width of the contact hole in the one direction, the contact resistance increases due to the effect of area reduction. On the other hand, it is possible to take measures to reduce the contact resistance by increasing the contact area while maintaining the effect of the area reduction.

[Brief description of the drawings]

FIG. 1 is a plan view showing a memory cell array of a NOR cell type nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a plan view showing a bit line formed on the device of FIG. 1;

FIG. 3 is a sectional view taken along the line III-III in FIGS. 1 and 2;

FIG. 4 is a sectional view taken along the line IV-IV in FIGS. 1 and 2;

FIG. 5 is a view showing a shape of a contact hole when the device shown in FIGS. 1 and 2 is actually manufactured.

FIG. 6 is a view showing the shape of a contact hole when the device shown in FIGS. 1 and 2 is actually manufactured.

FIG. 7 is a plan view showing a memory cell array of a NAND cell type nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 8 is a plan view showing a bit line formed on the device of FIG. 7;

FIG. 9 is a sectional view taken along the line IX-IX in FIGS. 7 and 8;

FIG. 10 is a sectional view taken along the line XX in FIGS. 7 and 8;

FIG. 11 is a view showing a shape of a contact hole when the devices of FIGS. 7 and 8 are actually manufactured.

FIG. 12 is a view showing a shape of a contact hole when the devices of FIGS. 7 and 8 are actually manufactured.

FIG. 13 is a plan view showing a memory cell array of a NAND cell type nonvolatile semiconductor memory device according to a third embodiment of the present invention.

14 is a plan view showing bit lines and element isolation regions in the device shown in FIG.

FIG. 15 is a sectional view taken along lines XV-XV in FIGS. 13 and 14;

FIG. 16 is a sectional view taken along lines XVI-XVI in FIGS. 13 and 14;

FIG. 17 is a view showing the shape of a contact hole when the devices of FIGS. 13 and 14 are actually manufactured.

FIG. 18 is a view showing the shape of a contact hole when the devices of FIGS. 13 and 14 are actually manufactured.

FIG. 19 is a plan view showing a memory cell array of a NAND cell type nonvolatile semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 20 is a plan view showing a bit line formed on the device of FIG. 19;

FIG. 21 is a sectional view taken along lines XXI-XXI in FIGS. 19 and 20;

FIG. 22 is a sectional view taken along lines XXII-XXII in FIGS. 19 and 20;

FIG. 23 is a view showing a shape of a contact hole when the devices of FIGS. 19 and 20 are actually manufactured.

FIG. 24 is a view showing the shape of a contact hole when the devices of FIGS. 19 and 20 are actually manufactured.

FIG. 25 is a plan view showing a memory cell array of a NAND cell type nonvolatile semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 26 is a plan view showing a bit line formed on the device of FIG. 25;

FIG. 27. XXVII-XXVII of FIG. 25 and FIG.
Sectional view along the line.

FIG. 28. XXVIII-XXVI of FIG. 25 and FIG.
Sectional drawing which follows the II line.

FIG. 29 is a view showing the shape of a contact hole when the devices of FIGS. 25 and 26 are actually manufactured.

FIG. 30 is a view showing the shape of a contact hole when the devices of FIGS. 25 and 26 are actually manufactured.

FIG. 31 is a plan view showing a modified example of the memory cell array of the NOR cell type nonvolatile semiconductor memory device of the present invention.

FIG. 32 is a plan view showing a modification of the memory cell array of the NAND cell type nonvolatile semiconductor memory device of the present invention.

FIG. 33 is a plan view showing the device structure of a stacked gate memory cell.

34 is a sectional view taken along the line XXXIV-XXXIV of FIG.

FIG. 35 is a sectional view taken along the line XXXV-XXXV in FIG. 33;

FIG. 36 is a plan view showing a device structure of a single-gate memory cell.

FIG. 37 is a sectional view taken along the line XXXVII-XXXVII in FIG. 36;

38 is a sectional view taken along the line XXXVIII-XXXVIII in FIG. 36.

FIG. 39 is a plan view showing a memory cell array of a conventional NOR cell type nonvolatile semiconductor memory device.

FIG. 40 is a plan view showing a bit line formed on the device of FIG. 39.

FIG. 41 is a sectional view taken along lines XLI-XLI in FIGS. 39 and 40;

FIG. 42 is a sectional view taken along lines XLII-XLII in FIGS. 39 and 40;

FIG. 43 is a view showing the shape of a contact hole when the devices of FIGS. 39 and 40 are actually manufactured.

FIG. 44 is a view showing a shape of a contact hole when the devices of FIGS. 39 and 40 are actually manufactured.

FIG. 45 is a plan view showing a memory cell array of a conventional NAND cell type nonvolatile semiconductor memory device.

FIG. 46 is a plan view showing a bit line formed on the device of FIG. 45.

FIG. 47: XLVII-XLVII of FIGS. 45 and 46
Sectional view along the line.

FIG. 48: XLVIII-XLVI of FIGS. 45 and 46
Sectional drawing which follows the II line.

FIG. 49 is a view showing a shape of a contact hole when the devices of FIGS. 45 and 46 are actually manufactured.

FIG. 50 is a view showing a shape of a contact hole when the devices of FIGS. 45 and 46 are actually manufactured.

[Explanation of symbols]

11, 21: P-type silicon substrate, 12, 22: N-type well region, 13, 23: P-type well region, 14, 24: Insulating material for element isolation (element isolation area), 15, 25: Tunnel insulating film, 16: charge transfer layer, 17: inter-gate insulating layer, 18, 27, 52: control gate layer, 19, 28: N-type diffusion layer, 19d: drain diffusion layer, 19s: source diffusion layer, 26: insulation for charge retention Films, 30, 44: contact holes (bit line contacts), 31, 41: interlayer insulating films, 32, 42, 45: contact plugs, 33: bit lines, 40: contact holes (source line contacts), 43: common source Line 51: charge retention insulating film.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Riichiro Shirada 8F, Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture F-term (reference) 5F001 AA25 AB08 AC02 AD51 AD52 AD53 AD60 AD61 5F083 EP02 EP23 EP76 EP77 ER03 ER09 ER14 ER19 GA09 KA05 LA12 LA16 LA20 LA21 MA06 MA19 MA20 NA01 5F101 BA07 BB05 BC02 BD32 BD33 BD34 BD35 BD36

Claims (16)

[Claims] 1. An element region and an element isolation region which are repeatedly arranged in one direction at a constant period, and memory cells formed in the element region are arranged in the one direction at the same period as the constant period. A contact hole, and a wiring for transmitting and receiving data to and from the memory cell via the contact hole, wherein the width of the contact hole in the other direction orthogonal to the one direction is larger than the width of the contact hole in the one direction. A non-volatile semiconductor memory device characterized by having a large width. 2. The nonvolatile semiconductor memory device according to claim 1, wherein a width of said contact hole in said other direction is at least 1.5 times a width of said contact hole in said one direction. 3. The width of the contact hole in the other direction is not more than three times the width of the contact hole in the one direction, and the width of the contact hole in the one direction is smaller than the width of the element region. 3. The nonvolatile semiconductor memory device according to claim 2, wherein the width is substantially equal to the width in one direction. 4. The non-volatile semiconductor device according to claim 1, wherein the width of the contact hole in the other direction is not less than twice and not more than 2.5 times the width of the contact hole in the one direction. Storage device. 5. The non-volatile semiconductor memory device according to claim 1, wherein said wiring is a bit line, and said bit line is connected to one end of a current path of said memory cell. 6. The other end of the current path of the memory cell is connected to a source line, and a control gate line of the memory cell extending in the one direction is arranged between the contact hole and the source line. The nonvolatile semiconductor memory device according to claim 5, wherein: 7. The non-volatile memory according to claim 1, wherein the wiring is a bit line, and the bit line is connected to one end of a current path of the memory cell via at least one transistor. Semiconductor memory device. 8. The other end of the current path of the memory cell is connected to a source line via at least one transistor, and between the contact hole and the source line
8. The nonvolatile semiconductor memory device according to claim 7, wherein at least one control gate line extending in one direction is arranged. 9. The non-volatile semiconductor device according to claim 1, wherein the memory cell includes a gate insulating film formed on the element region, and a charge transfer layer formed on the gate insulating film. Storage device. 10. The nonvolatile semiconductor memory device according to claim 1, wherein said wiring is a source line, and said source line is connected to one end of a current path of said memory cell. 11. The non-volatile memory according to claim 1, wherein the wiring is a source line, and the source line is connected to one end of a current path of the memory cell via at least one transistor. Semiconductor memory device. 12. The width of the contact hole in the other direction is the width in the other direction above the contact hole, the width in the other direction above the contact hole is Y1, and the width in the bottom of the contact hole is Y1. When the width in the other direction is Y2, Y1> Y2, and the width in the other direction at the top of the contact hole and the width in the other direction at the bottom of the contact hole change discontinuously. 2. The non-volatile semiconductor storage device according to claim 1, wherein: 13. The device region and the device isolation region extend in the other direction, and the width of the device region and the device isolation region in the one direction is substantially equal to the width of the contact hole in the one direction. 2. The method of claim 1, wherein:
14. The nonvolatile semiconductor memory device according to claim 1. 14. The nonvolatile semiconductor memory device according to claim 13, wherein the width of the element region and the element isolation region in the one direction is substantially equal to the width of a control gate line of the memory cell. . 15. An element region and an element isolation region which are repeatedly arranged in one direction at a constant period, and memory cells formed in the element region, and are arranged in the one direction at substantially the same period as the constant period. A first contact hole, a bit line connected to one end of a current path of the memory cell via the first contact hole and at least one transistor, and arranged in the one direction at a cycle substantially equal to the constant cycle. A second contact hole, and a source line connected to the other end of the current path of the memory cell via the second contact hole and at least one transistor, wherein the first and second contact holes are: In both cases, the width in the other direction orthogonal to the one direction is wider than the width in the one direction. 16. The nonvolatile semiconductor memory device according to claim 15, wherein a size of said first contact hole is substantially equal to a size of said second contact hole.