KR100219534B1 - Flash memory device & fabricating method for the same - Google Patents

Abstract

Disclosed are a flash memory device and a method of manufacturing the same, which can solve a problem in which a read-disturbance occurs during readout due to over erase without increasing an area of a cell. To this end, the present invention provides a separation distance between a source and a drain region having a second conductivity type impurity formed separately in a predetermined region of the semiconductor substrate having the first conductivity type impurity, and a source and drain region on the semiconductor substrate. A first insulating layer formed to have a predetermined thickness, a first conductive layer for word lines formed on the first insulating layer, and upper and side walls of the first conductive layer and surrounding sidewalls of the first insulating layer. And a second insulating film formed over the semiconductor substrate and on predetermined portions of the source and drain regions of the semiconductor substrate, and a second conductive layer for floating gate formed on the second insulating film. And a method for producing the same. Therefore, in the flash memory, it is possible to prevent read-disturbance when reading data of the memory cell, and to minimize the area of the cell while reducing the time and cost of the process.

Description

Flash memory device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device of a semiconductor device and a method of manufacturing the same. In particular, the present invention can solve a problem in which a read-disturbance occurs during reading by over erase without increasing a cell area. A flash memory device and a method of manufacturing the same.

Flash memories of semiconductor devices are classified into two types, NOR and NAND, according to the cell array structure. Unlike NAND flash memory where 8 or 16 cell transistors are connected in series on one bit line, NOR flash memory has 8 or 16 transistors connected in parallel on one bit line. In addition, NAND flash memory can store only one cell information in one bit line, whereas NOR flash memory stores and reads information in eight or sixteen cells connected in parallel to one bit line, respectively. In this way, the cell utilization efficiency can be improved. Therefore, a flash memory product is widely used for a MICOM product and a high speed random access DRAM interface.

In such a flash memory, one transistor including a source electrode, a drain, and a gate electrode composed of a floating gate and a control gate forms a unit memory cell Bit. Here, the floating gate serves to store data, the control gate serves to control the floating gate, and programming and data of the data by applying a high voltage signal to a bit line connected to the control gate and the drain region. It has the characteristic of erasing.

Hereinafter, a flash memory device and a problem according to the related art will be described with reference to the accompanying drawings of FIGS. 1 to 2.

1 is a diagram illustrating an equivalent circuit of a NOR flash memory. A plurality of transistors are connected in parallel to one bit line to form a predetermined number in the vertical direction, and in the horizontal direction, word lines are formed while crossing the bit lines in a predetermined number. have.

Here, when reading any one of the specific cells 1, since the transistor of the Noah type flash memory is connected in parallel with a plurality of transistors in one bit line, the cells adjacent to the common bit line in the specific cell ( If 3) is over erased, there is a problem that causes read-disturbance. One transistor is additionally required to structurally solve this read-disturbance problem. If one cell is composed of two transistors, the area of the cell is significantly increased. Therefore, a structure of a transistor for a memory cell used in a flash memory that can solve the above-described read-disturbance problem while minimizing an increase in the cell area has been developed.

FIG. 2 is a cross-sectional view illustrating a structure of a transistor used as a memory cell of a flash memory device capable of resolving a problem of read-disturbance while maximally suppressing an increase in the cell area according to the related art. In detail, there is a field oxide film 12 formed on the semiconductor substrate 10 by a device isolation process, and the gate oxide film 14 is disposed at a predetermined portion of the active region between the field oxide film 12 and the field oxide film 12. The floating gate 16 as the first conductive layer, the interlayer insulating film 18 and the control gate 20 as the second conductive layer are sequentially formed. Reference numeral 22 denotes a pass transistor formed of a third conductive layer which performs a function of blocking a current from an over erased cell when reading the data of the flash memory cell described above to prevent read-disturbance. It is an area to be composed. In addition, the source and drain regions 24 and 26 formed by performing an ion implantation process on the semiconductor substrate 10 using the second conductive layer and the third conductive layer as an ion implantation mask are respectively configured.

However, three conductive layers are required to manufacture the above-described cell, and thus, the manufacturing process is complicated, and manufacturing time and cost increase.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a flash memory device capable of minimizing a malfunction and minimizing a cell area when reading data of a cell using only two conductive layers.

Another object of the present invention is to provide a method of manufacturing the flash memory.

1 to 2 are diagrams for explaining a flash memory device and a problem thereof according to the prior art.

3 and 4 are diagrams for explaining the structure and characteristics of the flash memory device according to the present invention.

5 to 12 are cross-sectional views illustrating a method of manufacturing a flash memory according to the present invention in order of a process.

Description of the main symbols in the drawings

100: semiconductor substrate, 102: field oxide film,

104: first insulating film (gate oxide film) 106: first conductive layer (word line),

108: second insulating film (interlayer insulating film) 110: second conductive layer (floating gate),

112: source region, 114: drain region (bit line)

In order to achieve the above technical problem, the present invention provides a source and a drain region having a second conductivity type impurity separately formed in a predetermined region of the semiconductor substrate having a first conductivity type impurity, and a source and drain region on the semiconductor substrate. A first insulating layer formed to have a predetermined thickness with a distance therebetween, a first conductive layer for word lines formed on the first insulating layer, and upper and side walls of the first conductive layer A second insulating film formed on an upper portion of the semiconductor substrate and on a predetermined portion of the source and drain regions, and a second conductive layer for floating gate formed on the second insulating film. Provided is a flash memory device comprising:

Preferably, the first insulating film is composed of an oxide or an oxynitride, and the first conductive layer is preferably a polysilicon film.

It is preferable that the said 2nd conductive layer is a polysilicon film and metal polyside formed in a multilayered structure.

In addition, the metal polyside is preferably tungsten polyside.

The center of the first insulating layer is preferably asymmetrically longer in the drain region when comparing the separation distance between the source and the drain region.

Preferably, the second insulating film has the same thickness and material on the first conductive layer, on both side walls of the first conductive layer and the first insulating film, and on the semiconductor substrate.

According to an aspect of the present invention, there is provided a device isolation process on a semiconductor substrate of a first conductivity type impurity to define a field oxide film and an active region, and a first insulating film and a first insulating layer on the active region. Forming a first conductive layer sequentially, selectively etching the first insulating layer and the first conductive layer to form a first conductive layer pattern as a word line pattern, and the first conductive layer pattern Forming a second insulating layer and a second conductive layer on the formed semiconductor substrate, selectively etching the second insulating layer and the second conductive layer to form a second conductive layer pattern as a floating gate pattern, and And forming source and drain regions on both sides of the floating gate by ion implanting a second conductivity type impurity onto the entire surface of the semiconductor substrate having the second conductive layer pattern formed thereon. It provides a flash memory production process.

Preferably, the forming of the second conductive layer is preferably formed in a multilayer using a polysilicon film and a metal polyside.

According to the present invention, in the flash memory, it is possible to prevent a malfunction when reading the data of the cell and to minimize the area of the cell.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Structure and features

First, the structure and characteristics of a flash memory device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 3 and 4.

3 is a cross-sectional view of a single memory cell to illustrate a flash memory device according to the present invention. In detail, the semiconductor substrate 100 of the first conductivity type impurity has a field oxide film 102 for separating active and inactive regions, and a gate oxide film is formed in a predetermined region of the active region generated by the field oxide film 102. The first insulating film 104, which serves as a material and is composed of an oxide layer or an oxynitride layer, is positioned. A first conductive layer 106 made of polysilicon is formed on the first insulating film 104 to simultaneously perform the function of a word line and to simultaneously perform the function of a pass transistor in the prior art. . In addition, the second insulating film 108 serving as the interlayer insulating film or the tunnel layer of the floating gate may surround the upper and both side walls of the first conductive layer 106 and both side walls of the first insulating film 104. The semiconductor substrate 100 is formed of the same material and a predetermined thickness on the upper portion of the semiconductor substrate 100 and the upper portions of the source and drain regions 112 and 114. A floating gate, that is, the second conductive layer 110 has a polysilicon layer and a metal polyside (a reactant of metal and polyside) formed in a multilayer structure on the second insulating layer 108 to store the contents of data. Do this. In addition, a common source region 112 formed by performing ion implantation using the second conductive layer 110 as a mask and a drain region 114 used as a bit line are formed at lower ends of both sides of the second conductive layer 110. have. The source and drain regions 112 and 114 enter the lower portion where the second conductive layer 110 is located because of thermal diffusion in the diffusion process after the ion implantation is completed.

Here, the position of the second conductive layer 110 serving as the floating gate is asymmetrically formed so that the drain region is longer when viewed from the source region 112 and the drain region. This is to minimize the influence of the surrounding circuit area when a high voltage 12V is applied to the bit line which is the drain region when programming or erasing data to the flash memory cell.

In addition, the first conductive layer 104 which functions as a word line and a pass transistor is surrounded by the second conductive layer 110 serving as a floating gate, thereby reading data. ), The first conductive layer 104 maintains a constant threshold voltage (0.7V) to solve the problem of read-disturbance. In addition, by adopting the above-described structure, the memory cell composed of three conductive layers can be composed of two conductive layers, thereby simplifying the process and reducing the cost.

4, a plan view of a flash memory cell according to an embodiment of the present invention described above. Here, reference numeral 116 denotes an active region, 104 denotes a first conductive layer which is a word line, 118 denotes a second conductive layer which is a floating gate, and 118 denotes a contact hole for connecting a drain region and a bit line.

Manufacturing method

5 to 12 are cross-sectional views illustrating a method of manufacturing a flash memory according to the present invention in order of a process.

Referring to FIG. 5, a local oxidation of silicon (LOCOS) process or a selective isolation polysilicon oxidation (SEPOX) process is performed on a semiconductor substrate 100 of a first conductivity type impurity. As a result, a field oxide film 102 is formed which separates the active and inactive regions.

Referring to FIG. 6, an oxide layer or an acid is formed on a first insulating film 104 to be used as a gate oxide film of a word line transistor by performing a thermal oxidation process on the entire surface of the semiconductor substrate on which the device isolation process is completed. It is formed of a material of an oxynitride layer.

Referring to FIG. 7, the first conductive layer 106 used as a control gate and a word line is sequentially formed on the semiconductor substrate 100 on which the first insulating layer 104 is formed. It is laminated with a polyside consisting of silicon and metal silicide.

Referring to FIG. 8, a photoresist is applied on the first insulating layer 104 and the first conductive layer 106, and a photo and etching process is performed through dry etching to form the first insulating layer 104 and the first conductive layer. The layer 106 is anisotropically etched to complete the pattern of the first conductive layer 106 which is a word line transistor pattern.

Referring to FIG. 9, a second insulating layer 108 to be used as a tunnel layer of the floating gate is formed on the semiconductor substrate on which the first conductive layer 106 pattern is formed to have a predetermined thickness of less than 100 μs.

Referring to FIG. 10, in order to deposit a polysilicon film to be used as a floating gate on the second insulating film 108 and to continuously form polysides, for example, tungsten is deposited on the polysilicon film to be heat-treated at a high temperature. Next, the multilayer structure of the second conductive layer 110 including the polysilicon film and the metal silicide is formed.

Referring to FIG. 11, a photoresist is applied to the second insulating layer 108 and the second conductive layer 110, and a patterning process is performed to form predetermined regions of the second insulating layer 108 and the second conductive layer 110. Is anisotropically etched to form a floating gate pattern, that is, a second conductive layer 110 pattern. In this case, the pattern of the second conductive layer 110 centers around the first conductive layer 104 during the anisotropic etching so as to be asymmetrically longer toward the direction in which the drain region is to be formed.

Referring to FIG. 12, an ion implantation of an N-type impurity, which is a second conductivity type impurity, is performed on the resultant on which the second conductive layer pattern is formed, and a drive-in process is performed through heat treatment, thereby lowering both sides of the floating gate pattern. A common source 112 used as a ground and a drain region 114 used as a bit line are formed in the semiconductor substrate in the semiconductor substrate.

When the flash memory is manufactured according to the embodiment of the present invention described above, only a mask for manufacturing a pattern of a floating gate, that is, a pattern of the second conductive layer is added in a process of using two existing conductive layers without forming three conductive layers. This allows the manufacture of flash memory without significant process changes.

Principle of operation

12, the operation principle of the flash memory according to the preferred embodiment of the present invention will be described.

First, a programming operation principle will be described. In FIG. 12, 5 to 7 V is applied to the bit line, which is the drain region 14, as the Vcc voltage, and the source region 12 is connected to ground. Subsequently, if a high voltage of 12 to 13 V, which is a programming voltage Vpp, is applied to the word line of the cell to be programmed, that is, the first conductive layer 104 in the drawing. By injecting hot electrons into the second insulating layer thinly formed to be less than 100 kHz, which is a tunnel layer, the hot electrons having high energy accumulate in the second conductive layer 110 which is a floating gate, thereby increasing the threshold voltage. The memory cell is then brought into an off-state, which is a 'low' state.

Next, an operation principle of erasing will be described. In FIG. 12, a voltage of 5 to 7 V is applied to the word line of the first conductive layer 104 as the Vcc voltage, and then a source region (used as the ground terminal) is used. 112) is left floating or open. Subsequently, when a high voltage of 12 to 13 V is applied to the drain region 114 of the cell to be erased, a band-to-band current is generated in the second insulating layer 108, that is, the tunnel layer. Done. At this time, the generated holes are band to band hot hole injection due to the high electric field of 12 to 13V (band to band hot hole injection), so that the memory cell is in an 'high' on-state state. Becomes

Finally, the operating principle of the read is, in FIG. 12, the Vcc voltage is applied to the first conductive layer 104, which is a word line, the source region is connected to ground, and the bit of the cell to be read. Apply a voltage of 1.5-5V to the line. Then, a channel is formed in the drain direction in the source to generate a current flow. The amount of the current represents a state of charge (on / off) accumulated in the second conductive layer 110 which is the floating gate.

The present invention is not limited to the above-described embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit to which the present invention belongs.

Therefore, according to the present invention described above, in the flash memory, it is possible to prevent the read-disturbance when reading the data of the memory cell, and to minimize the area of the cell while reducing the time and cost of the process,

Claims (11)

Source and drain regions each having a second conductivity type impurity formed separately from a predetermined region of the semiconductor substrate having the first conductivity type impurity; A first insulating layer formed to have a predetermined thickness between the source and drain regions on the semiconductor substrate at a predetermined distance from each other; A first conductive layer for word lines formed on the first insulating layer; A second insulating film surrounding upper and both sidewalls of the first conductive layer, surrounding sidewalls of the first insulating film, and formed on predetermined portions of the source and drain regions; And And a second conductive layer for floating gate formed on the second insulating film. The flash memory device of claim 1, wherein the first insulating film is formed of an oxide film or an oxynitride film. The flash memory device of claim 1, wherein the first conductive layer is polysilicon. The flash memory device of claim 1, wherein the second conductive layer is formed in multiple layers. The flash memory device of claim 4, wherein the second conductive layer formed of the multilayer comprises polysilicon and a metal polyside. 6. The flash memory device of claim 5, wherein the metal polyside is tungsten polyside. The flash memory device of claim 1, wherein a center of the first insulating layer is asymmetrical when a distance between the source and the drain region is compared. 8. The flash memory device of claim 7, wherein the asymmetry is longer in the drain region used as the bit line. 2. The flash memory of claim 1, wherein the second insulating film has the same thickness and material on the first conductive layer, on both sidewalls of the first conductive layer and the first insulating film, and on the top of the semiconductor substrate. device. Performing a device isolation process on the semiconductor substrate of the first conductivity type impurity to define a field oxide film and an active region; Sequentially forming a first insulating film and a first conductive layer on the active region; Selectively etching the first insulating layer and the first conductive layer to form a pattern of a first conductive layer for a word line pattern; Forming a second insulating layer and a second conductive layer on the semiconductor substrate on which the first conductive layer pattern is formed; Selectively etching the second insulating layer and the second conductive layer to form a second conductive layer pattern for the floating gate pattern; And ion-implanting a second conductivity type impurity onto the entire surface of the semiconductor substrate on which the second conductive layer pattern is formed to form source and drain regions on both sides of the floating gate. The method of claim 10, wherein the forming of the second conductive layer comprises forming a plurality of layers using polysilicon and a metal polyside.

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