KR0152496B1 - Flash eeprom - Google Patents

Abstract

The EEPROM cell includes a select gate for accessing the cell and a floating gate for storing data. Each of the two gates is formed from a poly sidewall and is separated by a vertical oxide member formed by growing an oxide film on the vertical poly sidewall of an aperture in which the selection gate is formed. The final structure has smaller dimensions than can be obtained from optical lithography, since these two gates are in fact sidewalls and are therefore not limited to the dimensions obtainable by optical lithography.

Description

[Name of invention]

Method for forming EEPROM cell, integrated circuit EEPROM double gate field effect transistor and method for forming EEPROM memory array

Detailed description of the invention

[Field of Invention]

The present invention relates to ultra high density Electrically Erasable Programmable Read Only Memory (EEPROM) smaller than 1 square micrometer.

[Background of invention]

In the EEPROM technology, long researches have been conducted to reduce cell size in order to pack cells more efficiently on integrated circuit chips. U. S. Patent No. 5,041, 886 discloses an EEPROM cell of medium density (128 K bits). Here, a stacked floating gate-control gate system has adjacent select gates, which are formed after the floating gate and the control gate are in place. Is formed from. This has the advantage that the size of the cell is reduced since the sidewalls take up less space than conventional stacked arrays. In this patent, the select gate and the control gate are controlled by the same word line.

In a paper published in IEDM 91-319 by Yamauchi et al. Entitled “5V Dedicated Virtual Ground Flash Cell with Auxiliary Gate for High Density and High Speed Operation,” a planar select gate ( A planar select gate) is disclosed adjacent to the EEPROM.

[Summary of invention]

The present invention is directed to 128 megabits in which the floating gate and the select gate are formed from polysilicon sidewalls and are separated only by thin vertical oxide members formed on the vertical edges of the polysilicon sidewalls. An improved EEPROM cell suitable for a memory chip.

[Brief Description of Drawings]

1 is a detailed cross-sectional view of an embodiment of the present invention.

2 is a cross-sectional view of a pair of memory cells in accordance with the present invention.

3 is a plan view of a portion of a memory array.

4-9 are cross-sectional views of cells in the course of manufacture.

10A and 10B are cross-sectional views of intermediate stages.

11a and 11b are cross-sectional views of yet another intermediate step.

12 is a schematic circuit diagram of a portion of a memory array in accordance with the present invention.

13 is a schematic diagram of an integrated circuit memory chip formed in accordance with the present invention.

Best Mode for Carrying Out the Invention

Referring to FIG. 1, a source 30 having a gate structure 100 including a selection gate 120, a floating gate 130, and a control gate 140 formed on an integrated circuit silicon substrate 10 may be provided. A dual-gate MOS transistor disposed between and drain 20 is shown in detail. The select gate 120 on the left performs the standard electrical function of allowing access to the cell. The selection gate 120 has a vertical surface and an inclined surface, the vertical surface of which is in contact with the vertical surface of the temporary support. The floating gate 130 on the right stores charges to turn the transistors on or off, so that the floating gate 130 between the source 30 and the drain 20 depends on the charges stored in the gates. The electrical path may be provided or the electrical path may be blocked. The floating gate 130 also has a vertical surface and an inclined surface, the vertical surface of which is in contact with the vertical surface of the vertical insulating member 233 located in the center of the gate structure 100. The control gate 140 located on top of the gate structure 100 controls the charge state of the floating gate 130 as is known in the art.

An advantageous feature of the present invention is that the dimensioning and alignment of the control gate 140 indicated by arrow 260 is the only important lithography step. For other dimensions, optical lithography is not necessary, although the dimensions are smaller than dimension 260, and the other dimensions are obtained using sidewall technology. In the center of the gate structure, the floating gate and the selection gate are separated by a vertical oxide member 233. The vertical oxide member is formed by oxidizing the vertical surface of the poly sidewall (selection gate) after removal of the temporary polysilicon sidewall support layer (temporary polysilicon sidewall support layer is the foundation of the selection gate sidewall). Used as). After removal of the temporary polysilicon sidewall support layer, a second sidewall (floating gate 130) is formed using the vertical oxide member 233 as a vertical reference for the floating gate sidewall. do. Other types and thicknesses of oxides are described below.

Referring to FIG. 2, a cross-sectional view of a pair of memory cells 300 is shown. The pair of memory cells 300 includes two cell structures 100 and 100 ′. These two cell structures 100, 100 'are mirror images of each other and are disposed on both sides of the source 30 so that the two cell structures 100, 100' share a common source. The dimension of one cell, indicated by arrow 305, is illustratively 1.1 μm, which has a layout ground rule of 0.5 μm with a channel length of 0.5 μm, a source width of 0.5 μm and a drain width of 0.5 μm. ground rules). The width for a pair of cells sharing a common source is indicated by arrow 310.

Referring to FIG. 3, a plan view of a portion of a memory array formed in accordance with the present invention is shown. In FIG. 3 the dimensions of the pair of cells 300 (FIG. 2) are shown as 310, 320. For the sake of simplicity, some details have been omitted. In FIG. 3 the same number is given to the counterpart elements corresponding to those in FIGS. 1 and 2. In the center of FIG. 3, the source 30 extends between two select gates 120 (a portion with an upward oblique line from left to right) in the vertical direction in the figure. The floating gate 130 (the portion with the upward diagonal line from the right to the left) is tripped in the vertical direction in the drawing during the definition of the control gate 140, which must be separated. This is because it cannot connect adjacent cells. The control gate 140 extending horizontally across the array extends over the gate 130 extending horizontally throughout the array and over a portion of the gate 120. Two drains 20 are formed on the left and right sides of the gate structure. In FIG. 3, the portion denoted by (70) on the left indicates field oxides or shallow trench insulating areas. The portion labeled 350 at the top right represents the area containing the contacts of the vertical select gate line 120 used to control access to individual cells. This area is shown in more detail in FIGS. 10 and 11. In alternative designs, contact pads of select gates may be alternately placed at the top and bottom of the array to achieve a higher packing density.

A series of cross sectional views of the process flow is shown beginning with FIG. 4 shows an area at the same initial process step as the cell 300 shown in FIG. On the substrate 10, a pad oxide layer 205 having a nominal thickness of 12 nm is formed, followed by a nitride layer 210 having a nominal thickness of 10 nm. A layer of polysilicon or amorphous silicon 220 having a thickness of 400 nm to determine the height of the gate structure is then deposited and patterned to form an aperture 222 in the center. A 12 nm thick gate oxide 125 is grown in this hole, which will become the gate oxide of the select gate 120. In the same step, thermal oxides 230 and 232 are grown on the top surface of poly 220 and on the vertical poly surface of hole 222, respectively. A layer of CVD polysilicon 120 to be the select gate 120 is deposited over the hole 222 and the poly 220. At this time, the contact patterning step shown in FIG. 10 is performed.

Referring to FIG. 5, a double cell after etching the poly 120 by a reactive ion etching (RIE) blanket etch back process to form sidewalls 120 to be a select gate in the future. This is shown. It is desirable to recess the poly spacer 120 below the surface of the poly 220 so that the TEOS layer 123 is formed almost conformally around the poly spacer 120. Do. Thus, after formation of the sidewall spacers 120, an overetch is performed to recess the spacers 120 below the surface of the layer 230. Next, a dry thermal oxide layer 122 having a nominal thickness of 20 nm is grown on the select gate (thermal oxide with good oxide properties, for example low density interface state and high Thermal oxides with break-down voltages are known). After formation of the thermal oxide layer 122, a thick CVD tetraethyl ortho silicate (123) layer having a thickness of about 100 nm is attached to insulate and protect the select gate 120.

Then, as shown in FIG. 6, the photoresist layer 127 is coated and etched back, recessed portions between the select gates 120 on the left and right sides of the figure. Only the photoresist remains.

The polysilicon 220 and its associated layers are then removed by conventional selective wet etching or RIE processes to leave only the gate 120. Then, after removing the remaining photoresist 127, the thermal oxide layer is grown again on the vertical plane of the select gate 120, nitride is deposited by CVD, and another oxidation process is performed to form the vertical ONO dielectric member 233 about 20 nm. Is formed on the vertical surface of the poly selection gate 120 to a final thickness of. Then, after the formation of the vertical ONO member 233 (also referred to as an insulating member or ONO member), the horizontal surfaces of the silicon substrates on the left and right sides of the two selection gates 120 are cleaned and formed in FIG. 7 before the gate 130 is formed. As shown, the tunnel oxide 235 for the floating gate 130 is grown to a thickness of about 6-8 nm.

Thereafter, another polysilicon is attached and reetched to form the polysilicon sidewall 130 on the vertical ONO member 233. This polysilicon will be trimmed to form the floating gate 130 during the definition of the control gate structure 140.

A trim mask is used to separate the selection gate and the floating gate at the end of the mesa, which is illustrated in FIGS. 11A and 11B and will be described later. After the formation of the base portion of the gate structure, it is also generally possible to form a self-aligned source and drain in the memory cell, with a suitable dose and energy depending on the supply voltage and other design parameters, generally 10 ^14. Apply source / drain implants with a current density in the range of -10 ¹⁶ ions / cm ² . Next, as shown in FIG. 8, the ONO layer 237 on the floating gate 130 and the ONO layer 237 'on the horizontal plane of the substrate are replaced with the ONO layer 233 discussed with reference to FIG. Form similarly.

Next, as shown in FIG. 9, the fourth polysilicon layer 140 is attached and patterned to form a control gate structure as shown in FIG. As mentioned above, dimensioning and alignment of the control gate 140 with respect to the remainder of the gate structure is the only important lithographic step in the process. As shown in FIG. 1 and FIG. 2, it does not matter whether the control gate 140 extends over the select gate 120. FIG. Because the TEOS layer 123 is thicker than the tunnel oxide 235 and the ONO 237, the select gate 120 is affected even when a voltage high enough to program the floating gate 130 is applied to the control gate 140. Because do not receive. Thus, this alignment process is relatively insignificant. Dimension 260 of FIG. 1 has a nominal size of 0.5 μm. In the illustrated embodiment, the tolerance for the horizontal position of the gate 140 is nominally ± 0.15 μm, which can be easily achieved with current technology. The patterning of the control gate 140 is performed by overetching the etching of the floating gate 130 to the substrate or the field oxide in the region between the cells shown in FIG. 3 to obtain a trimming effect of the floating gate 130. Is done. The nominal thickness of the control gate 140 is 2500 mm 3 and the thickness of the floating gate 130 is 2000 mm 3. Thus, only a reasonable amount of overetching is needed to remove the floating gate 130 between cells after patterning the control gate 140. An exemplary etching sequence involves first etching the control gate 140 and then breaking through the interpoly ONO layer 237 to form the TEOS layer 123 and the surface oxides 237 ′ and 125. Stop here (because they are thicker than ONO layer 237), and finally perform a trim etch of the floating gate poly using an optional poly etch process.

Referring now to FIGS. 10A and 10B, a step of forming contact pads 352 from poly layer 120 by changing the remaining sidewall structure that unnecessarily connects contact pads of select gates is shown. These contact pads are formed in the area indicated by 350 in FIG. The pad formed from the poly 220 is patterned to form a rectangular island at the bottom of FIG. 10A. In the step of forming the sidewall of the select gate 120, a layer 120 is disposed over the layer 125. The protective layer 121 is formed of a photoresist or other suitable protective layer. In the etching process for forming the sidewalls 120, shown as extending in the vertical direction in the figure, the contact pads 352 and unnecessary sidewall strips 354 connecting and shorting these contact pads 352 are provided. Remains. The rectangular portion, denoted 70, represents a thin trench insulation region or field oxide insulation region that is used as a support for the contact region to provide an insulation and etch stop layer during the padding of the pad.

In FIGS. 11A and 11B, the step of arranging the sidewalls of the floating gate 130 and trimming the unnecessary sidewalls 354 is performed. The trim mask 360 is disposed to expose the area between the pads 360 and the composite structures 120-130 are cut.

Referring to FIG. 12, a schematic of the same portion of the memory array illustrated in FIG. 3 is shown. The pair of cells 300 are indicated by dotted lines. The vertical lines, labeled Vd and Vs, are connected to the source and drain of the memory cell. The source and drain extend continuously in the substrate as shown in parentheses in FIG. Metal or polysilicon lines are formed over the drain and extend downward to the substrate to provide bit line contacts. The source does not transmit a signal and is illustrated as being commonly grounded to the substrate.

The select gate control line, denoted by Vsg and 120 ', is connected to the conventional gate symbol and the select gate, denoted by 120. In this schematic representation, two different symbols, line and gate, are used to illustrate the reality of one continuous strip of polysilicon in the actual structure. Similarly, control gate 140 and floating gate 130 are shown with conventional horizontal line symbols, and the horizontal lines denoted by Vcg and 140 'are used as word lines. The bit line of the memory array is a wire connected to the drain of the cell, separating two adjacent transistor cells. The word line of the memory array is the control gate interconnect line 140 '. The common source may be a diffusion strip in contact with the substrate.

Referring to FIG. 13, a schematic diagram of an integrated circuit EEPROM 400 constructed in accordance with the present invention is shown. In this figure, input / output circuits 410, high voltage steering circuits 420, and charge pumps 430 each perform their usual functions. The charge pump 430 generates the high voltage 10V necessary to perform the write and erase operations, allowing the circuit to operate at only 5V (or less). The high voltage circuit 420 represents a transistor built in a conventional manner that is sufficiently robust to handle + 10V to -10V used for programming and erasure.

In the programming procedure, bias the select gate 120 slightly above the threshold and bias the control gate 140 to a high voltage (10V). Hot electrons from the channel are injected from the source into the floating gate 130. Typical parameters are Vs = 0.0V, Vd = 5.0V, Vsg = 1.5V, Vcg = 10.0V.

In the erase procedure, Fowler-Nordheim tunneling through tunnel oxide 235 is used, and the parameters are Vs = 0.0V, Vd = 5.0V, Vsg = 0.0V, and Vcg = -10.0V.

If the tunneling oxide is 8 nm and the select gate oxide is 10 nm, a read current of 100 μA can be used for a gate voltage of 3 V, typical process parameters and a 0.5 μm design rule. Higher read currents (and corresponding faster operation) will be obtained at a gate voltage of 5V. Typical readout parameters are Vs = 0.0V, Vd = 1.5V, Vsg = 5.0V, Vcg = 5.0V.

Those skilled in the art will be able to readily modify the disclosed embodiments, and the following claims are not limited to the embodiments illustrated herein.

Claims (16)

A select gate, a floating gate, and a control gate disposed on top of the floating gate—these gates are disposed on a channel and have a source and a drain ( and the select gate is separated in a vertical direction from the channel by a gate oxide, the floating gate is separated in a vertical direction from the channel by a tunnel oxide, and the control gate is a second insulator. In an electrically erasable programmable read only memory cell (EEPROM) including a dual gate transistor having a vertically separated from the floating gate by a layer, the select gate and the floating gate are polysilicon. Each formed from polysilicon sidewalls and formed by a thin vertical insulating member. EEPROM cell, characterized in that separated in the horizontal direction. The gate of claim 1, wherein the select gate is disposed adjacent to the source, the floating gate is disposed adjacent to the drain, the control gate extends over at least a portion of the select gate, and the select gate is selected from the first gate. Separated from the control gate in a vertical direction by a predetermined dielectric layer of one, and the floating gate is separated from the control gate by a second predetermined dielectric layer, the gate oxide, the first One predetermined dielectric layer, the tunnel oxide and the second predetermined dielectric layer are pre-determined on the control gate sufficient to cause tunneling of electrons through the tunnel oxide between the channel and the floating gate. Predetermined program voltage is the gate acid Through the water fit a cause tunneling of electrons EEPROM cell, it characterized in that a relationship such that insufficient. 2. The gate of claim 1 wherein the selection gate has a vertical surface in contact with the vertical insulation member and a second surface opposite the vertical surface, and the floating gate is in the vertical surface in contact with the vertical insulation member and opposite the vertical surface. EEPROM cell having a second side, wherein the control gate extends over at least a predetermined portion of sai floating gate. 3. The gate of claim 2 wherein the selection gate has a vertical surface in contact with the vertical insulation member and a second surface opposite the vertical surface, wherein the floating gate is formed of a vertical surface in contact with the vertical insulation member and a second surface opposite the vertical surface. 2. The EEPROM cell of claim 2, wherein the control gate extends over at least a predetermined portion of said floating gate. A gate structure disposed over the substrate and a source and a drain disposed across the channel in a silicon substrate, wherein the gate structure is disposed in series between the source and the drain. And a control gate disposed at least above the floating gate to control the floating gate and the charge state of the floating gate.-A method of forming a dual-gate field effect transistor. Growing a gate oxide over the channel, forming a sidewall selection gate of polysilicon over the gate oxide to contact a temporary sidewall support layer, and a vertical intermediate surface on the sidewall selection gate ( the temporary to expose a vertical intermediate surface A step of removing the side wall and the support layer, and forming a sidewall dielectric separation (separation sidewall dielectric) on the surface of the vertical middle; Growing a tunnel oxide over said channel adjacent said sidewall isolation dielectric; Forming a floating gate adjacent the sidewall isolation dielectric to form a double gate structure in which the select gate and the floating gate are separated by the sidewall isolation dielectric, and self-aligned with respect to the double gate structure. forming a self aligned source and a drain in the substrate, and forming a control gate over at least the floating gate. The method of claim 5, further comprising forming a thick protective layer over the selection gate prior to forming the floating gate, and trimming the floating gate by cutting through the floating gate. and double etching the control gate to a predetermined amount sufficient to trim the thick protective layer but insufficient to cut the thick protective layer such that the select gate is not affected by the trimming of the floating gate. How to form an effect transistor. A double gate field effect transistor comprising an array of double gate field effect transistors, each of the double gate field effect transistors comprising a source and drain disposed across a channel in a silicon substrate and a gate structure disposed over the substrate, The gate structure includes a select gate disposed in series between the source and the drain and a control gate disposed at least above the floating gate to control the charge state of the floating gate and the floating gate. Wherein the source and drain extend along a first axis, the floating gates extend parallel to the first axis, and the select gates in the array of dual gate field effect transistors. Extend parallel to the axis, the plurality of said Extend through gate transistors and terminate at a set of contacts and the control gates extend along a second axis perpendicular to the first axis—to form an EEPROM memory array. In the method; Forming a gate oxide over the channel, forming a sidewall select gate of polysilicon over the gate oxide to contact a temporary sidewall support layer, and a vertical intermeiate on the sidewall select gate. removing the temporary sidewall support layer to expose a surface, and forming a sidewall separation dielectric on the vertical intermediate surface; Growing tunnel oxide over said channel adjacent said sidewall isolation dielectric, and forming a floating gate adjacent said sidewall isolation dielectric, whereby said select gate and said floating gate are separated by said sidewall isolation dielectric Forming a gate structure, forming a self-aligned source and drain in the substrate relative to the double gate structure, forming a control gate over at least the floating gate, and forming the sidewalls; Prior to forming the select gate, patterning a portion of the material of the sidewall select gate in a contact pattern such that the contacts are formed simultaneously with the sidewall select gate. Forming method. 8. The method of claim 7, wherein the contacts are formed on an unerlying insulating layer that serves as a tech stop. Input / output means for input and output of data to an integrated circuit EEPROM, voltage generating means for generating a predetermined program voltage, and orienting the program voltage along predetermined program paths in the circuit. A memory array comprising a set of dual gate field effect transistor memory cells, comprising a voltage steering means for directing and a memory array. Each comprising a select gate, a control gate and a floating gate disposed between a common source and a drain over the channel, the select gate comprising in a vertical direction from the channel by a gate oxide, the floating gate being in tunnel tunnel. In the vertical direction from the channel by And the control gate is separated in a vertical direction from the floating gate by a second insulator layer.-In an integrated circuit EEPROM, the select gate and the floating gate are respectively formed from polysilicon sidewalls having a vertical plane, and And horizontally separated by a thin vertical insulating member adjacent the vertical plane of the selection gate and the floating gate. 10. The device of claim 9, wherein the select gate is disposed adjacent to the source, the floating gate is disposed adjacent to the drain, the control gate extends over at least a portion of the select gate, and the select gate comprises Separated from the control gate in a vertical direction by a predetermined dielectric layer of one, and the floating gate is separated from the control gate by a second predetermined dielectric layer, the gate oxide, the first One predetermined dielectric layer, the tunnel oxide and the second predetermined dielectric layer are pre-determined on the control gate sufficient to cause tunneling of electrons through the tunnel oxide between the channel and the floating gate. Predetermined program voltage is the gate oxidation An integrated circuit EEPROM cell, having a relationship that is insufficient to cause tunneling of electrons through water. 10. The device of claim 9, wherein the cells are arranged in pairs of cells sharing a common source and the select gates are disposed between the common source of the cells and the floating gates so that the cells are relative to each other. Integrated circuit EEPROM which results in mirror images of another. 12. The apparatus of claim 10, wherein: the cells are arranged in pairs of cells sharing a common source; The select gates are disposed between the common source of the cells and the floating gates such that the cells are mirror images of each other. 12. The device of claim 11, wherein the drains of the cells are bit lines of the EEPROM; And a set of interconnecting members connecting the control gates are word lines of the EEPROM. 13. The method of claim 12 wherein the drain of the cell is a bit line of the EEPROM; And a set of interconnecting members connecting the control gates are word lines of the EEPROM. 10. The device of claim 9, wherein a set of bit lines extends through the memory array to a set of bit line contacts disposed on an insulating layer such that signals are along the set of bit lines. Integrated circuit EEPROM. 16. The EEPROM of claim 15 wherein the bit line contacts are extensions of the select gates and are formed of the same material.