KR100287883B1 - Array of Devices of Nonvolatile Memory and Manufacturing Method Thereof - Google Patents

Abstract

To provide an array of a nonvolatile memory device capable of performing an independent erase operation between neighboring cells and increasing a coupling ratio of a control gate, and a method of manufacturing the same. An array of volatile memory devices includes a substrate in which an isolation region and an active region are defined, two stacked first gate insulating layers, a first floating gate, and a first floating gate in the active region between the isolation regions, and are automatically aligned in the substrate. An impurity region buried in one direction, a buried insulating film formed on the impurity region, a second floating gate formed in a predetermined pattern so as to partially overlap with the first floating gate, a second gate insulating film formed on the second floating gate, and the second On the second floating gate in the row direction so that one side of the floating gate is exposed. Generated control line and the gate, characterized by the second configured including an erase gate line formed in the row direction such that contact with the exposed one side surface of the floating gate.

Description

Array of Devices of Nonvolatile Memory and Manufacturing Method Thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a nonvolatile memory device and a manufacturing method thereof.

In general, the effective cell size of a memory cell that determines the density of nonvolatile memory such as flash EEPROM (Flash Electrically Erasable Programmable Read Only Memory) and EEPROM is determined by two factors.

One of the two elements is the size of the cell and the other is the array structure of the cell. The minimum cell structure in terms of memory cells is a simple stacked-gate structure.

Recently, as the application of nonvolatile memory such as flash EEPROM and flash memory card is expanded, research and development on this nonvolatile memory is required.

The biggest problem when using non-volatile semiconductor memory such as flash EEPROM, EEPROM as a mass storage media is that the cost-per-bit of the memory is too expensive.

In addition, a chip that consumes low power is required for thermal integration to a portable product.

Recently, research on multibit-per-cell has been actively conducted as a way to lower the price per bit.

The density of the conventional nonvolatile memory has a one-to-one correspondence with the number of memory cells. In contrast, multi-bit cells store more than one bit of data in one memory cell, thereby greatly increasing the storage density of data in the same chip area without reducing the size of the memory cell.

In order to implement the multi-bit cells, three or more threshold voltage levels must be programmed in each memory cell.

For example, in order to store two bits of data per cell, each cell must be programmed at a threshold voltage level of 2 ² = 4, that is, four levels.

At this time, the threshold voltage levels of the four steps logically correspond to logic states of 00, 01, 10, and 11.

The biggest challenge in such a multi-level program is that each threshold voltage level has a statistical distribution, which is about 0.5V.

Therefore, as each threshold voltage level is precisely adjusted to reduce the distribution, more threshold voltage levels can be programmed, and the number of bits per cell can be increased. As a method of reducing the above voltage distribution, a technique of performing programming by repeating a program and an inquiry is generally used.

In the above technique, a series of voltage pulses is applied to a cell to program the nonvolatile memory cell at a desired threshold voltage level.

In order to verify whether the cell has reached a desired threshold voltage level, a reading process is performed between voltage pulses. During each inquiry, the programming process is completed when the inquired threshold voltage level reaches a desired threshold voltage level value.

In such a method of repeating the program and inquiry, it is difficult to reduce the error distribution of the threshold voltage level due to the finite program voltage pulse width. In addition, since the algorithm for repeating the program and the inquiry is implemented in a circuit, the area of the peripheral circuit of the chip is increased and the repetitive method has a long program time.

FIG. 1A is a cross-sectional view of a typical simple stacked nonvolatile memory device, and FIG. 1B is a symbol of a typical nonvolatile memory device cell.

As shown in FIG. 1A, a floating gate 3 is formed on the p-type semiconductor substrate 1 with a tunneling oxide film 2 interposed therebetween, and a control gate 5 is formed on the floating gate 3. A dielectric film 4 is formed between the control gate 5 and the floating gate 3.

An n-type source 6a region and a drain 6b region are formed in the surface of the p-type semiconductor substrate 1 on both sides of the floating gate 3.

Although the effective cell size of the general simple stacked nonvolatile memory cell configured as described above is small, the coupling constant value of the control gate 5 is small, and in particular, the smaller the effective cell size of the nonvolatile memory cell is, the smaller the coupling constant becomes. there is a problem.

Therefore, in order to prevent the coupling constant from becoming small, the dielectric film 4 between the floating gate 3 and the control gate 5 is formed of an oxide nitride oxide (ONO) film, but this process is also complicated. And high temperature annealing process is required.

Meanwhile, as shown in FIG. 1B, each nonvolatile memory cell has a floating gate 3 as described above with reference to FIG. 1B, and a control gate that controls the amount of charge supplied to the floating gate 3 for programming. 5) and field effect transistors for reading (or querying) the amount of charge carriers provided to the floating gate 3 during programming.

The field effect transistor consists of a floating gate 3, a source 6a, a drain 6b, and a channel region 7 located between the drain 6b and the source 6a.

The operation of the nonvolatile memory cell configured as described above causes a current to flow between the drain 6b and the source 6a when a sufficient voltage is applied to the control gate 5 and the drain 6b to cause programming.

When the current reaches a value which is equal to or smaller than the reference current, the program completion signal is generated.

Hereinafter, a conventional nonvolatile memory device will be described with reference to the accompanying drawings.

FIG. 2A is a circuit diagram illustrating a conventional nonvolatile memory device, and FIG. 2B is a circuit diagram illustrating a conventional nonvolatile memory device without a metal contact having a simple stacked structure. FIG. 2C is a source and a drain. Fig. 1 is a circuit diagram of a conventional nonvolatile memory device which does not require a metal contact separated from the above.

As shown in FIG. 2A, a plurality of metal bit lines 9 are disposed at regular intervals in a column direction and a plurality of word lines in a direction orthogonal to the plurality of metal bit lines 9. ) 10 are arranged, and one common source line 11 is arranged for every two word lines 10 in the same direction as the plurality of word lines 10.

As described above in FIG. 1B, the drains 6b of the two cells of the nonvolatile memory cell are connected to the metal bit line 9, and the source 6a of the nonvolatile memory cell is connected to the common source line 11. . Therefore, since one metal contact 8 is required per two cells, the effective size of the memory cell considering the metal contact 8 is very large.

That is, as illustrated in FIG. 1A, a general nonvolatile memory array is composed of cells of a minimum size of a simple stacked structure, but the actual effective size is limited by the pitch of the metal contact 8.

In order to solve the above problems, an array without metal contacts has been proposed, which can reduce the number of metal contacts.

That is, an array without an ideal metal contact composed of cells having a simple stacked structure is shown. The array without an ideal metal contact composed of cells having a simple stacked structure provides a minimum effective cell size.

However, as described above, an array having no ideal metal contact composed of cells having a simple stacked structure has a program disturb phenomenon in which an unselected cell adjacent to a program word line direction is programmed or erased.

The array structure of the nonvolatile memory cell is an array structure without an ideal metal contact. Instead, as shown in FIG. 2B, a memory cell is selected as a split-channel cell, which is an asymmetric structure having a select gate 12. I use it.

In such a case, not only the program disturb may be prevented during programming by hot electron injection, but also an over erase problem, which is another problem of a simple stacked structure cell, may be eliminated.

As shown in FIG. 2B, the nonvolatile memory cell includes a plurality of word lines 10 disposed on a semiconductor substrate (not shown) at a predetermined distance from each other, and a plurality of squares at a predetermined distance from each other. A plurality of bit lines 13 are arranged orthogonally to the plurality of word lines 10 so as to be formed, and a plurality of nonvolatile memory cells are arranged one by one in each square.

In FIG. 2B, each nonvolatile memory cell has a floating gate 3, as described above in FIG. 1B, a control gate 5 for adjusting the amount of charge supplied to the floating gate 3 for programming, and And a field effect transistor for reading (or querying) the amount of charge carriers provided to the floating gate 3.

The field effect transistor consists of a floating gate 3, a source 6a, a drain 6b, and a channel region 7 located between the drain 6b and the source 6a.

The control gate 3 of each nonvolatile memory cell is connected to an adjacent word line 10, and the source 6a of the nonvolatile memory cell in one square is the drain 6b of the nonvolatile memory cell located in the next square. Are jointly connected to adjacent bit lines 13 together.

In addition, a select transistor 12 is connected to the bit line 13, and a metal contact 8 is connected to the select transistor 12 for every 32 or more nonvolatile memory cells in a column direction.

Therefore, the effective cell size can be reduced.

However, even in this case, the size of the unit cell increases due to the gate of the select transistor.

In particular, programming by tunneling, which is a low power operation, is impossible.

This phenomenon is because two cells adjacent in the direction of the word line 10 are subjected to exactly the same bias condition as can be easily inferred from the figure.

In order to eliminate the above problems and enable a tunneling program, an array without a metal contact composed of cells having a simple stacked structure is used as shown in FIG. 2C.

That is, a plurality of metal data lines 9 arranged at regular intervals in a column direction are disposed, and each bit line is arranged in the same direction as the plurality of metal data lines 9. The source line 15 and the drain line 21b are respectively completely separated from each other.

The source 6a of the nonvolatile memory cell described above in FIG. 1B is connected to the source line 15, and the drain 6b of the nonvolatile memory cell is connected to the drain line 14.

One metal contact 8 is connected to each of the metal data lines 9, and the control gate 5 is arranged in a direction orthogonal to a bit line divided into a source line 15 and a drain line 14. Are connected to each of the four word lines 10.

However, in such a structure, an increase in unit cell size due to separation of bit lines is inevitable.

3 is a cross-sectional view illustrating a channel-separated conventional nonvolatile memory device having a separated gate.

As shown in FIG. 3, a floating gate 3 is formed on the p-type semiconductor substrate 1 with a tunneling oxide film 2 interposed therebetween, and a control gate 5 is formed on the floating gate 3. The select gate 17 is formed on the p-type semiconductor substrate 1 including the control gate 5 and the floating gate 3 with an insulating film 16 interposed therebetween.

A dielectric film 4 is formed between the control gate 5 and the floating gate 3, and then floats within the surface of the p-type semiconductor substrate 1 on one side of the floating gate 3. A source 6a is formed so as to be offset from the gate 3, and a drain 6b is formed in the surface of the p-type semiconductor substrate 1 on the other side of the floating gate 3.

4A is a cross-sectional view illustrating a conventional channel-separated nonvolatile memory device, and FIG. 4B is a cross-sectional view illustrating a nonvolatile memory device in the channel width direction of FIG. 4A.

First, in the channel-separated nonvolatile memory device, as shown in FIG. 4A, the floating gate 3 is formed on the p-type semiconductor substrate 1 at regular intervals, and the control gate 5 is formed on the floating gate 3. do.

Subsequently, a tunneling oxide film 2 is formed between the floating gate 3 and the p-type semiconductor substrate 1, and a dielectric film 4 is formed between the floating gate 3 and the control gate 5. do.

Next, a source 6a is formed in the surface of the p-type semiconductor substrate 1 on one side of the floating gate 3 so as to be offset from the floating gate 3, and the other side of the floating gate 3. A drain 6b is formed in the surface of the p-type semiconductor substrate 1.

In the nonvolatile memory device in the channel width direction, as shown in FIG. 4B, a field oxide film 18 is formed on the p-type semiconductor substrate 1 to insulate the cell from the cell, and the field oxide film 18 is formed. The gate insulating film 19 is formed on the p-type semiconductor substrate 1 in between.

Subsequently, a floating gate 3 is formed on the gate insulating film 19 to overlap with the adjacent field oxide film 18, and a dielectric film 4 is formed on a predetermined region of the floating gate 3. The control gate 5 is formed on the dielectric film 4.

A gate cap insulating film 20 is formed on the control gate 5, sidewall insulating films 21 are formed on both side surfaces of the control gate 5 and the gate cap insulating film 20, and the field oxide film 18 An erase gate 17 is formed on a surface and the gate cap insulating layer 20.

Subsequently, a tunneling oxide layer 22 is formed on a side surface of the floating gate 3 and the erase gate 17 adjacent thereto.

The conventional nonvolatile memory device as described above has the following problems.

First, an array without an ideal metal contact composed of cells having a simple stacked structure may cause a program disturb problem in which an unselected cell adjacent to a word line direction is programmed or erased during programming.

Second, the source select transistor in an array without a modified metal contact composed of cells having a simple stacked structure has a problem of causing a source voltage drop.

Third, in the channel-separated structure, the process of self-aligning each channel of the selection transistor and the storage transistor with the respective gates is difficult, so that the electrical characteristics of the cell may be unevenly distributed between chips or within the chip, which may cause chip failure.

Fourth, the cell of the nonmagnetic alignment process in the channel-separated structure has a disadvantage in reducing the cell size.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides an array of a nonvolatile memory device capable of performing an independent erase operation between neighboring cells and increasing a coupling ratio of a control gate, and a method of manufacturing the same. Its purpose is to.

1A is a cross-sectional view of a typical simple stacked nonvolatile memory device

1B is a symbol of a typical nonvolatile memory device cell

2A is a circuit diagram illustrating a conventional nonvolatile memory device.

FIG. 2B is a circuit diagram of a conventional nonvolatile memory device that does not require a metal contact having a simple stacked structure.

2C is a circuit diagram of a conventional nonvolatile memory device that does not require a metal contact in which a source and a drain are separated.

3 is a structural cross-sectional view of a channel-separated conventional nonvolatile memory device having a separated gate.

4A is a cross-sectional view of a structure of a channel-separated conventional nonvolatile memory device

4B is a cross-sectional view of a structure of a conventional nonvolatile memory device showing a cross section in the channel width direction of FIG. 4A.

5 is a circuit diagram illustrating a nonvolatile memory device of the present invention.

6 is an array layout diagram of a nonvolatile memory device of the present invention.

FIG. 7A is a structural cross-sectional view along the line II of FIG. 6

7B is a structural cross-sectional view taken along line II-II of FIG. 6.

8A to 8I are cross-sectional views of lines I-I and II-II of FIG.

Explanation of symbols for the main parts of the drawings

31: semiconductor substrate 32: isolation oxide film

33: first gate oxide film 34: first polysilicon line

35: first cap oxide film 36: first sidewall spacer

37a, 37b, 37c: bit line 38: buckled oxide film

39: first floating gate 40: high temperature low pressure oxide film

41: second polysilicon line 42: second floating gate

43: second gate oxide film 44: control gate line

45 cap high-temperature low-pressure oxide film 46 second side wall spacer

47: erase gate line

In order to achieve the above object, an array of a nonvolatile memory device according to an embodiment of the present invention includes a substrate in which an isolation region and an active region are defined, two first gate insulating layers and a first floating gate stacked in an active region between the isolation regions, An impurity region automatically aligned with the first floating gate and buried in one direction in the substrate, an investment insulating film formed on the impurity region, a second floating gate formed in a predetermined pattern to partially overlap the first floating gate, and the second floating gate A second gate insulating layer formed on the second floating gate, a control gate line formed on the second floating gate in a row direction so that one side surface of the second floating gate is exposed, and a row gate contacting the exposed side surface of the second floating gate And an erase gate line formed therein.

In addition, the method of manufacturing an array of a nonvolatile memory device of the present invention having the above-described array includes defining an isolation region and an active region on a substrate, wherein two insulating layers, a polysilicon line, and a first insulating layer are formed in each active region between the isolation regions. Forming a stack structure of two cap insulating films, forming a first sidewall spacer between the insulating film, the polysilicon line and the first cap insulating film, and impurity in one direction in the substrate to be automatically aligned with the polysilicon line. Forming a region, forming a buried insulating film on the surface of the impurity region, patterning the insulating film and the polysilicon line in a square to form two first gate insulating films and two first floating gates in the active region; Forming an interlayer insulating layer having a contact hole so that a portion of the first floating gate is exposed; Forming a second floating gate having a predetermined pattern to contact the first floating gate on the contact hole and the interlayer insulating layer adjacent thereto, and forming a second gate insulating layer on the second floating gate. Forming a control gate line partially overlapping with the second floating gate and orthogonal to the impurity region, and having a contact hole to expose one side surface of each of the second floating gate and the second gate insulating layer. Forming a second cap insulation layer, forming a second sidewall spacer on the side of the contact hole, and removing the gate line in a direction parallel to the control gate line so as to contact the second floating gate through the contact hole. It characterized in that it comprises the step of forming.

Hereinafter, an array and a method of manufacturing the nonvolatile memory device of the present invention will be described with reference to the accompanying drawings.

5 is a circuit diagram illustrating a nonvolatile memory device of the present invention, and FIG. 6 is an array layout diagram of the nonvolatile memory device of the present invention.

7A is a structural cross-sectional view of the nonvolatile memory device of the present invention on the line II of FIG. 6, and FIG. 7B is a cross-sectional view of the nonvolatile memory device of the present invention on the line II-II of FIG. 6.

The nonvolatile memory device of the present invention takes a stacked cell structure such as an ETOX cell and has an erase gate for erasing using Fowler Nordheim Tunneling.

Referring to the drawings in detail, there are a plurality of EEPROM cells having floating gates, control gates, and source / drain regions, as shown in FIGS. 5, 6, 7a, and 7b.

In this case, the floating gate is formed of two layers of the first and second floating gates 39 and 42, and the second floating gate 42 is the first floating gate 39 except for one side of the first floating gate 39. Are stacked on.

The control gate is formed on the first and second floating gates 39 and 42 of each Y pyrom cell to form a line. That is, the control gate line 44 overlaps the upper portion of the second floating gate 42 so that one side of the second floating gate 42 of each Y pyrom cell is exposed. In this case, the control gate line 44 serves as a word line (W / L) that transfers a driving voltage to a plurality of ypyrom cells in a row direction.

A plurality of erase gate lines 47 are formed in a row direction to be connected to one exposed area of the second floating gate 42.

The source / drain region is composed of N + mem regions which are self-aligned to the first floating gate 39. The source region is formed in common between two adjacent ypyrom cells to form a common source line 37b (C S). / L), and one drain region is formed in each of the two pyrom cells.

At this time, each of the two cells is isolated by the isolation oxide film 32, and the drain region of each of the two pyrom cells constitutes a plurality of bit lines (B / L) 37a and 37c in a direction orthogonal to the word line (W / L). do.

Since the first and second floating gates 39 and 42 are not self-aligned and floated in the control gate line 44, the erasing gate line 47 is not shared by two cells.

Since there is no contact in the memory array, the effective cell size can be reduced compared to ETOX.

A method of manufacturing the nonvolatile memory device of the present invention having such an array will be described with reference to the accompanying drawings.

8A to 8I are process cross-sectional views of the nonvolatile memory device of the present invention.

At this time, the left side of the figure is a process flow chart on the line I-I of FIG. 6, and the right side is a process flow chart on the line II-II of FIG.

In the method of manufacturing a nonvolatile memory device according to the present invention, as shown in FIG. 8A, an initial oxide film and a nitride film are deposited on a P-type semiconductor substrate 31 having active and field regions, and a photoresist film is coated on the nitride film. The photoresist layer is patterned so that the initial oxide layer and the nitride layer of the portion defined as the region are exposed. Subsequently, the semiconductor substrate 31 is exposed by removing the initial oxide film and the nitride film by using the patterned photoresist film as a mask. (Not shown in the drawing)

Thereafter, an isolation oxide film 32 is formed on the semiconductor substrate 31 exposed by the thermal oxidation process. The isolation oxide film 32 is formed so that two cells enter therebetween.

After the first oxide film, the first polysilicon layer, and the second oxide film are deposited in this order, the first gate oxide film 33 and the first polysilicon line are anisotropically etched by etching the first oxide film, the first polysilicon layer, and the second oxide film. 34 and the first cap oxide film 35 are formed. In this case, two first polysilicon lines 34 are formed in the active region between the isolation oxide layers 32.

As shown in FIG. 8B, the first sidewall spacers are formed along both sides of the first gate oxide layer 33, the first polysilicon line 34, and the first cap oxide layer 35 by anisotropically etching the third oxide layer. Form 36).

As shown in FIG. 8C, a high concentration of N-type impurity ions is implanted into the semiconductor substrate 31 using the first polysilicon line 34 and the first sidewall spacer 36 as a mask. Thereafter, a high concentration of N-type impurity ions are diffused into the semiconductor substrate 31 by the diffusion process to be buried. Accordingly, a common source line 37b is formed between the first polysilicon lines 34, and one bit line 37a and 37c is formed on one side of the first polysilicon line 34, respectively.

Thereafter, a oxidized film 38 is formed on the surfaces of the bit lines 37a and 37c and the common source line 37b by a thermal oxidation process. In this case, the first sidewall spacer 36 serves to widen the channel of the memory cell and to reduce the ion implantation region for forming the bit lines 37a and 37c and the common source line 37b, and the first cap insulation layer 35. The first polysilicon line 34 is prevented from being oxidized when the methoxide oxide film 38 is formed.

As shown in FIG. 8D, the first polysilicon line 34 is etched in a direction perpendicular to the bit lines 37a and 37c and the common source line 37b, thereby forming the bit lines 37a and 37c and the common source line 37b. After the first floating gate 39 is formed to have a quadrangular shape between the first and second sides, the first sidewall spacers 36 on both sides of the first cap insulating layer 35 and the first cap insulating layer 35 are etched and removed.

As shown in FIG. 8E, after the high temperature low pressure oxide film 40 is deposited on the entire surface of the resultant material, the high temperature low pressure oxide film 40 in a direction perpendicular to the bit lines 37a and 37c is exposed to expose the upper portion of the first floating gate 39. ) To isolate the first floating gate 39 vertically adjacent to each other in the layout diagram of FIG. 6.

As shown in FIG. 8F, after depositing the second polysilicon layer on the entire surface of the resultant layer, the second polysilicon layer is anisotropically etched in a direction orthogonal to the bit lines 37a and 37c on the first floating gate 39. The second polysilicon line 41 is formed.

Next, as shown in FIG. 8G, the second polysilicon line 41 is anisotropically etched to be in contact with the first floating gate 39 and float in a square shape at a predetermined interval to form the second floating gate 42. do. At this time, the second floating gate 42 is formed to be as long as possible in the direction of the control gate line 44 to be formed later in order to increase the coupling ratio of the cell.

Next, as shown in FIG. 8H, a thin second gate oxide film 43 is formed on the second floating gate 42 by a thermal process. After the third polysilicon layer is deposited on the entire surface of the resultant product, the control gate line 44 is formed by anisotropically etching the third polysilicon layer so as to have one direction orthogonal to the bit lines 37a and 37c. Thereafter, after the fourth oxide film is sequentially deposited on the entire surface, the contact hole is formed by anisotropically etching the fourth oxide film so that one side surface of each of the second floating gate 42 and the second gate oxide film 43 of each y-pyrom cell is exposed. The cap high temperature low pressure oxidation film 45 which has is formed.

As shown in FIG. 8I, the fifth oxide film is deposited and then etched back to form a second sidewall spacer 46 on the contact hole side surface.

Thereafter, a fourth polysilicon layer is deposited on the entire surface, and the fourth polysilicon layer is photoetched to form a direction parallel to the control gate line 44 between the control gate lines 44. To form. In this case, the erase gate line 47 is in contact with the second floating gate 42 through the contact hole. At this time, since the second floating gate 42 is floated, one erase gate can be formed per one ypyrom cell. .

As such, when the erasing gate line 47 is formed between the control gate lines 44, the second floating gate 42 and the erasing gate line 47 meet through the contact hole, and thus the second floating gate 42 is formed. And the area where the erase gate line 47 meets can be minimized.

The operation of the nonvolatile memory device of the present invention manufactured as described above is as follows.

The program operation uses a channel hot electron injection scheme such as conventional ETOX.

That is, by applying a positive voltage to the control gate line 44 and the drain region (bit line of each cell), the hot electrons generated by the strong electric field of the drain region are first and second floating gates 39 by the channel hot electron injection method. , 42).

The erase operation is performed by applying a strong voltage to the erase gate line 47 to extract electrons charged in the first and second floating gates 39 and 42 using Fowler Nordheim tunneling.

In this way, the state of the cell is read by determining the difference between the threshold voltages according to the amount of electrons filled in the first and second floating gates 39 and 42 during programming and erasing.

The above-described array of the nonvolatile memory device of the present invention and a method of manufacturing the same have the following effects.

First, since a cell that does not require a metal contact having a simple stacked structure is formed, a nonvolatile memory cell having a minimum effective size can be manufactured, thereby increasing the degree of integration of the cell.

Second, since the bit line and the common source line are buried in the semiconductor substrate, the process can be simplified.

Third, since a cell having a simple stacked structure without forming the selection transistor is formed, the unit cell size can be made smaller than that of the cell using the selection transistor, and it is advantageous to increase the integration degree of the device.

Fourth, since the electrons charged in the floating gate are erased by using the erase gate, it is advantageous to secure the reliability of the device because a thin tunneling oxide film is not required.

Fifth, it is possible to minimize the area where the erase gate and the second floating gate meet by forming an erase gate so as to meet the second floating gate of each cell on one side, and by forming one erase gate per cell, Can be avoided.

Claims (6)

A substrate in which an isolation region and an active region are defined, Two first gate insulating layers and a first floating gate stacked in an active region between the isolation regions; An impurity region which is automatically aligned with the first floating gate and is buried in one direction in the substrate, A buried insulating film formed on the impurity region, A second floating gate formed in a predetermined pattern to partially overlap the first floating gate, A second gate insulating film formed on the second floating gate, A control gate line formed on the second floating gate in a row direction so that one side of the second floating gate is exposed; And an erase gate line formed in a row direction to be in contact with the exposed one side of the second floating gate. 2. The nonvolatile memory device of claim 1, wherein the impurity region constitutes a common source line between the first floating gate and a bit line between the first floating gate and the isolation region. Array. The array of claim 1, wherein the second floating gate is formed as long as possible in the direction of the control gate line. Defining an isolation region and an active region in the substrate, Forming two stacked structures of two insulating films, a polysilicon line, and a first cap insulating film in each active region between the isolation regions; Forming a first sidewall spacer between the insulating film, the polysilicon line, and a first cap insulating film; Forming an impurity region in one direction in the substrate to be automatically aligned with the polysilicon line; Forming a buried insulating film on the impurity region surface; Patterning the insulating film and the polysilicon line in a square to form two first gate insulating films and two first floating gates in the active region; Forming an interlayer insulating layer having a contact hole so that a portion of the first floating gate is exposed; Forming a second floating gate having a predetermined pattern to contact the first floating gate on the contact hole and the interlayer insulating layer adjacent thereto; Forming a second gate insulating film on the second floating gate; Forming a control gate line partially overlapping the second floating gate and orthogonal to the impurity region; Forming a second cap insulating film having a contact hole so that one side of each of the second floating gate and the second gate insulating film is exposed; Forming a second sidewall spacer on the contact hole side surface; And forming an erasing gate line in a direction parallel to the control gate line so as to contact each of the second floating gates through the contact hole. 5. The method of claim 4, wherein the impurity region is formed by implanting ions into the front surface of the substrate so as to be automatically aligned with the polysilicon line and thermally diffusing them. The method of claim 4, wherein the buried insulating film is formed on a surface of the impurity region by a thermal oxidation process.