KR100267769B1 - Method for manufacturing nonvolatile memory device - Google Patents

Abstract

PURPOSE: A method of manufacturing non-volatile memory device is provided to prevent the device characteristic due to hole injection into the tunneling oxidation layer by band-to-band tunneling which occurs when erasing the source side by poly-to-poly erase, and to exclude an additional process to form the erasing gate. CONSTITUTION: A buried layer(23) is formed on the semiconductor substrate(21) to have a certain interval. A first insulation layer(24a) is formed on the surface of the semiconductor device in the area of the buried layer. A first HLD layer(25), a nitride layer(26) and a second HLD layer(27) are successively deposited on the first insulation layer. A tunneling oxidation layer(28) is formed on the surface of the semiconductor substrate. A floating gate(29) is formed to overlap with the insulation layer by inserting the tunneling oxidation layer. The second HLD layer is selectively removed to define the erase gate region. On the overall surface of the semiconductor substrate including the floating gate, a second insulation layer is deposited. Putting the second insulation layer on the center, a control gate is formed on the floating gate, and an erase gate is formed on the erase gate region. Third and fourth insulation layers(30,35) are deposited to have a contact hole, exposing a predetermined portion of the control gate. A word line(34) is formed to connect with the control gate through the contact hole.

Description

Manufacturing method of nonvolatile memory device

The present invention relates to a semiconductor device, and more particularly to a method of manufacturing a nonvolatile memory device.

Recently, as the application of nonvolatile memory such as Flash Elecrically Erasable Programmable Read Only Memory (EEPROM) and Flash Memory Card is expanded, research and development on the nonvolatile memory is required.

In general, the biggest problem when using a nonvolatile semiconductor memory such as EEPROM, flash EEPROM as a mass storage media (data storage media) is that the cost-per-bit of the memory is too expensive.

In addition, a chip that consumes low power is required for application to a portable product.

Recently, researches on multibit-per-cells have been actively conducted to reduce the price per bit of the memory.

The bit density of a conventional nonvolatile memory has a one-to-one correspondence with the number of memory cells.

On the other hand, the multi-bit cell stores two or more bits of data in one memory cell, thereby greatly increasing the storage density of the data in the same chip area without reducing the size of the memory cell.

To implement such a multi-bit cell, three or more threshold voltage levels must be programmed in each memory cell.

For example, in order to store two bits of data per cell, each cell must be programmed at a threshold voltage level of 2 ² = 4, that is, four levels.

At this time, the threshold voltage levels of step 4 logically correspond to logic states of 00, 01, 10, and 11.

The biggest challenge in such a multi-level program is that each threshold voltage level has a statistical distribution, which is about 0.5V.

Therefore, as a method of reducing the threshold voltage level, a technique of performing programming by repeating a program and an inquiry is generally used.

In this technique, a series of voltage pulses are applied to a cell to program a nonvolatile memory cell at a desired threshold voltage level.

A reading process is performed between the voltage pulses to verify whether the cell has reached the desired threshold voltage level.

During each inquiry, the programming process stops when the queried threshold voltage level value reaches a desired threshold voltage level value.

In such a method of repeating the program and inquiry, it is difficult to reduce the error distribution of the threshold voltage level due to the finite program voltage pulse width.

In addition, since the algorithm that repeats the program and inquiry is implemented as a circuit, the area of the peripheral circuit of the chip is increased.

And the above repetitive method has a disadvantage that the program time is long.

To eliminate this drawback, SunDisk's R.Cernea introduced a technique for querying at the same time as programming.

1A is a circuit diagram illustrating a general nonvolatile memory cell.

As shown in Fig. 1A, the nonvolatile memory cell is composed of a control gate 1, a floating gate 2, a source 3, a channel region 4 and a drain 5.

If enough voltage is applied to the control gate 1 and the drain 5 to cause a program, a current flows between the drain 5 and the source 3.

This current is compared with a given reference current to generate a programming completion signal when it reaches a value less than or equal to the reference current.

This process is illustrated in Figure 1b.

This prior art can compensate for the shortcomings of the iterative technique of repeating programs and queries by automatically querying the program status at the same time as programming.

However, R. Ceernea's technique does not use a program gate for program operation separately, and does not use a structure in which a program is completely separated from a current path and a sensing (or inquiry) current path.

In particular, the threshold voltage level is not controlled by the voltage applied to the control gate of the memory cell.

Therefore, it is difficult to optimize the programming operation and the sensing operation separately.

In addition, since the programming and monitoring currents are not separated, it is difficult to directly control and adjust the threshold voltage level of the cell.

In addition, in the US patent (Registration No. 5,043,940), multilevel programming was performed by fixing a voltage applied to each terminal of a memory cell and changing reference currents corresponding to each level.

In this technique, as shown in FIG. 1B, the reference currents of the meter are generally hard to find an explicit relationship with the threshold voltages of the cell, and are not in a linear relationship.

Therefore, in the current controlled method as in the prior art, there is a disadvantage in that it is difficult to control the multilevel directly and effectively.

On the other hand, the cell structure of the EEPROM or flash EEPROM is divided into two types according to the floating gate position on the channel region.

The first is a simple stacked gate structure in which the floating gate is completely covered on the channel region of the cell. The second is a split-channel in which the floating gate covers only a part of the channel region between the source and the drain. Structure.

An area without a floating gate in the channel region is called a select transistor, and the select transistor and the floating gate transistor are connected in series to the same channel region to form a memory cell.

Such a channel-separated cell may also be classified into two types according to the formation method of the selection transistor.

The control gate electrode of the floating gate transistor and the gate electrode of the selection transistor have the same structure (called merged-split-gate-cell), and the gate-separated cell in which the control gate electrode and the gate electrode of the selection transistor are separated (called split-gate-cells).

The selection transistors have been introduced to prevent over-erasing problems and to facilitate the construction of contactless virtual ground arrays.

In particular, gate-separated cells have been introduced to facilitate the injection of hot electrons from the source side in addition to these purposes.

FIG. 2A is a circuit diagram illustrating a conventional nonvolatile memory cell having a simple stacked gate structure, and FIG. 2B is a circuit diagram illustrating a nonvolatile memory cell having a conventional channel-separated structure.

2a and 2b show the programming and erasing processes together with the structure of a conventional nonvolatile memory cell.

In FIG. 2A, reference numeral 6 denotes a control gate, 7 floating gate, 8 source, 9 drain, and 10 channel region.

In FIG. 2B, reference numeral 13 denotes a control gate, 14 floating gate, 15 source, 16 drain, 17 channel region, and 18 erase gate.

According to FIG. 2B, since the erase gate 18 is an unnecessary gate in the program operation, the conventional cells of FIGS. 2A and 2B become substantially the same as the double polygate structure in the programming operation.

As a result, all of the prior arts have been difficult to separate the program current path and the inquiry (or sensing) current path in the memory cell because programming is performed only by the electrodes of the control gate, the erase gate, the source, or the drain during the program operation.

Therefore, there is a disadvantage that it is difficult to control the multilevel directly and effectively.

The channel-separated nonvolatile memory cell uses a hot electron injection mechanism (programmed by hot electron injection mechanlsm).

In particular, the merged gate gate type cell uses injection of hot electrons from the drain side, and the split gate cell uses source side hot electron injection.

In addition, erase uses FN-Tunnelling as in other EEPROMs.

However, the above conventional nonvolatile memory device has the following problems.

First, in the floating gate memory without contact, the erase threshold voltage is generated from the process unevenness of the buried layer region when the erase is performed to the source side.

Second, band-to-band tunneling occurs in the semiconductor substrate due to a strong electric field, holes are injected into the tunneling oxide film, and traps are deteriorated.

Third, a complicated process and an additional polysilicon layer are needed to form an erase gate by employing poly-to-poly erase to avoid erasing to the source side.

The present invention has been made to solve the above problems and prevents deterioration of device characteristics due to hole injection into a tunneling oxide film by band-to-band tunneling that occurs during source-side erasing with poly-to-poly erasure. Another object of the present invention is to provide a method of manufacturing a nonvolatile memory device that does not require a separate process of forming an erase gate.

1A is a circuit diagram of a typical nonvolatile memory cell.

FIG. 1B is a graph for explaining the principle of auto inquiry programming of a nonvolatile memory according to FIG.

2A is a circuit diagram of a nonvolatile memory cell having a conventional simple stacked gate structure.

2B is a circuit diagram of a nonvolatile memory cell having a conventional channel-separated structure.

3A to 3H are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to the present invention.

4 is a circuit diagram showing a nonvolatile memory cell according to the present invention.

5 is a schematic circuit diagram of a nonvolatile memory device according to the present invention.

* Explanation of symbols for main parts of the drawings

21 semiconductor substrate 22 buffer oxide film

23: buried layer 24a, 24b: 1st, 2nd oxide film

25 first HLD layer 26 nitride film

27: second HLD layer 28: tunneling oxide film

29 floating gate 30 first interlayer insulating film

31a: erase gate 31b: control gate

32: third HLD layer 33: BPSG layer

34: word line 35: second interlayer insulating film

A method of manufacturing a nonvolatile memory device according to the present invention for achieving the above object is to form a buried layer having a predetermined interval in the surface of the semiconductor substrate, and to form a first insulating film on the surface of the semiconductor substrate in the buried layer region Depositing a first HLD layer, a nitride film, and a second HLD layer on the first insulating film, forming a tunneling oxide film on a surface of the semiconductor substrate, and interposing the tunneling oxide film through the tunneling oxide film. Forming a floating gate to overlap with the semiconductor substrate, selectively removing the second HLD layer to define an erase gate region, selectively removing the second HLD layer to define an erase gate region, and Depositing a second insulating film on the entire surface of the semiconductor substrate including the floating gate; Forming an erase gate in the control gate and the erase gate region above the floating gate, depositing a third insulating film and a fourth insulating film having contact holes to expose a predetermined portion of the surface of the control gate; and And forming a word line connected to the control gate through a contact hole.

Hereinafter, a method of manufacturing a nonvolatile memory device according to the present invention will be described in detail with reference to the accompanying drawings.

3A to 3H are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to the present invention.

As shown in FIG. 3A, a buffer oxide film 22 is formed on the semiconductor substrate 21, and the first photoresist PR 1 is coated on the buffer oxide film 22, followed by exposure and The first photoresist PR 1 is patterned by the developing process.

Subsequently, source / drain high concentration impurity ions are implanted into the entire surface of the semiconductor substrate 21 by using the patterned first photoresist PR 1 as a mask to fill the buried layer 23 in the surface of the semiconductor substrate 21. Form.

As shown in FIG. 3B, the first photoresist PR 1 and the buffer oxide film 22 are removed.

Next, the semiconductor substrate 21 is oxidized to form first and second oxide films 24a and 24b on the surface of the semiconductor substrate 21. In this case, the first oxide film 24a is formed on the surface of the semiconductor substrate 21 in the region of the buried layer 23 into which the impurity ions have been implanted to have a thickness of 1500 Å, and the second oxide film 24b is 100 in the region where the impurity ions are not implanted. It is formed to a thickness of ˜200 mm 3.

As shown in FIG. 3C, a first HLD layer 25 is deposited on the entire surface of the semiconductor substrate 21 including the first and second oxide films 24a and 24b at a thickness of 1000 to 2000 microseconds, and the first HLD is deposited. A nitride film 26 is deposited on the layer 25 to a thickness of 50 to 100 GPa, and a second HLD layer 27 is deposited on the nitride film 26 to about 1000 GPa.

The nitride layer 26 is deposited for the protection of the first HLD layer 25 when the second HLD layer 27 is wet etched in a later process.

Subsequently, after applying the second photoresist PR 2 on the second HLD layer 27, the second photoresist PR 2 is patterned by an exposure and development process.

The second HLD layer 27, the nitride layer 26, and the first HLD layer 25 are selectively removed using the patterned second photoresist PR 2 as a mask. At this time, a part of the second oxide film 24b is also etched at the same time.

As shown in FIG. 3D, the second photoresist PR 2 and the second oxide film 24b are removed, and the second substrate 24b is tunneled to the surface of the semiconductor substrate 21 from which the second oxide film 24b is removed. An oxide film 28 is formed, and a first polysilicon layer (not shown) is deposited on the entire surface of the semiconductor substrate 21 including the tunneling oxide film 29 to a thickness of 1000 to 2000 microseconds.

Subsequently, after applying the third photoresist PR 3 on the first polysilicon layer, the third photoresist PR 3 is patterned by an exposure and development process.

Using the patterned third photoresist PR 3 as a mask, the first polysilicon layer is selectively removed to expose a portion of the surface of the second HLD layer 27 to form a floating gate 29. ).

In this case, when the floating gate 29 is formed, all of the first polysilicon layers in the Peri region are removed.

As shown in FIG. 3E, the third photoresist PR 3 is removed and the second HLD layer 27 is selectively removed.

In this case, the second HLD layer 27 selectively removes only a region where an erase gate is to be formed in a subsequent process by wet etching.

Subsequently, a first interlayer insulating film 30 is deposited on the entire surface of the semiconductor substrate 21 including the floating gate 29 to a thickness of 200 to 300 Å.

Here, the first interlayer insulating film 30 is an insulating film of a laminated structure composed of a silicon oxide film / nitride film or a silicon oxide film / nitride film / silicon oxide film.

As shown in FIG. 3F, a second polysilicon layer 31 is deposited on the first interlayer insulating layer 30, and a fourth photoresist PR 4 is deposited on the second polysilicon layer 31. After coating, the fourth photoresist PR 4 is patterned by an exposure and development process.

As shown in FIG. 3G, the second polysilicon layer 31 is selectively removed using the patterned fourth photoresist PR 4 as a mask to remove the erase gate 31a and the control gate 31b. Form.

In this case, a gate electrode is formed in the ferry region.

Although not shown in the drawing, a source and a drain region having an LDD (Lightly Doped Drain) structure are formed in the ferry region.

Subsequently, the fourth photoresist PR 4 is removed, and a third HLD layer 32 is formed on the entire surface of the semiconductor substrate 21 including the erase gate 31a and the control gate 31b at a thickness of 1000 to 2000 microseconds. Deposit.

Subsequently, a BPSG layer 33 is deposited on the third HLD layer 32 to have a thickness of about 5000 GPa for interlayer insulation and planarization, and annealing is performed on the BPSG layer 33 to planarize.

As shown in FIG. 3h, the third HLD layer 32 and the BPSG layer 33 are selectively removed to form a contact hole so that the surface of the control gate 31b is partially exposed, and the contact hole is included. A metal layer for word lines (not shown) is deposited on the entire surface of the semiconductor substrate 21.

Subsequently, the metal layer is selectively removed to form a word line 34 connected to the control gate 31b.

In this case, since the buried layer is used as the source and drain regions to increase the cell size due to the contact formation, the control gate 31b may be formed to have a margin on the first oxide layer 24a, thereby increasing the cell size according to the contact formation. Can be prevented.

The second interlayer insulating layer 35 is deposited on the entire surface of the semiconductor substrate 21 including the word line 34.

4 is a circuit diagram showing a nonvolatile memory cell according to the present invention.

As shown in FIG. 4, a floating gate 41 storing charge carriers during programming and charge carriers provided from the outside during programming are injected into the floating gate 41 to perform erasure or program. An erase gate 42, a control gate 43 that controls the amount of charge carriers provided from the erase gate 42 to the floating gate 41 during programming, and the floating gate 41, a channel region. And a transistor (TR) for querying the amount of charge carriers provided from the erase gate (42) during programming.

The operation of the nonvolatile memory cell according to the present invention configured as described above is as follows.

First, the erase operation is to inject electrons into the floating gate 41 in the case of an N-type transistor. Therefore, the erase operation can be performed by tunneling from the channel region 44 or the drain 46 region, or by hot electron injection from the source 45 side.

When the hot carrier injection method is used during the erasing operation, the thickness of the gate dielectric positioned between the channel region 44 or the drain 46 and the floating gate 41 does not need to be thin enough for tunneling. The process and reliability of the gate dielectric is much easier, and the coupling ratio is much improved compared to that of the existing tunneling gate dielectric, thereby enabling low voltage and high speed operation.

These problems can solve the problems of most conventional nonvolatile memory cells, and in particular, low field leakage current of the gate oxide layer for tunneling occurring when the non-volatile memory cell size is scaled down. Problems such as leakage and degradation can be avoided. Therefore, the nonvolatile memory cell of the present invention can be easily reduced in this respect.

5 is a schematic circuit diagram of a nonvolatile memory device according to the present invention.

As shown in FIG. 5, the nonvolatile memory device includes a plurality of control gate (word) lines 51 disposed on a semiconductor substrate (not shown) at a predetermined distance from each other, and a plurality of non-volatile memory elements at a predetermined distance from each other. A bit line 52 made up of a plurality of buried layers orthogonal to each control gate line 51 so as to form four squares, and a plurality of erase gates arranged in the same direction as each bit line 52. It consists of a line 53 and a plurality of nonvolatile memory cells arranged one in each square.

As shown in FIG. 4, the nonvolatile memory cell includes a floating gate 41, an erase gate 42, a control gate 43, and a field effect transistor TR.

The field effect transistor TR includes a floating gate 41, a source 45 and a drain 46, and a channel region 44 positioned between the drain 46 and the source 35.

The control gate 43 of each nonvolatile memory cell is connected to an adjacent control gate line 51, and the erase gate 42 is connected to an adjacent erase gate line 53.

In addition, the source 45 of the nonvolatile memory cell in one square is jointly connected to the bit line 52 adjacent together with the drain 46 of the nonvolatile memory cell located in the square.

As described above, the manufacturing method of the nonvolatile memory device according to the present invention has the following effects.

First, it is possible to prevent deterioration of device characteristics due to hole injection into the tunneling oxide film due to band-to-band tunneling generated at the source side erasure with poly-to-poly erasure.

Second, when the control gate is formed, the erase gate is simultaneously defined to simplify the manufacturing process.

Third, since the word line is formed of a metal layer, the time for accessing the cell is short, thereby improving the speed of the device.

Claims (4)

Forming a buried layer at regular intervals in the surface of the semiconductor substrate; Forming a first insulating film on a surface of the semiconductor substrate in the buried layer region; Sequentially depositing a first HLD layer, a nitride film, and a second HLD layer on the first insulating film; Forming a tunneling oxide film on a surface of the semiconductor substrate; Forming a floating gate to overlap with the insulating layer through the tunneling oxide layer; Selectively removing the second HLD layer to define an erase gate region; Depositing a second insulating film on the entire surface of the semiconductor substrate including the floating gate; Forming an erase gate in the control gate and the erase gate region above the floating gate with the second insulating layer interposed therebetween; Depositing a third insulating film and a fourth insulating film having contact holes to expose a predetermined portion of the surface of the control gate; And forming a word line connected to the control gate through the contact hole. The method of claim 1, And the nitride film is selectively removed by wet etching to form an erase gate region to protect the first HLD layer, wherein the nitride layer is deposited to protect the first HLD layer. The method of claim 1, And the control gate and the erase gate are formed at the same time. The method of claim 1, And the second insulating film is a laminated insulating film composed of a silicon oxide film / nitride film or a silicon oxide film / nitride film / silicon oxide film.

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