JP2000252448A - Non-volatile semiconductor storage device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor storage device using a trench type element separation wherein the word line interval sandwiching a source line is minimized to cause no such problem as the resistance rise of the source line. SOLUTION: Trench element separation region 16 is so formed as to define an active region on a semiconductor substrate 2, and a drain diffusion layer is so formed as to be sandwiched between the trench element separation regions 16. A charge accumulation layer 20 for capacity coupling to the active region is formed on the active region through a first gate insulating film 18, a control gate 24 for capacity coupling to the charge accumulation layer 20 is formed on the charge accumulation layer 20 through a second gate insulating film 22, and a source diffusion layer 8 is formed on the opposite side of the drain diffusion layer to the control gate 24. The edge on a source diffusion layer 8 side of the trench element separation region 16 almost agrees with that of the charge accumulation layer 20 and control gate 24, with the source diffusion layer 8 formed flat without bending in the semiconductor substrate 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly to a stacked gate type flash EEPROM using a trench type element isolation and a method of manufacturing the same. is there.

[0002]

2. Description of the Related Art Three conventional examples of a stacked gate type nonvolatile semiconductor memory device using a trench type element isolation will be described below.

FIG. 26A is a plan view showing the structure of a nonvolatile semiconductor memory device using a trench type element isolation according to a first conventional example. FIGS. 26B to 26D are cross-sectional views showing the structure of this nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device shown in these figures is a NOR flash EEPROM.

[0004] As shown in FIGS.
On a conductive type semiconductor substrate 102, a trench element isolation region 104 is formed. This trench element isolation region 1
A floating gate 108 is formed on a part of the semiconductor substrate 102 except on the semiconductor substrate 104 via a tunnel oxide film 106. Further, the floating gate 10
On 8, a control gate 112 is formed via an interpoly insulating film 110. Such a structure is hereinafter referred to as a stacked gate structure.

As shown in FIG. 26C, the floating gate 108 is divided into individual cells, and the control gate 112 is formed continuously between adjacent cells to form a word line. As shown in FIG. 26D, in the semiconductor substrate 102 having the stacked gate structure, the semiconductor substrate 102 is self-aligned with a conductive type (second conductive type).
(Conductive type) source diffusion layer 114 and drain diffusion layer 116
Are formed. The source diffusion layer 114 is formed as shown in FIG.
As shown in the plan view of (a), the cells are also connected between adjacent cells to form a source line.

[0006] An interlayer insulating film 118 is formed on the entire surface of the semiconductor substrate 102, and a contact hole 120 is formed on the drain diffusion layer 116 so as to penetrate the interlayer insulating film 118. Further, a bit line 122 connected to the contact hole 120 is formed on the contact hole 120, and an insulating film 124 is formed on the bit line 122 and the interlayer insulating film 118.

Next, the operation of the first conventional nonvolatile semiconductor memory device will be described.

In writing, the source line 114 and the semiconductor substrate 102 are set to 0 [V], and a high voltage, for example, 5 V is applied to the drain diffusion layer 116 of the memory cell to be written.
[V] is applied. Furthermore, a high voltage, for example, 10 V, is applied to the control gate 112 with 0 [V] applied to the drain diffusion layer 116 of the memory cell for which writing is prohibited.
[V] is applied. Then, so-called hot carriers are generated in the vicinity of the drain diffusion layer 116 of the memory cell in which writing is performed, and writing is performed by electrons reaching the floating gate 108 and accumulated therein. At this time, the threshold voltage Vth at the time of writing in the memory cell having the stacked gate structure becomes a positive high voltage, for example, 5 [V].

In erasing, the control gate 11
2 is applied with 0 [V], and a high voltage, for example, 12 [V] is applied to the source line 114. Then, the electrons accumulated in the floating gate 108 cause a tunnel phenomenon (Fowler-No.
rdheim) to the source line 114,
Erasure is performed. At this time, the threshold voltage Vt at the time of erasing is
h is a positive low value, for example, 2 [V].

In reading, a positive voltage, for example, 4 [V] is applied to the control gate 112, and a voltage of 3 [V] is applied to the drain diffusion layer 116. Then, in the write cell, no current flows because the threshold voltage Vth is higher than the applied voltage, and in the erase cell, the threshold voltage Vth
Is lower than the applied voltage, a current flows. Thereby, the information stored in the memory cell is determined.

Next, a nonvolatile semiconductor memory device using a trench type element isolation according to a second conventional example will be described.

FIG. 27A is a plan view showing a structure of a nonvolatile semiconductor memory device using a trench type element isolation according to a second conventional example. FIGS. 27B to 27D are cross-sectional views showing the structure of this nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device shown in these figures is a NOR flash EEPROM.

On a semiconductor substrate 102 of the first conductivity type, a trench element isolation region 104 is formed in a long groove shape.
Source diffusion layers 114 of adjacent memory cells are separated by trench element isolation regions 104. Since the source diffusion layer 114 does not operate in this state, the contact hole 1
They are connected to each other via a source wiring 132 via the reference numeral 30. The operation is the same as that of the first conventional example, and the description is omitted.

Next, a description will be given of a third conventional nonvolatile semiconductor memory device using trench type element isolation.

FIG. 28A is a plan view showing the structure of a nonvolatile semiconductor memory device using a trench type element isolation according to a third conventional example. FIGS. 28B to 28E are cross-sectional views showing the structure of this nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device shown in these figures is a NOR flash EEPROM.

As shown in FIGS. 28A to 28E, the first
On a conductive type semiconductor substrate 102, a trench element isolation region 104 is formed. The element regions of the adjacent memory cells are initially separated by the insulating film of the trench element isolation region 104 formed in a long groove shape. As shown in FIG. 28E, the part of the insulating film in the region where the source line is to be formed is removed by etching away the part of the insulating film, and the source diffusion layer 114 is formed on both the top and bottom of the trench. It is formed.

At this time, the source diffusion layers 114 on the bottom and upper portions of the trench are connected to the source diffusion layers 114 on the side walls of the trench.
Although the connection is made by A, when the source diffusion layer 114 is formed by ion implantation, almost no impurities are implanted into the side walls. Therefore, the source diffusion layer 114A on the side wall has low resistance and high resistance. The operation is the same as in the first and second conventional examples, and the description is omitted.

[0018]

In the above-described nonvolatile semiconductor memory device of the first conventional example, as shown in FIG. 26A, the control gate 112 and the trench element isolation film 104 are combined by a lithography process. A margin is required to cope with the deviation. Even if the width of the source diffusion layer 114 is 0.25 [μm], about 0.1 [μm] is required on both sides, so that the distance between the control gates 112 sandwiching the source diffusion layer 114 is 0.45 [μm]. This leads to an increase in cell size.

Further, in the above-mentioned nonvolatile semiconductor memory device of the second conventional example, similarly, as shown in FIG. 27, contact hole 130 connected to source diffusion layer 114 prevents short-circuit with a stacked gate. Therefore, a margin is required for the adjustment. Since this alignment margin also needs to be about 0.1 μm on both sides, the interval between the control gates 112 across the source diffusion layer 114 is 0.45 μm. This leads to an increase in cell size.

In the above-described nonvolatile semiconductor memory device of the third conventional example, since the source diffusion layer 114 is formed in a self-aligned manner with respect to the control gate 112, the distance between the control gates 112 is 0.25 [ μm]. However, the source diffusion layer 114A formed on the side wall of the trench is hardly doped, and thus has a high resistance. If the dose of ion implantation is increased in order to increase the concentration of the source diffusion layer 114A in the side wall portion, the dose of the source diffusion layer 114 in the planar portion (upper and bottom surfaces of the trench) becomes too large. In these cases, crystal defects and defects in cell operation occur.

That is, in the nonvolatile semiconductor memory device using the trench type element isolation, as described above, if the source line is not formed in a self-aligned manner with the word line, a margin for alignment is required, so that the source line is sandwiched. Word line spacing cannot be reduced to the minimum size. On the other hand, when the source lines are formed in a self-aligned manner using the word lines, the word line interval can be minimized.
A problem occurs that the resistance value of the source line increases.

In view of the above, the present invention has been made in view of the above-mentioned problem, and in a nonvolatile semiconductor memory device using trench-type element isolation, a word line interval between source lines can be minimized. It is another object of the present invention to provide a nonvolatile semiconductor memory device which does not cause a problem such as an increase in resistance of a source line.

[0023]

To achieve the above object, a nonvolatile semiconductor memory device according to the present invention comprises a plurality of trench element isolation regions formed to define an active region in a semiconductor substrate; A drain region formed in the active region so as to be sandwiched between the trench element isolation regions and having a conductivity type opposite to the conductivity type of the semiconductor substrate; and a charge storage formed on the active region so as to be capacitively coupled to the active region. A layer, a control gate formed on the charge storage layer to be capacitively coupled to the charge storage layer, and a control gate formed on the opposite side of the drain region with respect to the control gate, in parallel with the control gate, A source region of a conductivity type and a reverse conductivity type of the semiconductor substrate, and an edge of the trench element isolation region facing the source region is substantially equal to an edge of a lower surface of the charge storage layer. It has, wherein the source region is formed in a substantially planar in said semiconductor substrate.

Further, according to the present invention, there is provided a nonvolatile semiconductor memory device, comprising: a plurality of trench isolation regions formed so as to define an active region in a semiconductor substrate; and the active region sandwiched by the trench isolation regions. A drain region of a conductivity type opposite to the conductivity type of the semiconductor substrate, a first select gate transistor formed adjacent to the drain region, and a capacitive coupling with the active region on the active region. A charge storage layer formed on the charge storage layer, a control gate formed on the charge storage layer so as to be capacitively coupled to the charge storage layer, and a memory cell having the charge storage layer and the control gate. A second select gate transistor formed on the opposite side of the first select gate transistor with respect to the memory cell so as to sandwich the memory cell; Is formed so as to adjacent to the second select gate transistor in parallel to the control gate, comprising a said conductive semiconductor substrate and the opposite conductivity type of the source region,
An edge of the trench element isolation region facing the source region substantially coincides with an edge of a lower surface of the gate of the second select gate transistor, and the source region is formed substantially planar in the semiconductor substrate. It is characterized by having been done.

Further, according to a method of manufacturing a nonvolatile semiconductor memory device according to the present invention, there is provided a step of forming a first mask material on a semiconductor substrate, and an ion implantation method using the first mask material as a mask. A step of forming a source diffusion layer in a linear shape in a substrate, a step of forming a first insulating film in self-alignment with the source diffusion layer, and forming a second mask material so as to cover an element formation region Forming a trench by etching the first mask material and the semiconductor substrate by etching using the first insulating film and the second mask material as a mask; and forming a second trench in the trench.
Forming a trench element isolation region by burying the insulating film, forming a groove by removing the first mask material left in the element formation region, and exposing a surface of the semiconductor substrate in the groove. Forming a first gate insulating film, forming a first conductive film on the first gate insulating film, forming a third insulating film on the first conductive film, and forming a second conductive film on the first conductive film. Forming a conductive film, patterning the second conductive film, the third insulating film, and the first conductive film to form a charge storage layer, a second gate insulating film, and a control gate; It is characterized by having.

Further, in the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, a step of forming a plurality of first mask members in a line on a semiconductor substrate; A step of introducing an impurity into the substrate to form an impurity introduction region of a conductivity type opposite to that of the semiconductor substrate; and forming a second mask material over the entire surface of the semiconductor substrate, and forming a desired mask between the first mask material. Selectively leaving a second mask material in a region, forming a third mask material in a linear shape substantially orthogonal to the first mask material, and forming a second mask material and a third mask material. Using the first mask material as a mask,
Forming a trench by removing the mask material and the semiconductor substrate to a position deeper than the impurity introduction region, and forming an element isolation region by burying an insulating film in the trench after removing the third mask material. Removing the first mask material left under the third mask material to expose the surface of the semiconductor substrate; and forming a first gate insulating film on the surface of the semiconductor substrate. Forming, forming a first conductive film on the first gate insulating film, and linearly patterning the first conductive film so as to be substantially orthogonal to the second mask material. Forming a second gate insulating film on the first conductive film; forming a second conductive film on the second gate insulating film;
Forming a plurality of fourth mask members in a linear shape on the second conductive film so as to sandwich the second mask members at substantially the same interval as the width of the second mask members; And sequentially etching the second conductive film, the second gate insulating film, and the first conductive film using the fourth mask material as a mask.

Further, in the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, a step of forming a first mask material in a portion where a word line is to be formed on a semiconductor substrate of a first conductivity type; By ion implantation using a mask material as a mask,
Forming a source diffusion layer and a drain diffusion layer of a second conductivity type opposite to the first conductivity type in the semiconductor substrate, and an entire surface of the semiconductor substrate including on the first mask material; Depositing a first insulating film on the substrate, isotropically etching the first insulating film to selectively leave the first insulating film on the source diffusion layer, and covering an element formation region. Forming a second mask material, and sequentially etching the first mask material and the semiconductor substrate by etching using the first insulating film and the second mask material as a mask. Depositing a filling material over the entire surface of the semiconductor substrate after removing the second mask material; and removing the filling material above the upper surface of the first insulating film to form a trench isolation region. And the second step The left below the mask material first
Forming a groove by removing the mask material, forming a first gate insulating film on the exposed surface of the semiconductor substrate in the groove, and forming the first gate insulating film in the groove. Depositing a first conductive film on the entire surface of the semiconductor substrate including the film, selectively etching the first conductive film to form a slit between memory cells adjacent in a word line direction; Forming a second insulating film and a second conductive film sequentially on the entire surface of the semiconductor substrate including on the first conductive film; and forming the second conductive film, the second insulating film, and the first conductive film on the first conductive film. Selectively etching the conductive film sequentially to form a control gate, a second gate insulating film, and a charge storage layer, each of which is a word line.

Further, in the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, a step of forming a first gate insulating film on a semiconductor substrate, and a step of forming a first conductive film on the first gate insulating film Forming a pattern, linearly forming a source diffusion layer in the semiconductor substrate by ion implantation using the first conductive film as a mask, and forming a first insulating layer in a self-aligned manner with the source diffusion layer. Forming a film, forming a first mask material so as to cover the element formation region,
Forming a trench by etching the first conductive film and the semiconductor substrate by etching using the first insulating film and the first mask material as a mask; and forming a second insulating film in the trench. Forming a buried trench element isolation region, forming a second conductive film on the surface of the first conductive film, and forming a third insulating film and a third conductive film on the second conductive film And a step of patterning the third conductive film, the third insulating film, and the second conductive film to form a control gate, a second gate insulating film, and a charge storage layer. It is characterized by doing.

Further, in the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, a step of forming a first gate insulating film on a semiconductor substrate, and a step of forming a first conductive film on the first gate insulating film. A step of forming a plurality of lines in a line, a step of introducing an impurity into the semiconductor substrate using the first conductive film as a mask, and forming an impurity introduction region of a conductivity type opposite to that of the semiconductor substrate; Forming a first mask material, and selectively forming a first mask material in a desired region between the first conductive films.
Leaving a mask material, forming a second mask material in a line so as to be substantially orthogonal to the first mask material, and using the first mask material and the second mask material as masks. ,
Removing the first conductive film, the first gate insulating film, and the semiconductor substrate to a position deeper than the impurity introduction region to form a trench; and, after removing the second mask material, Forming an element isolation region by burying an insulating film in the trench, and forming a second conductive film on the entire surface of the semiconductor substrate including the portion of the first conductive film left below the second mask material A step of linearly patterning the second conductive film so as to be substantially orthogonal to the first mask material, and a step of forming a second gate insulating film on the second conductive film. Forming a third conductive film on the second gate insulating film; and forming the first mask on the third conductive film at substantially the same interval as the width of the first mask material. Forming a plurality of third mask members in a line so as to sandwich the members , Characterized by comprising the said third mask material as a mask the third conductive film, a second gate insulating film, the step of sequentially etching the second conductive film.

Further, in the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, the first conductive film is formed on the portion of the semiconductor substrate of the first conductivity type where the word line is to be formed via the first gate insulating film. Forming a source diffusion layer and a drain diffusion layer of a second conductivity type of a conductivity type opposite to the first conductivity type in the semiconductor substrate by an ion implantation method using the first conductive film as a mask. Forming a first insulating film on the entire surface of the semiconductor substrate including on the first conductive film; and forming the first insulating film on the source diffusion layer by isotropically etching the first insulating film. Selectively leaving the first insulating film, forming a first mask material so as to cover an element formation region, and forming the first conductive film and the semiconductor substrate in the first conductive film. Etching using insulating film and first mask material as mask A step of sequentially etched by,
Depositing a filling material over the entire surface of the semiconductor substrate after removing the first mask material, and removing the filling material above an upper surface of the first insulating film to form a trench isolation region; And depositing a second conductive film on the entire surface of the semiconductor substrate including the first conductive film left under the first mask material, and selectively etching the second conductive film. Forming a slit between memory cells adjacent to each other in the word line direction, and sequentially forming a second insulating film and a third conductive film on the entire surface of the semiconductor substrate including on the second conductive film. And selectively etching the third conductive film, the second insulating film, and the second conductive film sequentially to form a control gate, a second gate insulating film, and a charge storage layer, which are word lines, respectively. And forming.

[0031]

Embodiments of the present invention will be described below with reference to the drawings.

First, the structure of the nonvolatile semiconductor memory device according to the first embodiment of the present invention will be described.

FIG. 1A is a plan view of the nonvolatile semiconductor memory device according to the first embodiment, and FIG. 1B is a sectional view taken along line 1b-1b in the plan view. (C) is a sectional view taken along line 1c-1c in the plan view. This nonvolatile semiconductor memory device is a NOR flash memory.

As shown in FIG. 1C, a trench element isolation region 16 is formed in the semiconductor substrate 2 so as to define an element region (active region). Tunnel oxide film 18 is formed on semiconductor substrate 2 between trench element isolation regions 16, and floating gate 20 serving as a charge storage layer is formed on tunnel oxide film 18.

Further, an interpoly insulating film 22 is formed on the floating gate 20, and a control gate 24 is formed on the interpoly insulating film 22. Semiconductor substrate 2 including control gate 24
An insulating film 26 is formed on the entire surface of the substrate, and a bit line wiring 30 is formed on the insulating film 26. Further, an insulating film 32 is formed on the insulating film 26 including the bit line wiring 30. Further, the insulating film 26 is provided with a bit line contact 28 indicated by a broken line formed by partially opening the conductive film and burying the conductive film. The bit line contact 28 connects the bit line wiring 30 to a drain diffusion layer (not shown).

As shown in FIG. 1B, a source diffusion layer 8 is formed in the semiconductor substrate 2 so as to be parallel to the control gate 24. On the source diffusion layer 8, a silicon oxide film 4 is formed. Silicon oxide films 12 are sequentially formed. An interpoly insulating film 22 is formed on the trench element isolation region 16, and a control gate 24 is formed on the interpoly insulating film 22.

Further, as described above, the insulating film 26 is formed on the entire surface of the semiconductor substrate 2 including the control gate 24, and the insulating film 32 is formed on the insulating film 26. Further, the insulating film 26 is provided with a bit line contact indicated by a broken line formed by partially opening the hole and embedding a conductive film.

Here, as shown in FIG. 1B, one end of the edge of the control gate 24 is formed so as to substantially coincide with one end of the edge of the trench isolation region 16. In other words, in the floating gate below the control gate 24, the edge of the lower surface on the source diffusion layer 8 side is the edge of the trench isolation region 16,
They are formed so as to coincide with each other so that there is no problem in the operation function. Thus, the distance between the control gates 24 across the source diffusion layer 8 is the smallest possible dimension. The source diffusion layer 8 is formed in the semiconductor substrate 2 in a planar shape, and the surface position of the source diffusion layer 8 is equal to the original surface position of the semiconductor substrate 2 before the film is deposited. I do. As described above, the nonvolatile semiconductor memory device according to the first embodiment is formed.

Next, a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment will be described.

FIGS. 2 to 12 are a plan view and a cross-sectional view of each step showing the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment.

FIGS. 2A to 12A are plan views of this nonvolatile semiconductor memory device, and FIGS. 2B and 12C are cut along the respective cutting lines in the plan views. FIG.

As shown in FIG. 2, an insulating film, for example, a silicon oxide film 4 is formed on the entire surface of the semiconductor substrate 2 of the first conductivity type. For example, a silicon nitride film 6 is formed as a mask material on a portion where the word line is to be formed on the silicon oxide film 4. Further, a source diffusion layer 8 and a drain diffusion layer 10 are formed in the semiconductor substrate 2 by using an ion implantation method or the like.

Further, as shown in FIG.
A silicon oxide film 12 serving as a mask material is formed on the entire surface of the substrate. At this time, the thickness of the silicon oxide film 12 is the same as that of the two silicon nitride films 6 formed so as to sandwich the source diffusion layer 8.
Of the interval between the two silicon nitride films 6 formed so as to sandwich the drain diffusion layer 10.
Make it thinner than 2. Subsequently, as shown in FIG. 4, the silicon oxide film 1 is isotropically etched.
2 is etched to leave a silicon oxide film 12 as a mask material only on the source diffusion layer 8.

The definition of the thickness between the silicon oxide film 12 and the silicon nitride film 6 is adopted as a means for selectively leaving the silicon oxide film 12 only on the source diffusion layer 8. It may not be applied when the mask material of the drain region is removed in the buried lithography process.

Next, as shown in FIG. 5, a mask material or a photoresist 14 is formed so as to cover the element formation region. Further, the exposed silicon nitride film 6, the silicon oxide film 4, and the semiconductor substrate 2, which are the mask material, are sequentially etched under the etching condition in which the silicon oxide film 12, which is the mask material, is not etched to form the structure shown in FIG. I do. At this time, since the region where the source diffusion layer 8 is formed is protected by the silicon oxide film 12, the region is not etched.

Subsequently, as shown in FIG. 7, the photoresist 14 is removed, and a trench filling material 16a is deposited on the entire surface of the semiconductor substrate 2. Furthermore, by the CMP method, etc.
As shown in FIG. 8, the trench filling material 16a above the upper surface of the silicon oxide film 12 is removed to form a trench isolation region 16.

After that, the silicon nitride film 6 and the silicon oxide film 4 as the mask material are removed, and a tunnel oxide film 18 is formed on the exposed surface of the semiconductor substrate 2 as shown in FIG. Further, as shown in FIG. 10, a floating gate electrode material, for example, a polysilicon film 20a is deposited,
A slit is formed between adjacent cells.

Subsequently, as shown in FIG. 11, an interpoly insulating film 22 is formed on the entire surface of the semiconductor substrate 2. Further, the control gate 2 is formed on the interpoly insulating film 22.
4. For example, a polysilicon film or a refractory metal silicide film is formed. Then, as shown in FIG. 12, the control gate 24, the interpoly insulating film 22, and the floating gate 20 are selectively etched sequentially.

Thereafter, necessary post-oxidation is performed, and an insulating film 26 is deposited on the entire surface of the semiconductor substrate 2 including the control gate 24, as shown in FIG. The insulating film 26 is opened and a conductive film is buried to form a bit line contact 28. Further, a conductive film is formed on the entire surface of the semiconductor substrate 2,
By patterning, the bit line wiring 30 connected to the bit line contact 28 is formed. Further, bit line wiring 3
An insulating film 32 is formed on a semiconductor substrate including zero. As described above, the nonvolatile semiconductor memory device according to the first embodiment is manufactured.

Next, the operation of the nonvolatile semiconductor memory device according to the first embodiment will be described.

In writing, the source line 8 and the semiconductor substrate 2 are set to 0 [V], and a high voltage, for example, 10 [V] is applied to the drain 10 of the memory cell to be written.
Then, so-called hot carriers are generated in the vicinity of the drain 10 of the memory cell to be written. Of these, electrons reach the floating gate 20 and are accumulated, so that writing is performed. At this time, the write threshold voltage Vth of the stacked gate cell becomes a high positive value, for example, 5 [V].

In erasing, the control gate 24
Is applied to the source line 8 and a high voltage, for example,
[V] is applied. Then, the floating gate 20
The electrons accumulated in the tunnel are tunneling (Fowler-Nordheim)
As a result, erasing is performed by passing through the source line 8. At this time, the threshold voltage Vth for erasing has a low positive value, for example, 2 [V].

In reading, a positive voltage, for example, 4 [V] is applied to the control gate 24, and a voltage of 3 [V] is applied to the drain 10. Then, in the write cell, the current does not flow because the threshold voltage Vth is higher than the applied voltage, and in the erase cell, the current flows because the threshold voltage Vth is lower than the applied voltage. Thereby, the information stored in the memory cell can be determined.

In this nonvolatile semiconductor memory device,
The dimension between the word lines (control gates 24) sandwiching the source line (source diffusion layer 8) is the same as the word line width;
That is, the minimum possible size can be achieved. As described above, since it is not necessary to provide a margin for comparison as compared with the above-described first and second conventional nonvolatile semiconductor memory devices, it is possible to reduce the size of the memory cell in the nonvolatile semiconductor memory device. it can. The source diffusion layer is formed before the trench etching, and is covered with a protective film during the trench etching so as not to be etched. Therefore, the source line can be formed from a diffusion layer that maintains a planar structure without bending. Therefore, unlike the third conventional nonvolatile semiconductor memory device described above, the problem that the impurity concentration is different between the side wall portion and the plane portion of the trench in the source diffusion layer does not occur.

As described above, according to the nonvolatile semiconductor memory device of the first embodiment, even when trench type element isolation is used, the word line interval between the sources can be minimized, and the source line can be formed. This can prevent problems such as an increase in resistance from occurring. This allows
The area of the memory cell can be reduced.

Next, the structure of the nonvolatile semiconductor memory device according to the second embodiment of the present invention will be described.

FIG. 13A is a plan view of the nonvolatile semiconductor memory device according to the second embodiment, and FIG. 13B is a sectional view taken along line 13b-13b in the plan view.
(C) is a sectional view taken along line 13c-13c in the plan view. This nonvolatile semiconductor memory device is a NOR flash memory.

As shown in FIG. 13C, the semiconductor substrate 4
2, a trench element isolation region 56 is formed so as to define an element region (active region). Tunnel oxide film 44 is formed on semiconductor substrate 42 between trench element isolation regions 56, and floating gates 46 and 58 are formed on tunnel oxide film 44.

Further, the floating gates 46 and 58
An interpoly insulating film 60 is formed thereon, and a control gate 62 is formed on the interpoly insulating film 60. An insulating film 64 is formed on the entire surface of the semiconductor substrate 42 including the control gate 62.
4, a bit line wiring 68 is formed. Further, an insulating film 70 is formed on the insulating film 64 including the bit line wiring 68. Further, the insulating film 64 is provided with a bit line contact 66 indicated by a broken line formed by partially opening the conductive film and burying the conductive film. The bit line contact 66 connects the bit line wiring 68 to a drain diffusion layer (not shown).

As shown in FIG. 13B, a source diffusion layer 48 is formed in the semiconductor substrate 42 so as to be parallel to the control gate 62.
A tunnel oxide film 44 and a silicon oxide film 52 are sequentially formed thereon. An interpoly insulating film 60 is formed on the trench isolation region 56, and a control gate 62 is formed on the interpoly insulating film 60.

Further, as described above, the insulating film 64 is formed on the entire surface of the semiconductor substrate 42 including the control gate 62, and the insulating film 70 is formed on the insulating film 64. Further, the insulating film 64 is provided with a bit line contact indicated by a broken line formed by partially opening the conductive film and burying the conductive film.

Here, as shown in FIG. 13B, one end of the edge of the control gate 62 is formed so as to substantially coincide with one end of the edge of the trench isolation region 56. In other words, the control gate 62
The lower floating gate is formed such that the edge of the lower surface on the side of the source diffusion layer 48 coincides with the edge of the trench isolation region 56 to such an extent that there is no problem in the operation function. Thus, the distance between the control gates 62 across the source diffusion layer 48 is the smallest possible dimension. Further, the source diffusion layer 48 is formed in the semiconductor substrate 42 in a planar shape, and the surface position of the source diffusion layer 48 matches the original surface position of the semiconductor substrate 42 before the film is deposited. I have. As described above, the nonvolatile semiconductor memory device according to the second embodiment is formed.

Next, a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment will be described.

FIGS. 14 to 24 are plan views and cross-sectional views of respective steps showing a method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment.

FIGS. 14A to 24A are plan views of this nonvolatile semiconductor memory device, and FIGS. 14B to 24C are views taken along respective cutting lines in the plan views. FIG.

As shown in FIG. 14, a tunnel oxide film 44 is formed on the entire surface of the semiconductor substrate 42 of the first conductivity type. A floating gate material, for example, a polysilicon film is deposited on the entire surface of the tunnel oxide film 44, and is patterned to form a polysilicon film 46a at a portion where a word line is to be formed. Further, a source diffusion layer 48 and a drain diffusion layer 50 are formed in the semiconductor substrate 42 by using an ion implantation method or the like.

Subsequently, as shown in FIG. 15, a silicon oxide film 52 serving as a mask material is formed on the entire surface of the semiconductor substrate 42. At this time, the thickness of the silicon oxide film 52 is larger than 1/2 of the interval between the two polysilicon films 46a formed so as to sandwich the source diffusion layer 48, and the drain diffusion layer 5
0, two polysilicon films 46a formed so as to sandwich
Is set to be thinner than 1/2 of the interval. Further, as shown in FIG. 16, the silicon oxide film 52 is etched using isotropic etching to leave the silicon oxide film 52 as a mask material only on the source diffusion layer 48.

The above-mentioned definition of the thickness between the silicon oxide film 52 and the polysilicon film 46a is adopted as means for selectively leaving the silicon oxide film 52 only on the source diffusion layer 48. It may not be applied when the mask material of the drain region is removed in the buried lithography process.

Next, as shown in FIG. 17, a mask material or a photoresist 54 is formed so as to cover the element formation region.
To form Further, the polysilicon film 46a, which is an exposed mask material, the tunnel oxide film 44, and the semiconductor substrate 42
Are sequentially etched under the etching conditions in which the silicon oxide film 52 is not etched to form the structure shown in FIG. At this time, since the region where the source diffusion layer 48 is formed is protected by the silicon oxide film 52, no trench etching is performed.

Subsequently, as shown in FIG. 19, the photoresist 54 is removed, and a trench filling material 56a is deposited on the entire surface of the semiconductor substrate 42. Further, as shown in FIG. 20, the trench filling material 56a above the upper surface of the silicon oxide film 52 is removed by a CMP method or the like to form a trench element isolation region 56.

Next, a conductive material to be a part of the floating gate, for example, a polysilicon film 58a is deposited to form a structure shown in FIG. Subsequently, as shown in FIG. 22, the polysilicon film 58a is patterned to form slits between adjacent cells.

Further, as shown in FIG. 23, an interpoly insulating film 60 is formed on the entire surface of the semiconductor substrate 42. Further, the control gate 6 is formed on the interpoly insulating film 60.
2. For example, a polysilicon film or a refractory metal silicide film is formed. Then, as shown in FIG. 24, the control gate 62, the interpoly insulating film 60, and the floating gates 46 and 58 are selectively and sequentially etched.

Thereafter, as shown in FIG. 13, necessary post-oxidation is performed, and an insulating film 64 is deposited on the entire surface of the semiconductor substrate 42. The insulating film 64 is opened and a conductive film is buried to form a bit line contact 66. Further, the semiconductor substrate 4
2, a conductive film is formed on the entire surface and patterned to form a bit line wiring 68. Further, an insulating film 70 is formed on the entire surface of the semiconductor substrate 42 including the bit line wiring 68. As described above, the nonvolatile semiconductor memory device according to the second embodiment is manufactured.

The operation of the nonvolatile semiconductor memory device according to the second embodiment is the same as that of the nonvolatile semiconductor memory device according to the first embodiment, and a description thereof will be omitted.

In this nonvolatile semiconductor memory device,
The dimension between word lines (control gates 62) sandwiching the source line (source diffusion layer 48) can be made the same as the word line width, that is, the smallest possible dimension. As described above, since it is not necessary to provide a margin for comparison as compared with the above-described first and second conventional nonvolatile semiconductor memory devices, it is possible to reduce the size of the memory cell in the nonvolatile semiconductor memory device. it can. The source diffusion layer is formed before the trench etching, and is covered with a protective film during the trench etching so as not to be etched.
For this reason, the source line can be formed by a diffusion layer having a planar structure. Therefore, unlike the third conventional nonvolatile semiconductor memory device described above, the problem that the impurity concentration is different between the side wall portion and the plane portion of the trench in the source diffusion layer does not occur.

As described above, according to the nonvolatile semiconductor memory device of the second embodiment, even when trench type element isolation is used, the word line interval between the sources can be minimized, and the source line This can prevent problems such as an increase in resistance from occurring. This allows
The area of the memory cell can be reduced. Further, in the second embodiment, as compared with the first embodiment, after forming the trench element isolation region, the silicon nitride film and the silicon oxide film which are the mask material of the portion where the word line is to be formed are removed. Since there is no need to form a tunnel oxide film, the number of manufacturing steps can be reduced as compared with the first embodiment.

In the nonvolatile semiconductor memory devices according to the first and second embodiments, the NOR type flash memory has been described. However, the present invention is not limited to the NOR type flash memory, and other types of flash memory such as NAND type can be used. It is also applicable to memories. In the third embodiment of the present invention, a case where the present invention is applied to a NAND type will be described.

FIG. 25A is a plan view showing the structure of the nonvolatile semiconductor memory device according to the third embodiment. FIG.
(B) is sectional drawing which followed the 25b-25b line | wire in a top view. The nonvolatile semiconductor memory device shown in FIG.
This is a D-type flash memory.

As shown in FIGS. 25A and 25B, a trench element isolation region 74 is formed in a semiconductor substrate 72 so as to define an element region (active region). In the semiconductor substrate 72, a source diffusion layer 76 is formed orthogonally to between the trench element isolation regions 74.
A silicon oxide film 78 and a silicon oxide film 80 are sequentially formed thereon. On the trench element isolation region 74, an interpoly insulating film 82 is formed.

Further, on the interpoly insulating film 82,
A plurality of control gates 84 are formed, and on both sides of the control gate 84, gates (hereinafter, select gates) 86 of select gate transistors are formed. A source diffusion layer 76 is formed on one side between the select gates 86 of the two select gate transistors, and a bit line contact 88 connected to the drain diffusion layer between the select gates 86 of the two select gate transistors on the other side. Are formed. Further, an insulating film 90 is formed on the entire surface of the semiconductor substrate 72 including the select gate 86 and the control gate 84.

Here, as shown in FIG. 25 (b), one end of the edge of the select gate 86 is formed so as to substantially coincide with one end of the edge of the trench element isolation region 74. In other words, the edge of the lower surface of the select gate 86 on the source diffusion layer 76 side is formed in the trench isolation region 7.
4 is formed so as to coincide with the edge of No. 4 to the extent that there is no problem in the operation function. Thus, the distance between the select gates 86 across the source diffusion layer 76 is the smallest possible dimension.

As described above, in the NAND type nonvolatile semiconductor memory device, the control gate 84 is connected to the source-side select gate 86 and the drain-side select gate 8.
A plurality, for example, eight or sixteen are formed between six.
When there are 16 control gates each with the source line interposed therebetween, the source line is shared by 32 memory cells in the column direction, so that the select gate 86 for reducing the cell size is used.
The influence of the width between the gates is small, but if the width between the select gates is reduced, the cell size is still reduced.

As described above, according to the nonvolatile semiconductor memory device of the third embodiment, the distance between the gates sandwiching the source can be minimized even when the trench type element isolation is used. Thereby, the area of the memory cell can be reduced. Further, as a modified example of the third embodiment, the present invention can be applied to a NOR flash memory with a select gate in which each memory cell unit is formed of one memory cell.

[0084]

As described above, according to the present invention, in a nonvolatile semiconductor memory device using a trench type element isolation, a word line interval between source lines can be minimized, and a source line can be formed. It is possible to provide a nonvolatile semiconductor memory device which does not cause a problem such as an increase in resistance of the semiconductor device.

[Brief description of the drawings]

FIG. 1A is a plan view of a nonvolatile semiconductor memory device according to a first embodiment, and FIG.
1C is a cross-sectional view taken along line 1b, and FIG.
It is sectional drawing which followed the 1c line.

2A and 2B are a plan view and a cross-sectional view illustrating a first step in a method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment.

3A and 3B are a plan view and a cross-sectional view illustrating a second step of the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment.

FIG. 4 is a plan view and a cross-sectional view of a third step in the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment.

FIG. 5 is a plan view and a cross-sectional view of a fourth step in the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment.

6A and 6B are a plan view and a cross-sectional view illustrating a fifth step of the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment.

FIG. 7 is a plan view and a cross-sectional view of a sixth step showing the method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment.

FIG. 8 is a plan view and a cross-sectional view of a seventh step showing the method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment.

FIG. 9 is a plan view and a cross-sectional view of an eighth step showing the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment.

FIG. 10 is a plan view and a cross-sectional view of a ninth step illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment.

FIG. 11 is a plan view and a cross-sectional view of a tenth step showing the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment.

FIG. 12 is a plan view and a cross-sectional view of an eleventh step showing the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment.

FIG. 13A is a plan view of a nonvolatile semiconductor memory device according to a second embodiment, FIG. 13B is a cross-sectional view taken along line 13b-13b in the plan view, and FIG. (c) is a sectional view taken along line 13c-13c in the plan view.

14A and 14B are a plan view and a cross-sectional view illustrating a first step in a method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment.

FIG. 15 is a plan view and a cross-sectional view of a second step in the method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.

FIG. 16 is a plan view and a cross-sectional view of a third step showing the method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.

FIG. 17 is a plan view and a cross-sectional view of a fourth step in the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment.

FIG. 18 is a plan view and a cross-sectional view illustrating a fifth step in the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment.

FIG. 19 is a plan view and a cross-sectional view of a sixth step showing the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment.

FIG. 20 is a plan view and a cross-sectional view of a seventh step showing the method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.

FIG. 21 is a plan view and a cross-sectional view of an eighth step showing the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment.

FIG. 22 is a plan view and a sectional view showing a ninth step of the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment.

FIG. 23 is a plan view and a cross-sectional view showing a tenth step of the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment.

FIG. 24 is a plan view and a cross-sectional view showing an eleventh step of the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment.

FIG. 25A is a plan view showing the structure of the nonvolatile semiconductor memory device according to the third embodiment, and FIG.
Is a sectional view taken along line 25b-25b in the plan view.

FIG. 26A is a plan view showing a structure of a nonvolatile semiconductor memory device using a trench type element isolation according to a first conventional example, and FIGS. 26B to 26D show the nonvolatile semiconductor memory device; FIG. 4 is a cross-sectional view illustrating a structure of a semiconductor memory device.

FIG. 27 (a) is a plan view showing the structure of a nonvolatile semiconductor memory device using a trench type element isolation according to a second conventional example, and FIGS. 27 (b) to (d) show this nonvolatile semiconductor memory device. FIG. 4 is a cross-sectional view illustrating a structure of a semiconductor memory device.

FIG. 28 (a) is a plan view showing the structure of a nonvolatile semiconductor memory device using a trench type element isolation according to a third conventional example, and FIGS. 28 (b) to 28 (e) show the nonvolatile semiconductor memory device; FIG. 4 is a cross-sectional view illustrating a structure of a semiconductor memory device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 2 ... Semiconductor substrate 4 ... Silicon oxide film 6 ... Silicon nitride film 8 ... Source diffusion layer 10 ... Drain diffusion layer 12 ... Silicon oxide film 14 ... Photoresist 16 ... Trench isolation region 16a ... Trench filling material 18 ... Tunnel oxide film 20 ... Floating gate 20a ... Polysilicon film 22 ... Interpoly insulating film 24 ... Control gate 26 ... Insulating film 28 ... Bit line contact 30 ... Bit line wiring 32 ... Insulating film 42 ... Semiconductor substrate 44 ... Tunnel oxide film 46 ... Floating gate 46a ... polysilicon film 48 ... source diffusion layer 50 ... drain diffusion layer 52 ... silicon oxide film 54 ... photoresist 56 ... trench isolation region 56a ... trench filling material 58 ... floating gate 58a ... polysilicon film 60 ... interpoly insulating film 62 control gate 64 insulating film 66 bit line contact 68 bit line wiring 70 insulating film 72 semiconductor substrate 74 trench isolation region 76 source diffusion layer 78 silicon oxide film 80 silicon oxide film 82 inter Poly insulating film 84 ... Control gate 86 ... Gate of select gate transistor 88 ... Bit line contact 90 ... Insulating film

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F001 AA23 AB02 AC03 AD19 AD41 AD52 AD53 AD60 AE02 AE03 AE08 AG07 AG10 AG28 5F083 EP23 EP33 EP34 EP76 EP77 ER02 ER05 ER14 ER16 ER22 GA02 GA09 JA35 KA11 KA14 MA06 MA20 PR01 PR06

Claims (10)

[Claims] A plurality of trench isolation regions formed to define an active region in a semiconductor substrate; and a plurality of trench isolation regions formed in the active region so as to be sandwiched between the trench isolation regions. A drain region of a reverse conductivity type; a charge storage layer formed on the active region so as to be capacitively coupled to the active region; and a control formed on the charge storage layer so as to be capacitively coupled to the charge storage layer. A gate formed on the opposite side of the drain region with respect to the control gate so as to be in parallel with the control gate, and having a source region of a conductivity type and a reverse conductivity type of the semiconductor substrate; The edge facing the source region substantially coincides with the edge of the lower surface of the charge storage layer, and the source region is formed in a substantially planar shape in the semiconductor substrate. The nonvolatile semiconductor memory device according to claim and. 2. A semiconductor device, comprising: a plurality of trench element isolation regions formed to define an active region in a semiconductor substrate; and a plurality of trench element isolation regions formed in the active region so as to be sandwiched between the trench element isolation regions. A drain region of opposite conductivity type, a first select gate transistor formed adjacent to the drain region, a charge storage layer formed on the active region so as to be capacitively coupled to the active region, A control gate formed on the storage layer so as to be capacitively coupled to the charge storage layer; and a memory cell having the charge storage layer and the control gate, the memory cell having a pair of select gate transistors. A second select gate transistor formed on the opposite side of the first select gate transistor; and a second select gate transistor adjacent to the second select gate transistor. A source region of a conductivity type and a reverse conductivity type of the semiconductor substrate, which is formed in parallel with the control gate, and an edge of the trench element isolation region facing the source region is formed of the second select gate transistor. A nonvolatile semiconductor memory device substantially coincident with an edge of a lower surface of a gate, wherein the source region is formed substantially planar in the semiconductor substrate. 3. The nonvolatile semiconductor memory device according to claim 1, wherein a surface position of said source region substantially coincides with a surface position of said semiconductor substrate. 4. A step of forming a first mask material on a semiconductor substrate, and a step of forming a source diffusion layer in the semiconductor substrate in a linear shape by an ion implantation method using the first mask material as a mask. Forming a first insulating film in a self-aligned manner with the source diffusion layer; forming a second mask material so as to cover an element forming region; and forming the first mask material and the semiconductor substrate. Forming a trench by etching by etching using the first insulating film and the second mask material as a mask, forming a trench isolation region by burying a second insulating film in the trench, Removing the first mask material left in the element formation region to form a groove; forming a first gate insulating film on the exposed surface of the semiconductor substrate in the groove; 1 game Forming a first conductive film on the insulating film; forming a third insulating film and a second conductive film on the first conductive film; Forming a charge storage layer, a second gate insulating film, and a control gate by patterning an insulating film and a first conductive film, a method for manufacturing a nonvolatile semiconductor memory device. 5. A step of linearly forming a plurality of first mask members on a semiconductor substrate; introducing impurities into the semiconductor substrate using the first mask members as a mask; Forming a second mask material over the entire surface of the semiconductor substrate, and selectively leaving the second mask material in a desired region between the first mask materials. Forming a third mask material in a line so as to be substantially orthogonal to the first mask material; and forming the first mask material using the second mask material and the third mask material as masks. Forming a trench by removing the semiconductor substrate to a position deeper than the impurity introduction region; and forming an element isolation region by burying an insulating film in the trench after removing the third mask material. Remaining below the third mask material Removing the first mask material thus formed to expose the surface of the semiconductor substrate; forming a first gate insulating film on the surface of the semiconductor substrate; A step of forming a first conductive film; a step of linearly patterning the first conductive film so as to be substantially orthogonal to the second mask material; and a second gate on the first conductive film. Forming an insulating film; forming a second conductive film on the second gate insulating film; forming a second conductive film on the second conductive film having substantially the same width as the second mask material. Forming a plurality of fourth mask materials in a linear shape so as to sandwich the second mask material at intervals; and forming the second conductive film using the fourth mask material as a mask;
A step of sequentially etching the second gate insulating film and the first conductive film. A method for manufacturing a nonvolatile semiconductor memory device, comprising: 6. A method of forming a first mask material in a portion where a word line is to be formed on a semiconductor substrate of a first conductivity type; and an ion implantation method using the first mask material as a mask. Forming a source diffusion layer and a drain diffusion layer of a second conductivity type opposite to the first conductivity type therein; and forming a first diffusion layer on the entire surface of the semiconductor substrate including on the first mask material. Depositing an insulating film of: a step of isotropically etching the first insulating film to selectively leave the first insulating film on the source diffusion layer; and covering an element formation region. A step of forming a second mask material; a step of sequentially etching the first mask material and the semiconductor substrate by etching using the first insulating film and the second mask material as a mask; 2 after removing the mask material Depositing a filling material over the entire surface of the semiconductor substrate; removing the filling material above the upper surface of the first insulating film to form a trench isolation region; and forming a trench element isolation region below the second mask material. Forming a groove by removing the remaining first mask material; forming a first gate insulating film on the exposed surface of the semiconductor substrate in the groove; and forming a groove in the groove. A first conductive film is deposited on the entire surface of the semiconductor substrate including the first gate insulating film, and the first conductive film is selectively etched to form a slit between memory cells adjacent in the word line direction. Forming a second conductive film on the entire surface of the semiconductor substrate including on the first conductive film;
Forming an insulating film and a second conductive film sequentially, and selectively etching the second conductive film, the second insulating film, and the first conductive film sequentially to control each of the word lines. Forming a gate, a second gate insulating film, and a charge storage layer. A method for manufacturing a nonvolatile semiconductor memory device, comprising: 7. A step of forming a first gate insulating film on a semiconductor substrate, a step of patterning a first conductive film on the first gate insulating film, and a step of masking the first conductive film. Forming a source diffusion layer in the semiconductor substrate in a linear shape by the ion implantation method, forming a first insulating film in self-alignment with the source diffusion layer, and covering the element formation region. Forming a first mask material; and forming a trench by etching the first conductive film and the semiconductor substrate by etching using the first insulating film and the first mask material as a mask. Forming a trench element isolation region by burying a second insulating film in the trench; forming a second conductive film on the surface of the first conductive film; and forming a second conductive film on the second conductive film. Third insulating film, third conductor Forming a film, patterning the third conductive film, the third insulating film, and the second conductive film to form a control gate, a second gate insulating film, and a charge storage layer; A method for manufacturing a nonvolatile semiconductor memory device, comprising: 8. A step of forming a first gate insulating film on a semiconductor substrate; a step of forming a plurality of first conductive films linearly on the first gate insulating film; Introducing an impurity into the semiconductor substrate using the conductive film as a mask to form an impurity introduction region of a conductivity type opposite to that of the semiconductor substrate; forming a first mask material over the entire surface of the semiconductor substrate; Selectively leaving a first mask material in a desired region between the conductive films; forming a second mask material in a linear shape so as to be substantially perpendicular to the first mask material; Using the first mask material and the second mask material as masks, the first conductive film, the first gate insulating film, and the semiconductor substrate are removed to a position deeper than the impurity introduction region to form a trench. And after removing the second mask material, Forming an element isolation region by burying an insulating film in the trench, forming a second conductive film on the entire surface of the semiconductor substrate including the first conductive film left below the second mask material Performing a step of linearly patterning the second conductive film so as to be substantially orthogonal to the first mask material; and forming a second gate insulating film on the second conductive film. Forming a third conductive film on the second gate insulating film; and forming the first mask on the third conductive film at substantially the same interval as the width of the first mask material. Forming a plurality of third mask materials in a linear shape so as to sandwich the material, the third conductive film using the third mask material as a mask,
A method of sequentially etching a second gate insulating film and a second conductive film, the method comprising manufacturing a non-volatile semiconductor memory device. 9. A step of forming a first conductive film on a portion where a word line is to be formed on a semiconductor substrate of a first conductivity type via a first gate insulating film; and using the first conductive film as a mask. Ion implantation method
Forming a source diffusion layer and a drain diffusion layer of a second conductivity type opposite to the first conductivity type in the semiconductor substrate; and an entire surface of the semiconductor substrate including on the first conductive film First
Depositing an insulating film of: a step of isotropically etching the first insulating film to selectively leave the first insulating film on the source diffusion layer; and covering an element formation region. A step of forming a first mask material; a step of sequentially etching the first conductive film and the semiconductor substrate by etching using the first insulating film and the first mask material as a mask; A step of depositing a filling material over the entire surface of the semiconductor substrate after removing the first mask material; and a step of removing the filling material above the upper surface of the first insulating film to form a trench element isolation region. Depositing a second conductive film over the entire surface of the semiconductor substrate including over the first conductive film left under the first mask material, and selectively etching the second conductive film; Memory adjacent to word line Forming a slit between Le, second on the entire surface of the semiconductor substrate including the second conductive film on
Forming an insulating film and a third conductive film sequentially; and selectively etching the third conductive film, the second insulating film, and the second conductive film sequentially to control each of the word lines. Forming a gate, a second gate insulating film, and a charge storage layer. A method for manufacturing a nonvolatile semiconductor memory device, comprising: 10. The step of depositing the first insulating film,
The first insulating film is １ ／ of a distance between the first mask material or the first conductive film sandwiching the source diffusion layer.
10. The method according to claim 6, wherein the first mask material or the first conductive film sandwiching the drain diffusion layer is deposited to be thinner than half the distance between the first mask material and the first conductive film. A method for manufacturing a nonvolatile semiconductor memory device.