KR100297109B1 - Flash memory device and method of manufacturing and erasing the same - Google Patents

Abstract

The present invention relates to a flash memory device, a manufacturing method and an erasing method thereof, an element isolation film for separating an active region and a field region in a selected region on a semiconductor substrate, a word line formed to vertically cross the element isolation layer, A source line and a drain region formed by an impurity ion implantation process using a word line as a mask, a drain line formed over the drain region between the word lines, and an active region separated by the device isolation layer, and perpendicular to the word line It comprises a source line formed to intersect.

According to the present invention, since the source line is formed to intersect the word line vertically, bit erasing that selects and erases one cell is possible, and over erasing can be prevented by erasing only the selected bit. Only the bit can be implemented, so that the characteristics of the device can be improved, for example, to improve recovery efficiency.

Description

Flash memory device, method of manufacturing and erasing the same {Flash memory device and method of manufacturing and erasing the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory, and in particular, by allowing the word line and the source line to cross vertically, all operations of the existing flash memory are enabled, and bit erasing is possible to solve the problem of over erasing. The present invention relates to a flash memory device, a method of manufacturing the same, and an erasing method capable of improving device characteristics.

A conventional method of manufacturing a flash memory device will be described with reference to the layout of FIG. 1.

The field oxide film 1 is formed in an oxidation process using an element isolation mask in a selected region on the semiconductor substrate. The tunnel oxide film and the first polysilicon film 2 are sequentially formed on the semiconductor substrate including the field oxide film 1. The first polysilicon film 2 and the tunnel oxide film are etched by a lithography process and an etching process using the first polysilicon mask to expose a predetermined region of the field oxide film 1. The first polysilicon mask is formed to expose a predetermined region of the field oxide film 1 formed by the device isolation mask. After the dielectric film and the second polysilicon film are formed on the entire structure, the second polysilicon film, the dielectric film, the first polysilicon film, and the tunnel oxide film are sequentially formed by a lithography process and a self-aligned etching process using a word line mask. Etching and etching a predetermined region of the field oxide layer form a stacked gate structure, that is, word line 3, in which floating gates and control gates are stacked. The word line mask is formed in such a shape because the word line mask is formed to vertically cross the device isolation mask along the top of the field oxide film exposed by the first polysilicon mask. An impurity ion implantation process is performed to form the source line 4 and the drain region. The source line 4 is formed to be parallel to the word line. After forming an interlayer insulating film on the entire structure, a predetermined region of the interlayer insulating film is removed by a lithography process and an etching process using a metal contact mask to form a contact hole 5 exposing a portion of the source line and a drain region. The metal layer is formed on the entire structure to fill the contact hole 5, and then the bit line 6 is formed by a patterning process using a bit line mask.

Conventional flash memory devices manufactured in the above layout have the following problems.

First, since the flash memory device erases the charge stored in the floating gate with a source, the erase is performed sector by sector in the above structure in which the word line and the source line are formed in parallel. Therefore, bit erasing that can erase one cell unit is impossible.

Second, since the erase is performed in units of sectors as described above, the erase speed is different for each cell. Thus, a problem arises in that a cell that has already been erased is erased while another cell is erased.

Third, the recovery efficiency is lowered because the recovery is performed in units of drain lines.

Fourth, contact holes exist in a part of the drain and the source line, and a metal layer is formed to fill the gap, and a bit line is formed by patterning the metal layer, thereby decreasing the integration degree.

Fifth, since the source line is formed by diffusion of impurities, the operation speed of the device due to the resistance is lowered.

Accordingly, an object of the present invention is to provide a flash memory device, a manufacturing method thereof, and an erasing method capable of enabling sector erasing and bit erasing, and improving the reliability of the device since the operation speed of the device is not deteriorated.

A flash memory device according to the present invention for achieving the above object is a semiconductor substrate, a device isolation film for separating an active region and a field region in a selected region on the semiconductor substrate, and a word line formed to cross perpendicular to the device isolation film And a source and drain region formed by an impurity ion implantation process using the word line as a mask, a drain line formed over the drain region between the word lines, and the word line on an active region separated by the device isolation layer. And a source line formed to intersect with each other vertically.

In addition, a method of manufacturing a flash memory device according to the present invention for achieving the above object is formed by forming a device isolation film in a selected region on a semiconductor substrate, and sequentially forming a tunnel oxide film and a first polysilicon film on the entire structure Etching the selected regions of the first polysilicon film and the tunnel oxide film to expose a predetermined region of the device isolation layer, and sequentially forming a dielectric film and a second polysilicon film on the entire structure, and then the second polysilicon. Sequentially etching the film, the dielectric film, the first polysilicon film, and the tunnel oxide film to form a word line crossing the device isolation layer, and performing an impurity ion implantation process using the word line as a mask. Forming a source and drain region thereon, and forming a conductive layer over the drain region Forming a drain line in parallel with the word line by forming a drain line, forming a contact layer exposing the source region after forming an interlayer insulating film on the entire structure, and filling the contact hole on the entire structure so as to fill the contact hole. And depositing a metal layer and patterning the metal layer so as to vertically cross the word line to form a source line.

On the other hand, the flash memory device erase method according to the present invention for achieving the above object applies a voltage of 5V to all the source lines of the flash memory device formed so as to cross the source line perpendicular to the word line, and to all word lines Erasing is performed in units of sectors by applying a voltage of −9 V, and bit erasing by applying voltages of 5 V and −9 V to a source line and a word line selecting one cell, respectively.

1 is a layout of a conventional flash memory device.

2 is a layout of a flash memory device according to the present invention.

3 is a cross-sectional view taken along the line AA ′ of FIG. 2;

4 is a cross-sectional view taken along the line BB ′ of FIG. 2.

<Explanation of symbols for main parts of the drawings>

1, 10 and 102: field oxide film 2, 20 and 104: first polysilicon film

3 and 30: wordline 4 and 60: source line

5 and 50: contact hole 6: bit line

40: drain line 101: semiconductor substrate

103 tunnel oxide film 105 dielectric film

106: second polysilicon film 107: source region

108: drain region 109: conductive layer

110: interlayer insulating film 111: metal layer

The present invention will be described in detail with reference to the accompanying drawings.

2 is a layout of a flash memory device according to the present invention, FIG. 3 is a cross-sectional view taken along the line AA ′ of FIG. 2, and FIG. 4 is a cross-sectional view taken along the line BB ′ of FIG. 2. With reference to these, the flash memory device according to the present invention will be described in the order of manufacturing method.

Field oxide films 10 and 102 are formed in an oxidation process using an element isolation mask in a selected region on the semiconductor substrate 101. The device isolation mask is formed in a pattern at predetermined intervals so that the field oxide films 10 and 102 formed by the oxidation process thereby expose a predetermined region of the semiconductor substrate 101. After the tunnel oxide film 103 and the first polysilicon films 20 and 104 are sequentially formed on the entire structure, the first polysilicon films 20 and 104 and the lithography process and the etching process using the first polysilicon mask are performed. The predetermined region of the tunnel oxide film 103 is etched to expose the predetermined regions of the field oxide films 10 and 102. The first polysilicon mask is formed to cover the entire structure and to expose only a predetermined region of the field oxide films 10 and 102. The dielectric film 105 and the second polysilicon film 106 are sequentially formed over the entire structure. In this case, a tungsten silicide film and an anti-reflection film may be further formed on the second polysilicon film 106. A second polysilicon film 106, a dielectric film 105, a first polysilicon film 104, and a tunnel oxide film are formed by performing a lithography process and a self-aligned etching process using a word line mask formed to perpendicularly intersect the device isolation mask. The 103 is sequentially etched to form a stacked gate structure in which a floating gate and a control gate, which serve as a word line 30, are stacked. An impurity ion implantation process is performed to form the source 107 and drain 108 regions on the exposed semiconductor substrate 101. A conductive layer 109 such as a polysilicon film or a metal layer is formed on the drain region 108 and then patterned to form a drain line 40. The drain line 40 is formed in parallel with the word line 30. After the interlayer insulating layer 110 is formed on the entire structure, the contact hole 50 exposing the source region 107 is formed by etching the selected region of the interlayer insulating layer 110 by a lithography process and an etching process using a source contact mask. do. After forming the metal layer 111 on the entire structure to fill the contact hole 50, the source layer 60 is formed by patterning the metal layer by a lithography process and an etching process using a source line mask.

The flash memory device having the layout as described above enables not only sector erasing but also bit erasing. That is, only one cell can be selectively erased by forming the source line formed of the metal layer to cross the word line vertically. In addition, the operation of other devices is the same as that of a conventional flash memory device. If this is explained in more detail as follows.

First, the sector-by-sector erasing is performed by applying a voltage of 5 V to the source lines 1 through 3 and a voltage of -9 V through the word lines 1 through 4 in the same manner as the erase method of the conventional flash memory device. .

On the other hand, for bit erasure that can be achieved in the present invention, for example, in order to erase a cell where the source line 1 and the word line 1 cross each other, a voltage of 5 V is applied to the source line 1 and a voltage of -9 V to the word line 1. It is applied to maintain the 0V or floating state in common to the remaining source line and word line, and all drain lines to maintain the floating state.

In addition, recovery, program, and reading methods are the same as the existing methods. However, the recovery may be performed in units of word lines by selecting an arbitrary word line and a drain among the word lines. That is, the source line and the word line of the over erased cell may be selected to selectively recover only the bit.

As described above, according to the present invention, since the source line formed of the metal layer is formed to intersect the word line vertically, bit erasing to select and erase one cell is possible, and over erasing can be prevented by erasing only selected bits. In addition, since the recovery can be performed only on the bits that are excessively erased, the characteristics of the device can be improved, for example, the recovery efficiency can be improved.

Claims (5)

A semiconductor substrate, An isolation layer for separating the active region and the field region from the selected region on the semiconductor substrate; A word line formed to vertically cross the device isolation layer; Source and drain regions formed by an impurity ion implantation process using the word line as a mask; A drain line formed over the drain region between the word lines; And a source line formed to vertically cross the word line on an active region separated by the device isolation layer. The flash memory device of claim 1, wherein the drain line is formed of a conductor. 3. The flash memory device of claim 2, wherein the conductor is a polysilicon film or a metal layer. Forming an isolation film in a selected region on the semiconductor substrate, Sequentially forming a tunnel oxide film and a first polysilicon film on the entire structure, and then etching selected regions of the first polysilicon film and the tunnel oxide film to expose a predetermined region of the device isolation film; After the dielectric film and the second polysilicon film are sequentially formed on the entire structure, the second polysilicon film, the dielectric film, the first polysilicon film, and the tunnel oxide film are sequentially etched to cross the vertical lines with the device isolation layer. Forming a, Forming a source and a drain region on the semiconductor substrate by performing an impurity ion implantation process using the word line as a mask; Forming a conductive line on the drain region and patterning the conductive layer to form a drain line in parallel with the word line; Forming a contact hole exposing the source region after forming an interlayer insulating film over the entire structure; And depositing a metal layer on the entire structure so that the contact hole is buried, and patterning the metal layer to cross the word line vertically to form a source line. A voltage of 5V is applied to all source lines of the flash memory device formed so as to cross the source line perpendicularly to the word line, and a voltage of -9V is applied to all word lines to perform erasing in sector units, and one cell is selected. And erasing bits by applying voltages of 5V and -9V to the source line and the word line, respectively.