JP3604845B2 - Nonvolatile memory device and method of manufacturing the same - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device having a structure capable of preventing a source line from being divided.
[0002]
[Prior art]
A non-volatile memory element connects a memory cell having a stacked structure of a floating gate and a control gate, a bit line for reading information stored in the memory cell, a control gate electrode, and adjacent memory cells. And word lines.
[0003]
Among the nonvolatile memory elements, flash memories characterized by collectively erasing information of all cells are classified into NOR type and NAND type. A NAND flash memory has eight or sixteen cell transistors connected in series to one bit line contact, and has a low information reading and writing speed, whereas a NOR flash memory has one bit line contact. Two cell transistors are connected to the contact in parallel, and the speed of reading and writing information is very high. Therefore, NOR flash memories are widely used in microcomputer products and high-speed DRAM interface flash products.
[0004]
1A to 1E are cross-sectional views illustrating a conventional nonvolatile memory device.
[0005]
Reference numerals 3a and 3b denote bit line contacts, 7 denotes a floating gate isolation region, 11 denotes a semiconductor substrate, 13 denotes a field oxide film, 14 denotes a first active region, 15 denotes a second active region, and 16 denotes a second active region. Reference numeral 17 indicates a control gate, and reference numeral 17 indicates a source line.
[0006]
FIG. 1A is a layout diagram of a conventional nonvolatile memory cell array, and the steps of the process are as follows.
[0007]
First step: After forming a field oxide film 13 on a semiconductor substrate to define a first active region 14 and a second active region 15 that intersect at right angles to each other, a first dielectric film (see FIG. (Not shown).
[0008]
Second step: depositing a floating gate electrode material on the first dielectric layer.
[0009]
Third step: The floating gate electrode material existing between the bit line contact 3a and the bit line contact 3b in parallel with the first active region 14 is removed to form the floating gate isolation region 7.
[0010]
Fourth step: a second dielectric layer (not shown) and a control gate electrode material (patterned into a control gate 16 in a subsequent step) are sequentially deposited on the semiconductor substrate.
[0011]
Fifth step: The control gate 16 is formed by leaving the control gate electrode material between each bit line contact 3a, 3b and the second active region 15 so as to be in a band shape in parallel with the second active region 15. .
[0012]
Sixth step: After etching the second dielectric layer using the control gate 16 as a mask, the remaining floating gate electrode material is etched using a self-aligned etching method.
[0013]
Seventh step: forming a bit line connecting the bit line contacts 3a and 3b.
[0014]
In the third step, when the floating gate isolation region 7 is formed, in the region L where the floating gate isolation region 7 and the second active region 15 intersect, the floating gate electrode material is etched to expose the semiconductor substrate. Become.
[0015]
When the sixth step is performed in such a state, a pitching phenomenon occurs in which the semiconductor substrate in the region L is etched.
[0016]
This pitching phenomenon is shown in detail in FIG. 1A, which is a cross-sectional view taken along line AA ′ of FIG. 1A, and FIG. 1C, which is a cross-sectional view taken along line BB ′.
[0017]
Referring to FIG. 1C, a dielectric layer (not shown) and a control gate 16 are formed on the field oxide layer 13, and the semiconductor substrate 11 in the second active region 15 is etched.
[0018]
This pitching phenomenon causes a problem of dividing the source line in a subsequent step, that is, a step of forming a source line connecting the source regions of the respective memory cell transistors in the second active region 15.
[0019]
Referring to FIG. 1D, when the ion implantation is performed asymmetrically to form the source line 17 on the semiconductor substrate 11 in which the pitching phenomenon has occurred, a divided portion of the source line such as a portion may occur. I understand. Further, referring to FIG. 1E, it can be seen that even when the semiconductor substrate 11 on which another type of pitching has occurred is ion-implanted symmetrically, a divided portion of the source line like the portion b occurs.
[0020]
When the ion implantation process is performed on the semiconductor substrate on which pitching has occurred as described above, there is a problem that not only the source line disconnection phenomenon but also the source line resistance is significantly increased.
[0021]
When the resistance of the source line increases, the voltage applied to the source line must be increased. However, this has a limit, so that it is not possible to obtain a constant cell characteristic.
[0022]
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. In a process of self-aligned etching of a floating gate using a control gate as a mask, a source line is divided by a pitching phenomenon in which a semiconductor substrate is etched. It is an object of the present invention to provide a non-volatile memory element having a structure for preventing the non-volatile memory element.
[0023]
[Means for Solving the Problems]
According to an embodiment of the present invention, there is provided a nonvolatile memory device including: a bit line contact connected to a drain of each memory cell transistor; A first active region in which the memory cell transistors are formed symmetrically; and a second active region in a direction perpendicular to the first active region, the source lines connecting the sources of the memory cell transistors. A second active region, a field oxide film formed in a region between the first active regions and also between the second active regions, and a field oxide film formed on the field oxide film, A floating gate isolation region smaller than a field oxide film, between the bit line contact and the second active region; Characterized in that it comprises a control gate formed in parallel with the second active region.
[0024]
According to another embodiment of the present invention, there is provided a nonvolatile memory device including: a bit line contact connected to a drain of each memory cell transistor; A first active region in which the memory cell transistors are formed symmetrically with respect to the bit line contact; and a second active region perpendicular to the first active region, the source of each memory cell transistor being connected. A second active region in which a source line to be formed is formed; a field oxide film formed in a region between the first active regions and also between the second active regions; and a field oxide film formed on the field oxide film. A floating gate isolation region formed to be longer than the field oxide film in a direction of the first active region; Characterized in that it comprises a control gate formed in parallel with the second active region between the contact and the second active region.
[0025]
According to another embodiment of the present invention, there is provided a nonvolatile memory device including: a bit line contact connected to a drain of each memory cell transistor; A first active region in which the memory cell transistors are formed symmetrically with respect to the bit line contact; and a second active region perpendicular to the first active region, the source of each memory cell transistor being connected. A second active region in which a source line to be formed is formed, a field oxide film formed between the first active region and the second active region, and a floating gate isolation formed on the field oxide film. And a capacitor formed between the bit line contact and the second active region in parallel with the second active region. A roll gate, to provide a nonvolatile memory device whose width is characterized in that it comprises a narrow control gate in said field oxide film than the first active region.
[0026]
Preferably, the floating gate isolation region is smaller than the field oxide film or extends in the direction of the first active region beyond a region on the field oxide film.
[0027]
Therefore, in the nonvolatile memory device according to the present invention, by improving the shape of the floating gate isolation region or the floating gate isolation region and the control gate, the semiconductor substrate is etched in the process of self-aligning the floating gate using the control gate as a mask. Pitching phenomenon can be suppressed. Therefore, it is possible to prevent the source line from being electrically disconnected or the resistance from being increased during the subsequent process, that is, the ion implantation process for forming the source line, thereby contributing to the stable operation of each cell and the improvement of the yield. can do.
[0028]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.
[0029]
2A to 2C are views for explaining a nonvolatile memory device according to an embodiment of the present invention.
[0030]
Reference numerals 23a and 23b denote bit line contacts, 24 denotes a first active region, 25 denotes a second active region, 27 denotes a floating gate isolation region, 31 denotes a semiconductor substrate, 33 denotes a field oxide film, and 36 denotes a field oxide film. Control gates are shown.
[0031]
FIG. 2A is a layout diagram of a part of the nonvolatile memory cell array.
[0032]
The nonvolatile memory according to this embodiment includes a first active region 24 in which memory cell transistors are formed symmetrically with respect to the bit line contacts 23a and 23b, the respective bit line contacts 23a and 23b, and a first active region. 24, and a second active region 25 where a source line connecting the sources of the respective memory cell transistors is formed, and between two adjacent first active regions 24 and two adjacent second active regions 25 are formed. The field oxide film 33 and the floating gate isolation region 27 formed between the active regions 25 and the second active region 25 are formed between the bit line contacts 23a and 23b and the second active region 25. And a control gate 36.
[0033]
In this embodiment, in order to prevent the source of each memory cell transistor from being divided in the second active region 25, the floating gate isolation region 27 is so formed as to fit within the region on the field oxide film 33. It is formed smaller than 33.
[0034]
A floating gate electrode material exists in a portion other than the floating gate isolation region 27. Therefore, when the floating gate electrode material is self-aligned etched using the control gate 36 as a mask in such a state, the remaining portion of the M portion where the region between the adjacent floating gate isolation regions 27 and the second active region 25 intersect is left. Since the floating gate electrode material is etched, the semiconductor substrate is not etched, and the pitching phenomenon does not occur.
[0035]
2B and 2C are cross-sectional views taken along lines AA 'and BB' in FIG. 2A, respectively. A dielectric film (not shown) and a control gate 36 are formed on the field oxide film 33, and the source It can be seen that the pitching phenomenon does not occur in the second active region 25 where the line is formed.
[0036]
According to the present invention, a step in a semiconductor substrate in an active region, that is, a phenomenon in which a source line is electrically disconnected or a resistance is increased during ion implantation for forming a source line in a subsequent process due to a conventional pitching phenomenon can be prevented, It is extremely useful for stable operation of the cell and improvement of the yield.
[0037]
3A to 3C are cross-sectional views illustrating a nonvolatile memory device according to another embodiment of the present invention.
[0038]
Reference numerals 43a and 43b denote bit line contacts, 47 denotes a floating gate isolation region, 51 denotes a semiconductor substrate, 53 denotes a field oxide film, 44 denotes a first active region, 45 denotes a second active region, and 56 denotes a second active region. Control gates are shown.
[0039]
FIG. 3A is a layout diagram of a part of the nonvolatile memory cell array. In this embodiment, the floating gate isolation region 47 is formed on the field oxide film 53, and is formed longer than the length of the field oxide film 53 in the direction in which the first active region 44 extends. It is configured similarly to.
[0040]
Since the floating gate isolation region 47 overlaps a part of the region on the second active region 45, the floating gate electrode is formed at the N portion where the region between the adjacent floating gate isolation region 47 and the second active region 45 intersects. There is a portion where the substance remains (overlapping portion) and a portion where the semiconductor substrate is exposed (non-overlapping portion).
[0041]
When the floating gate electrode material is self-aligned etched using the control gate 56 as a mask in such a state, a pitching phenomenon occurs in which the exposed semiconductor substrate is etched in a part of the N portion. However, since only a portion of the N portion is etched, the source line is not separated during a subsequent process, that is, a process of forming a source line connecting the source regions of the respective memory cell transistors in the second active region 45. Absent.
[0042]
3B is a cross-sectional view taken along line AA ′ of FIG. 3A, and FIG. 3C is a cross-sectional view taken along line BB ′. A dielectric film (not shown) and a control gate 56 are formed on the field oxide film 53. This indicates that only a part of the semiconductor substrate is etched in the second active region 55 where the source line is formed.
[0043]
FIG. 4 is a layout diagram for explaining a nonvolatile memory device according to another embodiment of the present invention.
[0044]
Reference numerals 63a and 63b denote bit line contacts, 64 denotes a first active region, 65 denotes a second active region, 73 denotes a field oxide film, and 76 denotes a control gate.
[0045]
As shown in the layout diagram of FIG. 4, in this embodiment, the control gate 76 is formed between the bit line contacts 63a and 63b and the second active region 65 in parallel with the second active region 65, and The width h on the oxide film 73 is smaller than the width h ′ on the first active region 64. This is to increase the channel length formed between the drain and the source in the first active region 64. Other parts are the same as in FIG. 2A.
[0046]
In this embodiment, in order to prevent the source of each memory cell transistor from being disconnected, as in the embodiment shown in FIG. 2A, the length of the floating gate isolation region 67 (in the first active region 64 direction) Is shorter than the length of the field oxide film 73 (the length in the direction of the first active region 64) or, as in the embodiment shown in FIG. Are formed so as to be separated from each other at a considerable interval.
[0047]
The present invention is not limited to the specific embodiments described above, and various modifications are possible within the scope of the technical idea of the present invention.
[0048]
【The invention's effect】
In the nonvolatile memory device according to the present invention, by improving the shape of the floating gate isolation region or the floating gate isolation region and the control gate, the semiconductor substrate is etched when the floating gate is self-aligned etched using the control gate as a mask. The pitching phenomenon can be suppressed. Therefore, it is possible to prevent a source line from being electrically disconnected or a resistance from being increased in a subsequent process, that is, an ion implantation process for forming a source line, and to stably operate and improve the yield of each cell. Contribute to the improvement of
[0049]
[Brief description of the drawings]
FIG. 1A is a layout diagram for explaining a conventional nonvolatile memory element.
FIG. 1B is a cross-sectional view taken along line AA ′ of FIG. 1A.
FIG. 1C is a sectional view taken along line BB ′ of FIG. 1A.
FIG. 1D is a cross-sectional view taken along line AA ′ of FIG. 1A.
FIG. 1E is a sectional view taken along line AA ′ of FIG. 1A.
FIG. 2A is a layout diagram for explaining a nonvolatile memory element according to one embodiment of the present invention;
FIG. 2B is a sectional view taken along line AA ′ of FIG. 2A.
FIG. 2C is a sectional view taken along line BB ′ of FIG. 2A.
FIG. 3A is a layout diagram illustrating a nonvolatile memory device according to another embodiment of the present invention;
FIG. 3B is a cross-sectional view taken along line AA ′ of FIG. 3A.
FIG. 3C is a sectional view taken along line BB ′ of FIG. 3A.
FIG. 4 is a layout diagram for explaining a nonvolatile memory device according to another embodiment of the present invention.
[Explanation of symbols]
3a, 3b Bit line contact 7 Floating gate isolation region 11 Semiconductor substrate 13 Field oxide film 14 First active region 15 Second active region 16 Control gate 17 Source line 23a, 23b Bit line contact 24 First active region 25 Second active region 27 Floating gate isolation region 31 Semiconductor substrate 33 Field oxide film 36 Control gate 43a, 43b Bit line contact 44 First active region 45 Second active region 47 Floating gate 51 Semiconductor substrate 53 Field oxide film 56 Control gate 63a, 63b Bit line contact 64 First active region 65 Second active region 73 Field oxide film 76 Control gate

Claims (2)

A bit line contact connected to the drain of each memory cell transistor;
A first active region for forming the memory cell transistor symmetrically about the bit line contact so as to contact the bit line contact;
A second active region forming a source line connecting the sources of the memory cell transistors in a direction perpendicular to the first active region;
A field oxide film formed in a region surrounded by the first active region and the second active region;
A floating gate isolated on the field oxide film;
A method for manufacturing a non-volatile memory device including a control gate formed between the bit line contact and the second active region in parallel with the second active region ,
Removing a portion of the floating gate electrode material in a floating gate isolation region such that the floating gate isolated on the field oxide film is formed;
A second step of forming the floating gate by self-aligning etching of the floating gate electrode material using the control gate as a mask,
In the first step, forming, as the floating gate isolation region, a region which is parallel to the first active region, crosses the field oxide film, reaches the second active region, and is isolated on the second active region. A method for manufacturing a nonvolatile memory element . A bit line contact connected to the drain of each memory cell transistor;
A first active region for forming the memory cell transistor symmetrically about the bit line contact so as to contact the bit line contact;
A second active region forming a source line connecting the sources of the memory cell transistors in a direction perpendicular to the first active region;
A field oxide film formed in a region surrounded by the first active region and the second active region ;
A second active region formed parallel to the control gate between the bit line contact and the second active region, Tsu narrowly in the field oxide film than its width the first active region and the control gates,
A nonvolatile memory element comprising:

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