JP2001274663A - Power semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem of a conventional power semiconductor device that has had difficulties of improving the element breaking capability, a high switching speed and a switching loss. SOLUTION: A snubber capacitor 15 is connected between a collector electrode and an emitter electrode of an IGBT 11 and a gate resistor 12 is connected to its gate electrode. The power semiconductor device is characterized in that an expression of Rg<(16,000×Cs/(A×Ic)+750)/Cg holds among a resistance Rg (ohms) of the gate resistor 12, a capacitance Cs (nF) of the snubber capacitor 15, a gate capacitance Cg (nF), an element valid area A (cm2) and a current Ic (A) flowing through between the collector and emitter electrodes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate bipolar transistor, and more particularly to a power semiconductor device such as an IGBT for controlling large power.

[0002]

2. Description of the Related Art Conventionally, MOS gate devices such as IGBTs are
For example, since the capacity was about 600 V and 1000 A,
Charge / discharge type snubber circuits have not been generally used. However, IGBTs have been increased in capacity and withstand voltage, and their use has been extended to applications where GTO was conventionally used, such as inverters for driving high-voltage motors and power transmission and distribution. In such a field, since a high withstand voltage of 4 kV or more is required, a charge / discharge type snubber circuit has been used unlike a conventional medium-capacity inverter. The snubber capacitor Cs constituting the snubber circuit commutates a current flowing through the element at the time of turn-off, thereby suppressing a rising speed of a voltage between the main electrodes. As a result, the turn-off process of the element falls within the safe operation area, and the element can be prevented from being destroyed.

On the other hand, in this type of MOS power device, a gate resistor is connected to a gate electrode. The gate resistance delays the turn-off operation when the device is turned off, and as a result, has a function of expanding a safe operation area.
In other words, even when the voltage between the main electrodes increases during the turn-off of the element, the negative charge of the electrons reduces the high electric field inside the element and injects the safe operation area by injecting electrons from the channel region of the MOS transistor. Can be spread. For this purpose, a gate resistor having a relatively large resistance value is used.

[0004]

Conventionally, even when a charge / discharge type snubber circuit is used for an IGBT, a gate resistor having the same resistance value as that when no charge / discharge type snubber circuit is used has been used. This is a result of optimizing the cutoff capability and switching loss per chip.

However, with the recent increase in capacity, a multi-package of elements or a multi-package in which a plurality of elements are connected in series or in parallel has been developed. For this reason, when a gate resistor having a relatively large resistance value is used as in the related art,
The expected breaking ability was not always obtained, and the breaking ability was reduced.

Further, since the resistance value of the gate resistor is large,
The time from when a signal is input to the gate electrode until the start of turn-on and turn-off increases. For this reason, switching timing tends to vary among a plurality of elements connected in series or in parallel. In addition, since the minimum turn-on and turn-off times are prolonged, there is a problem that the output of the device is reduced and the switching loss is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to improve the cutoff capability of an element, speed up switching, and reduce switching loss. It is an object of the present invention to provide a power semiconductor device capable of reducing power consumption.

[0008]

In order to solve the above-mentioned problems, a power semiconductor device according to the present invention comprises an insulated gate bipolar transistor having a high voltage side main electrode, a low voltage side main electrode, and a control electrode, and the bipolar transistor. A snubber circuit having a capacitor element connected between the low voltage side main electrode and the high voltage side main electrode, and a gate resistor connected to the gate electrode of the bipolar transistor. The gate resistance Rg (Ω) Capacitance Cs of capacitor element
(NF), gate capacitance Cg (nF) and element effective area A
(/ Cm ² ) and the current Ic flowing between the high-voltage side main electrodes.
The relation of (A) is Rg <(16000 × Cs / (A × I
c) +750) / Cg is satisfied.

The power semiconductor device of the present invention has a high-voltage main electrode, a low-voltage main electrode, and a control electrode, and includes a plurality of insulating devices in which the high-voltage main electrode and the low-voltage main electrode are connected in series or in parallel. A gate-type bipolar transistor, a snubber circuit having a capacitor element connected between the low-voltage main electrode and the high-voltage main electrode of each of the bipolar transistors, and a gate resistor connected to the gate electrode of each of the bipolar transistors. The gate resistance Rg (Ω), the capacitance Cs (nF) of the capacitor element, and the gate capacitance Cg
(NF), the element effective area A (/ cm ² ), and the current Ic (A) flowing between the high-voltage-side main electrodes is Rg <(160).
It is characterized by satisfying 00 × Cs / (A × Ic) +750) / Cg.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a driving circuit of a planar IGBT according to a first embodiment of the present invention. The IGBT 11 is a planar IGBT having a gate capacitance of Cg (nF) and an element effective area of A (cm ² ).
A gate resistor 12 having a resistance value Rg (Ω) and a gate drive circuit 13 are connected in series between the gate electrode and the emitter electrode of the IGBT 11. The emitter electrode of the IGBT is grounded, and a snubber diode 14 forming a snubber circuit SNB and a snubber capacitor 1 having a capacitance Cs (nF) are provided between the collector electrode and the emitter electrode.
5 are connected in series, and the snubber diode 14 has a resistor 1
6 are connected in parallel. Further, a power supply 18 is connected to the collector electrode of the IGBT 11 via, for example, a reactor 17 constituting a load circuit.
7 is connected to a diode 19.

The gate capacitance Cg (nF) is obtained by dividing the turn-off charge of the gate by the difference between the gate voltages before and after the turn-off.

In the above configuration, an experiment was conducted to show the resistance value of the gate resistor 12, the capacitance of the snubber capacitor 15, the rate of voltage rise between the collector electrode and the emitter electrode, that is, the rate of voltage rise dVce / dt between the main electrodes shown in FIG. Got a relationship with.

In a conventional planar IGBT drive circuit, before the gate voltage falls below the gate threshold voltage Vth, the voltage between the collector electrode and the emitter electrode as a main electrode starts to rise, for example, from the N-type source layer through the channel. The expansion of the depletion layer due to the flowing electron current was suppressed, the voltage rise speed dVce / dt between the main electrodes was slow, and the turn-off loss was large.

On the other hand, in the circuit shown in FIG.
When the resistance value Rg (Ω) of the gate resistor 15 is reduced, the time from when the gate voltage starts to be reduced to when the interruption of the electron current from the gate is completed is shortened, and the voltage rise between the main electrodes is increased. Furthermore, when the resistance value of the gate resistor 15 is reduced, the electron current from the channel region of the MOS transistor is cut off, and after the gate voltage falls below the threshold voltage Vth, the voltage between the main electrodes starts to rise. In this case, the voltage rise between the main electrodes is the fastest, and the speed is the capacitance Cs of the snubber capacitor and the current Is = Cs ×
(DVcc / dt).

Further, since the supply of electrons from the emitter electrode to the bulk as the high resistance layer is completely stopped before the voltage rise between the main electrodes starts, the current Ic flowing between the main electrodes of the IGBT 11 is quickly cut off. . For this reason, IGB
Turn-off loss generated at T11ｃ (Ic × Vce) dt
Is minimized.

FIG. 2 shows that the gate capacitance Cg is 600 (nF).
When the planar IGBT having an element effective area A of 24.6 (cm ² ) is turned off from the state of the current Ic = 1000 (A), the resistance value Rg of the gate resistance, the capacitance Cs of the snubber capacitor, and the voltage rising speed The relationship of dVce / dt is shown. As is clear from FIG. 2, at a collector current of 1 (kA), as the resistance value Rg of the gate resistance decreases with respect to the snubber capacitor having a capacity of 300 (nF), the voltage rise rate dVce / dt increases. When the resistance value Rg is 8 (Ω), it becomes 2.6 (kV / μs) and is saturated.

Similarly, for a snubber capacitor having a capacitance of 660 (nF), when the resistance value Rg of the gate resistance is reduced, the voltage rise rate dVce / dt increases, and the resistance value Rg becomes 15.8 (Ω). ) To 1.35 (kV / μs) and saturates.

When the resistance value Rg of the gate resistance is reduced for a snubber capacitor having a capacitance of 136 (nF),
The voltage rising speed dVce / dt increases, and the resistance value Rg becomes 4.55 (kV / μs) at 4.5 (Ω) and saturates.

When the resistance Rg of the gate resistor is reduced for a snubber capacitor having a capacitance of 66 (nF), the voltage rising rate dVce / dt increases, and the resistance Rg becomes 3.
At 0 (Ω), it becomes 7.4 (kV / μs) and saturates.

By the way, when there is no snubber capacitor,
The resistance value Rg of the gate resistor saturates at 1.5 (Ω), and the voltage rise rate dVce / dt becomes 7.4 (kV / μs).

From the above results, the gate capacitance Cg is 600
(NF), when the planar type IGBT having the element effective area A of 24.6 (cm ² ) is turned off from the state of the current Ic = 1000 (A), the voltage rise rate dVce / d
The resistance value Rg of the gate resistance in the region where t is the maximum satisfies Expression (1).

Rg <0.022 × Cs + 1.25 (1) FIG. 3 shows a planar IGBT having a gate capacitance Cg of 600 (nF) and an element effective area A of 24.6 (cm ² ).
Is turned off from the state of the current Ic = 1000 (A), the capacitance Cs of the snubber capacitor,
It shows the relationship of turn-off loss. From the figure, the resistance value R of the gate resistance is obtained for the snubber capacitor having the same capacitance.
When g is reduced, the turn-off loss is reduced, and the turn-off loss is saturated at the minimum value when the voltage rise rate dVce / dt is saturated under the above conditions.

From the above experiment, the resistance value Rg of the gate resistance was obtained.
(Ω), capacitor capacitance Cs (nF), gate capacitance C
If the relationship between g (nF), the element effective area A (/ cm ² ), and the current Ic between the main electrodes satisfies the expression (2), the maximum voltage rise rate between the main electrodes with respect to the capacitance of the snubber capacitor. It turned out that it can be shut off by dVce / dt.

Rg <(16000 × Cs / (A × Ic) +750) / Cg (2) Here, the numerical value of the expression (2) is obtained from the oblique lines in FIG.

FIG. 4 assumes an apparatus in which, for example, 20 IGBT chips are housed in a package, and the current between the main electrodes is 1000 (A) and the element area is 2
It is a figure explaining the relation between the capacity of the snubber capacitor and the resistance value of the gate resistance in the case of 4.6 (cm ² ). Here, by using a combination of the gate resistance and the snubber capacitor satisfying the above equation (1), the turn-off loss in the element can be minimized.

FIG. 5 shows an example of a one-chip IGBT, in which the element area is 1.23 (cm ² ) and the current between the main electrodes is 50 (A). The relationship with the resistance value is shown. In FIG. 5, a region indicated by oblique lines is a region of the gate resistance Rg in which the turn-off loss can be minimized, and this region satisfies Expression (3).

Rg <8.7 × Cs + 25 (3) According to the first embodiment, the gate resistance Rg,
The relationship among the capacitance Cs of the snubber capacitor, the gate capacitance Cg, the element effective area A, and the current Ic between the main electrodes is represented by the following equation (2): Rg <(16000 × Cs / (A × Ic) +75)
0) / Cg. For this reason,
The resistance value of the gate resistor can be reduced as compared with the related art, and the stability of current interruption can be improved. Moreover, since the resistance value of the gate resistor can be reduced, the switching speed of the element can be increased, and the turn-off loss can be reduced.

The gate resistance is not limited to the case of being constituted by one resistance element, but may be constituted by connecting a plurality of resistance elements in series or in parallel. Further, these resistors may be provided on either or both of the outside and inside of the package. The method of converting the resistance value when a plurality of resistors are connected in series or in parallel to form a gate resistor is as follows. This conversion method is the same as the calculation of a series or parallel connection of ordinary resistors. That is, for the resistors connected in series, the sum of the resistance values is the resistance value of the combined resistance.

For the resistors connected in parallel, the sum of the reciprocals of the resistance values is obtained, and the reciprocal thereof is obtained to obtain the value of the combined resistance. The combined resistance of the combined resistance and the normal resistance or the combined resistance of the combined resistances is the same as the method of calculating the combined resistance of the resistors. This operation is performed recursively, and finally, the sum of all the resistance values is obtained and set as the resistance value Rg of the gate resistance.

Since the operation of a MOS gate element such as an IGBT is faster than that of a conventional bipolar drive element such as a GTO, if the capacitance of the snubber capacitor is large, most of the loss of the device is caused by the snubber including the snubber capacitor. This results in loss of the circuit. For this reason, it is important in device design to set the capacitance of the snubber capacitor within a range where the element does not break down and the loss in the element is sufficiently small.
The range of the capacitance of this snubber capacitor is determined by the current I
The value of the capacitance Cs (nF) of the snubber capacitor for c = 1000 (A) should be used as 1 (μF) or less, and particularly, the device loss is minimized at 0.6 (μF) or less. .

(Second Embodiment) FIG. 6 shows an example in which the circuit shown in FIG. 1 is applied to a single-phase inverter. In FIG. 6, the same parts as those in FIG. Only the parts will be described.

Each of the IGBT units 61 _{1 to} 61 shown in FIG.
In 1 _4, free wheel diodes 20 ₁ to 20 ₄ are connected between each other IGBT 11 ₁ to 11 ₄ of the collector electrode and the emitter electrode. IGBT11 ₁ ,
11 The _second collector electrode is connected to one end of the anode reactor 21, IGBT 11 _3, 11 to the emitter electrode ₄ is connected to one end of the anode reactor 22. A capacitor 23 and a power supply 24 are connected in parallel between the other ends of the anode reactors 21 and 22. Furthermore, between each other IGBT 11 ₁ of emitter electrode and the IGBT 11 ₄ of the collector electrode, the inductive load 25 is connected. Also, the gate resistors 12 ₁ to 12 ₄ are connected to a drive circuit (not shown).

In the single-phase inverter, the resistance value of the gate resistor can be determined in the same manner as in the first embodiment. The setting conditions of the gate resistance value shown in the first embodiment are as follows.
Place each IGBT unit 61 ₁ to 61 ₄ by a plurality as shown in FIG. 6, it is these series connections or effective when connected in parallel. The reason for this is that by setting the resistance value of each gate resistor as described above, the time from when a signal is supplied to the gate electrode of each IGBT to when the element is turned off is shortened, so that the connection is made in series or in parallel. IGB
Deviation of the current cutoff timing between each other of T units 61 ₁ is less likely to occur. This series or parallel connected another IGBT unit 61 ₂ of the mutual, between mutual IGBT unit 61 _3, and is the same between each other of the IGBT unit 61 _4. By aligning the current cutoff timings of the IGBTs, the voltage sharing is uniform between the elements connected in series, and the current sharing is uniform between the elements connected in parallel. For this reason, the margin of the device design can be narrowed.

As a result, even with a device having the same design, the output voltage can be increased, and the substantial output can be improved. Further, since the capacity of the snubber capacitor can be reduced, the loss of the element can be reduced.

The viewpoint of the capacity of the snubber capacitor which can prevent the IGBT from being destroyed and sufficiently reduce the loss in the IGBT described in the first embodiment is also effective when a plurality of IGBTs are connected in series. According to the experiment, when the capacitance Cs of the snubber capacitor is 0.2 (μF) to 0.3 (μF) with respect to the main electrode current Ic = 1000 (A), there is no bias in voltage sharing in series connection. And was effective in reducing loss.

According to the second embodiment, a plurality of IGBs
Also in the inverter constituted by T, the relationship among the resistance value Rg of the gate resistance, the capacitance Cs of the snubber capacitor, the gate capacitance Cg, the element effective area A, and the current Ic between the main electrodes satisfies the expression (2). It has established. For this reason,
The switching capability can be increased, and the switching loss can be reduced, while the cutoff capability of the element can be improved.

Furthermore, since the switching timing can be made uniform between the elements connected in series or in parallel, the output of the device can be improved.

The first and second embodiments are IGBTs.
Although the case where the present invention is applied has been described, the present invention is not limited to this. For example, an electron injection promoting transistor (IEGT;
Injection Enhanced Gate Transistor) can also be applied.

Of course, various modifications can be made without departing from the spirit of the present invention.

[0041]

As described in detail above, according to the present invention,
It is possible to provide a power semiconductor device capable of improving the cutoff capability of the element, increasing the switching speed, and reducing the switching loss.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing the operation of FIG. 1 and showing a relationship between a gate resistance value and a voltage rising speed dVce / dt between main electrodes when a collector current is fixed.

FIG. 3 is a diagram showing the operation of FIG. 1 and showing the relationship among the capacitance of the snubber capacitor, the gate resistance value, and the turn-off loss of the IGBT.

FIG. 4 is a diagram showing the operation of FIG. 1 and showing the relationship between the capacitance of the snubber capacitor and the gate resistance value when the collector current is constant.

FIG. 5 is a diagram showing the operation of FIG. 1 and showing the relationship between the capacitance of the snubber capacitor and the gate resistance value when the collector current is constant.

FIG. 6 is a circuit diagram showing a second embodiment of the present invention and showing a case where the present invention is applied to a single-phase inverter.

[Explanation of symbols]

11, 11 _{1 to} 11 ₄ ... IGBT, 12, 12 _{1 to} 12 ₄ ... gate resistance, SNB ... snubber circuit, 15, 15 ₁ to 15 ₄ ... snubber capacitor.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Ichiro Omura 1 Tokoba Toshiba-cho, Komukai-ku, Kawasaki-shi, Kanagawa F-term in the Toshiba Microelectronics Center Co., Ltd. AX02 AX06 AX12 AX55 AX56 AX64 BX16 CX00 CX07 DX09 EX04 EY01 EY05 EY10 EY12 EZ17 GX01 GX06

Claims (2)

[Claims] An insulated gate bipolar transistor having a high voltage side main electrode, a low voltage side main electrode, and a control electrode, and a snubber having a capacitor element connected between the low voltage side main electrode and the high voltage side main electrode of the bipolar transistor. A circuit, and a gate resistor connected to the gate electrode of the bipolar transistor. The gate resistance Rg (Ω), the capacitance Cs (nF) of the capacitor element, the gate capacitance Cg (nF), and the element effective area A (/ Cm ² ) and the current I flowing between the high-voltage side main electrode
The relationship of c (A) is Rg <(16000 × Cs / (A × Ic) +750) /
A power semiconductor device satisfying Cg. 2. A plurality of insulated gate bipolar transistors having a high voltage side main electrode, a low voltage side main electrode, and a control electrode, wherein the high voltage side main electrode and the low voltage side main electrode are connected in series or in parallel. A snubber circuit having a capacitor element connected between the low-voltage main electrode and the high-voltage main electrode of the bipolar transistor; and a gate resistor connected to the gate electrode of each of the bipolar transistors. The gate resistance Rg (Ω ), The capacitance Cs (nF) of the capacitor element, the gate capacitance Cg (nF), the element effective area A (/ cm ² ), and the current I flowing between the high-voltage side main electrodes.
The relationship of c (A) is Rg <(16000 × Cs / (A × Ic) +750) /
A power semiconductor device satisfying Cg.