JP2001274159A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable improvement of a step difference in surface between a wiring layer and insulating film, even when the amount of recess is made large in order to secure residual thickness of a barrier layer covering the surface of the wiring layer. SOLUTION: A carbon film 15 is formed on a silicon oxide film 14 on an Si substrate 11. Grooves 16 are formed in the silicon oxide and carbon films 14 ands 15. A first TaN film 17 is formed on the carbon film 15 and along the surfaces of the grooves 16. A Cu wiring layer 18 is formed on the first TaN film 17 so as to embed the grooves 16. The surface of the Cu layer 18 is planarized to embed the first TaN layer 17 and Cu layer 18 into the grooves. The surface of the Cu layer 18 is retreated from areas of the surface of the layer 18 other than areas for formation of the wiring layer 18 to form recesses 20. A second TaN layer 19 is formed on the first layer 17 and the Cu layer 18. The surface of the second layer 19 is planarized to cause the carbon film 15 to be exposed. The carbon film 15 is selectively removed to expose the silicon oxide film 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring technology, and more particularly to a method for manufacturing a semiconductor device in which a wiring layer is entirely covered with a barrier metal.

[0002]

2. Description of the Related Art Since Cu serves as a lifetime killer for silicon devices, it is essential to suppress the diffusion of Cu into an interlayer film in order to apply Cu as an LSI wiring.
In addition, the wiring upper barrier layer is required to have a function of preventing the Cu wiring surface from being oxidized during the process.

Conventionally, a silicon nitride layer has been used as an upper barrier layer of a Cu wiring, but there is a problem that the capacitance between wirings is increased due to a high dielectric constant. In order to solve this problem, it has been proposed to form a barrier layer on the upper surface of the Cu wiring, which is the same as or equivalent to that used on the side and bottom surfaces, to completely surround the wiring.

As a method of forming this structure, after a Cu damascene wiring is formed, a so-called recess etching process is performed to retreat the surface of the Cu wiring from the surface of the insulating film. A method has been devised in which the barrier layer is left only on the wiring by mechanical polishing (CMP).

In order to suppress the capacitance between wirings, it is desirable to reduce the amount of recess. In this case, however, the polishing rate of chemical mechanical polishing (CMP) varies in the plane and dishing causes a sufficient pattern in the entire surface of the wafer. It is difficult to leave a barrier layer having a thickness.

On the other hand, although the capacitance between wirings is increased, the chemical mechanical polishing (CMP)
Although the above-mentioned problem can be solved, since the level difference from the surface of the insulating film is large even after the formation of the barrier layer, there arises a problem that a sufficient coverage cannot be obtained when an oxide film or the like is formed in a subsequent step.

By the way, various attempts have been made to cover an upper portion of a wiring formed by a damascene process with a barrier metal. The most common method is metal film deposition by PVD or CVD. However, in order to leave the barrier metal above the wiring, a so-called “recess process” is used, and it is necessary to deposit a film in a concave portion having a wiring surface at the bottom, and the step coverage of PVD or CVD is not sufficient. If it is enough, the function of the barrier metal cannot be sufficiently performed.

The steps of forming a barrier metal on the upper part of the wiring include wiring CMP, wiring recess, cleaning (if necessary), formation of barrier metal, extra barrier metal CMP, and (as needed) CMP. Follow the process sequence. Here, a wet process other than the barrier metal formation is generally performed, and if the barrier metal formation process can be performed by a wet process, there is a possibility that a series of processes can all be performed continuously in a wet apparatus. As described above, the wet plating method is convenient because the step coverage is good and the continuity of the process can be ensured.

Therefore, electroless plating has been attempted as a wet barrier metal forming method. This method seems to be promising at first glance because a metal film can be selectively formed on the divided wiring, but it has great limitations. The principle of electroless plating limits the types of metal that can form a film on the surface of a metal wiring. Actually, when a barrier metal is formed on the upper portion of the pot wiring formed by the damascene method, an appropriate metal film cannot be formed.

On the other hand, in electrolytic plating, metal ions are electrically deposited on the surface of the conductive film. However, in the electroplating, a potential for plating must be applied to the wiring layer. In a normal process, the wiring is cut off at the time of forming the metal on the wiring, so that it is impossible to flow a plating current.

[0011]

As described above, if the recess amount is reduced in order to form a recess for burying a barrier metal layer on a wiring layer, a barrier metal layer having a sufficient thickness remains. There was a problem that it was difficult. If the recess amount is increased, a step difference from the surface of the insulating film after the formation of the barrier metal layer is large, so that sufficient coverage cannot be obtained when an oxide film or the like is formed in a subsequent process, and the capacitance between wirings increases accordingly. There were problems such as getting lost.

As a method of forming a barrier metal layer formed on a wiring layer, it is desired to use an electrolytic plating method. However, since a conductive layer is not formed on an insulating layer, a plating current is applied. Therefore, there is a problem that the barrier metal layer cannot be formed by the electrolytic plating method.

An object of the present invention is to improve the step between the wiring surface and the insulating film surface even when the recess amount is increased in order to secure the remaining film thickness of the barrier layer covering the surface of the wiring layer, and to improve the step in the post-process. An object of the present invention is to provide a method of manufacturing a semiconductor device capable of avoiding a problem caused by a step such as insufficient coverage of an insulating film and suppressing an increase in capacitance between wirings.

Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming a barrier metal covering the surface of a wiring layer by an electrolytic plating method.

[0015]

Means for Solving the Problems [Configuration] The present invention is configured as follows to achieve the above object.

(1) A method of manufacturing a semiconductor device according to the present invention (claim 1) includes a step of forming an intermediate layer on an insulating layer on a semiconductor substrate, and a step of forming a groove in the insulating layer and the intermediate layer. Forming a first barrier metal layer along the surface of the intermediate layer and the groove, depositing a wiring layer on the first barrier metal layer so as to fill the groove, Performing a planarization process on the surface of the layer to bury and form a first barrier metal layer and a wiring layer in the groove; and forming a recess by retreating the surface of the wiring layer from the surface of the insulating layer. Forming a second barrier metal layer along the surface of the intermediate layer and the concave portion;
Performing a planarization process on the surface of the barrier metal layer to expose the surface of the intermediate layer; and selectively removing the intermediate layer to expose the surface of the insulating layer. Features.

Preferred embodiments of the present invention are described below.
After the removal of the intermediate layer, chemical mechanical polishing is performed under conditions where the second barrier metal layer is polished. The intermediate layer is at least one selected from a carbon film, a silicon nitride film, and a silicon oxide film. (2) The method for manufacturing a semiconductor device of the present invention (claim 4)
Forming a groove in the insulating layer on the semiconductor substrate, forming a first barrier metal layer along the surface of the insulating layer and the groove, and filling the groove on the first barrier metal layer Forming a wiring layer, and performing a flattening process on the surface of the wiring layer at least in a range where the first barrier metal layer can be continuously left on the interlayer insulating film; Forming a recess by recessing the surface of the wiring layer in the first step;
Forming a second barrier metal layer on the barrier metal layer and the wiring layer by electrolytic plating using the first barrier metal layer remaining on the insulating layer; Flattening the surface of the first barrier metal layer until the surface of the insulating layer is exposed.

(3) A method of manufacturing a semiconductor device according to the present invention (claim 5) includes a step of forming a conductive layer on an insulating layer on a semiconductor substrate, and a step of forming a groove in the conductive layer and the insulating layer. Forming a first barrier metal layer along the surface of the conductive layer and the groove; and forming a wiring layer on the first barrier metal layer so as to fill the groove. Performing a flattening process on the surface of the wiring layer to the extent that the conductive layer can be continuously left on the insulating layer, forming a wiring layer in the trench, and forming the surface of the conductive layer on the insulating layer. Forming a recess by recessing from the surface of the insulating layer; and forming a second barrier metal layer on the conductive layer and the wiring layer by an electrolytic plating method using a conductive layer remaining on the insulating layer. And a second barrier metal layer and a conductive layer The surface, characterized in that it comprises a planarizing until the surface of the insulating layer is exposed.

In the two inventions described in (2) and (3), it is preferable that the wiring layer is formed by an electrolytic plating method.

[Operation] The present invention has the following operation and effects by the above configuration.

In the step of performing a recess etching process to retreat the surface of the wiring layer from the surface of the insulating film, forming a barrier layer and leaving the barrier layer only on the wiring by chemical mechanical polishing, the remaining film thickness of the barrier layer Even if the recess amount is increased in order to ensure that the intermediate layer that can be removed by a different process from the insulating film is formed in advance on the insulating film surface and removed after chemical mechanical polishing,
It is possible to improve the level difference between the wiring surface and the insulating film surface and to avoid a problem caused by a level difference such as insufficient coverage of the insulating film in a later step. It is also possible to suppress an increase in the capacitance between wirings.

After the removal of the intermediate layer, chemical mechanical polishing is performed under the condition that the second barrier metal layer is polished.
The second barrier metal layer formed on the side wall of the recess can be removed. Since the chemical mechanical polishing time is shorter than the normal chemical mechanical polishing time, it does not affect the second barrier metal layer on the wiring layer.

Also, in the step of flattening the wiring layer, the barrier metal layer or the conductive layer covering the side of the wiring is continuously left on the insulating layer, so that the barrier on the wiring can be formed at a low cost and at a high speed by an electroplating process. Metal formation is possible, and the types of metal that can be formed are extremely wide as compared with the electroless method.
Further, since all the wiring forming processes by the damascene method can be performed by a wet method, processing can be continuously performed by the same apparatus, and a quick, inexpensive, and simple process can be realized.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a process sectional view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention. First, as shown in FIG. 1A, after a thermal oxide film 12 is formed to a thickness of 100 nm on a Si substrate (semiconductor substrate) 11, a silicon nitride film 13 is formed to a thickness of 30 nm by a CVD method.
m, a silicon oxide film 14 is deposited to a thickness of 400 nm by a CVD method. Carbon film (intermediate layer) on silicon oxide film 14
15 is deposited to a thickness of 100 nm.

Next, as shown in FIG. 1B, after patterning the carbon film 15 by ordinary PEP and etching, the carbon film 15 is
A groove 16 is formed by E. The groove 16 has a length of 3 m, L /
This is a pattern in which both ends of the wiring are connected to electrode pads when S = 0.2 / 0.2 μm.

Next, as shown in FIG. 1 (c), a first TaN film (first
Is formed. Further, the first Ta
After depositing a 200 nm-thick Cu film on the N film 17, a Cu film is further formed by an electrolytic plating method using copper sulfate, and a Cu wiring layer 18 is deposited so as to fill the trench 16. Next, as shown in FIG. 1D, the first Ta
Using the N film 17 as an etching stopper, the Cu wiring layer 1
8 is subjected to a CMP process to form a first TaN film 1.
7 is exposed.

Then, as shown in FIG. 1 (e), the surface of the Cu wiring layer 18 is recessed by performing a recess process using an acid while rotating the wafer at a high speed by a spin etcher. To form After recess processing,
Rinse with pure water for 5 minutes and then dry. Cu wiring layer 18
Was 150 nm, and the cross-sectional shape of the sample was good.

Then, as shown in FIG. 1F, a second TaN film 20 is formed on the entire surface by sputtering to a thickness of 50 nm.
Form. Then, as shown in FIG. 1G, a second layer on the carbon film 15 is formed by a chemical mechanical polishing (CMP) process.
The TaN film 20 and the first TaN film 17 are removed to expose the carbon film 15 on the field over the entire surface of the wafer.
Since the recess amount of the Cu wiring layer 18 is larger than the thickness of the second TaN film 20, the second T
The aN film 20 had a sufficient thickness remaining on the entire surface of the wafer.

After that, as shown in FIG. 1H, the carbon film 15 is removed by CDE using O ₂ gas.
In order to remove the remaining portion of the TaN film formed on the side wall of the concave portion, the TaN film was polished for 10 seconds by a slurry used for chemical mechanical polishing (CMP). Since this process is shorter in time than ordinary chemical mechanical polishing (CMP), only the remaining TaN film is removed, and the TaN film on the Cu wiring is not affected at all.

In this embodiment, the chemical mechanical polishing (CMP) before the recess processing is stopped at the stage where the TaN film 17 is exposed, but the recess etching processing may be performed after the silicon oxide film 14 is exposed. .

After measuring the wiring resistance of the wafer thus formed with a blow bar, an acceleration test was performed in which the wafer was allowed to stand for 1 hour in an oven at 300 ° C. in an air atmosphere. After the acceleration test, when the resistance of the Cu wiring was measured again by the blow bar, there was no change before and after the acceleration test.
It was confirmed that the barrier layer functioned as an antioxidant layer. After forming an insulating film by coating on a wafer on which a large number of wiring patterns were formed, annealing was performed at 450 ° C. for 60 hours. When the Cu concentration was measured by dissolving the applied insulating film, there was no significant difference between the presence and absence of annealing. This confirmed that the upper barrier layer functions as a Cu diffusion preventing layer.

When a silicon oxide film was formed on a wafer prepared in the same manner to form an upper wiring, a desired performance could be obtained without any problem by a conventional process.

As the intermediate layer, a silicon nitride film, a silicon oxide film or the like can be used in addition to the carbon film.

[Second Embodiment] FIG. 2 is a process sectional view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention. First, as shown in FIG. 2A, after a thermal oxide film 12 is formed to a thickness of 100 nm on a Si substrate (semiconductor substrate) 11, a silicon nitride film 13 is formed to a thickness of 30 nm by a CVD method.
m, and further, the low dielectric constant insulating film 24 is
Deposited. The low dielectric constant insulating film 24 contains a large number of methyl groups in the skeleton of silicon oxide, and is resistant to hydrofluoric acid. A silicon oxide film (intermediate layer) 25 is deposited to a thickness of 100 nm on the low dielectric constant insulating film 24 by a CVD method.

Next, as shown in FIG. 2B, a groove 16 is formed in the silicon oxide film 25 and the low dielectric constant insulating layer 24 by ordinary PEP and etching. The groove 16 has a length of 3 m, L / S = 0.2 / 0.2 μm, and is a pattern in which both ends of the wiring are connected to the electrode pads.

Next, as shown in FIG. 2C, a 20 nm-thick first TaN film (first
Is formed. Further, the first Ta
After depositing a 200 nm-thick Cu film on the N film 17, a Cu film is formed by electrolytic plating using copper sulfate, and a Cu wiring layer 18 is deposited so as to fill the trench 16. Next, as shown in FIG. 2D, the surface of the Cu wiring layer 18 is subjected to a CMP process using the first TaN film 17 as an etching stopper to expose the first TaN film 17. Then, the silicon oxide film 25 is exposed by another CMP process.

Next, as shown in FIG. 2E, the wafer is subjected to a recess treatment using an acid while rotating the wafer at a high speed by a spin etcher, so that the surface of the Cu wiring layer 18 is receded, and the recess 19 is formed. To form After recess processing,
Rinse with pure water for 5 minutes and then dry. Cu wiring layer 18
Was 150 nm, and the cross-sectional shape of the sample was good.

Then, as shown in FIG. 2F, a second TaN film 20 is formed on the entire surface by sputtering to a thickness of 50 nm.
Form. Then, as shown in FIG. 2G, the second TaN film 20 on the silicon oxide film 25 is removed by a chemical mechanical polishing (CMP) process, and the silicon oxide film 25 on the field is exposed on the entire surface of the wafer. Let it. Since the recess amount of the Cu wiring layer 18 is larger than the thickness of the second TaN film 20, the second TaN film 20 has a sufficient thickness remaining on the entire surface of the wafer above the Cu wiring layer 18.

Next, as shown in FIG. 2H, the silicon oxide film 25 is removed with hydrofluoric acid. In order to remove the remaining portion of the TaN film formed on the side wall of the concave portion,
Polishing was performed for 10 seconds with a slurry used for chemical mechanical polishing (CMP) of the N film. Since this process is shorter in time than ordinary chemical mechanical polishing (CMP), only the remaining TaN film is removed and the second process on the Cu wiring layer 18 is performed.
No effect was observed on the TaN film 20 of FIG.

As a result of the same test as in the first embodiment, good oxidation resistance, Cu barrier properties, and consistency with the subsequent steps were confirmed.

[Third Embodiment] In this embodiment, a barrier metal formed under a wiring during a process is used as a conductor layer for electrolytic plating. In this embodiment, a copper wiring is used. FIGS. 3 and 4 are process cross-sectional views showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention.

First, as shown in FIG. 3A, a groove (450 nm deep) is formed in the interlayer insulating film 32 formed on the Si substrate 31.
m) Form the hole 33. Next, as shown in FIG. 3B, a TaN (tantalum nitride) film (first barrier metal layer) 34 having a thickness of 20 nm is formed as a barrier layer by a sputtering method. Further, after a sputtered copper film 35 having a thickness of 100 nm is formed by a sputtering method, an electrolytic plating copper film 36 having a thickness of 900 nm is formed using the sputtered copper film 35 as a conductive layer.
Hereinafter, the sputtered copper film 35 and the electrolytic plated copper film 36 are referred to as copper wiring layers 35 and 36.

Next, as shown in FIG.
The extra copper wiring layers 35 and 36 on the TaN film 34
(Damascene method). In the slurry in the CMP step, silicon oxide is used as abrasive grains and ammonium persulfate or the like is added. In this CMP process, the removal rate of TaN is one tenth slower than that of copper, so that the removal of the sputtered copper film 35 and the electrolytic plating copper film 36 is completed with the TaN film 34 remaining.

Next, as shown in FIG. 4D, only copper is selectively etched by recess using a mixed solution of hydrochloric acid and hydrogen peroxide, so that the surfaces of the copper wiring layers 35 and 36 are about 100 nm.
Retreat.

In this state, the TaN film 34 remaining between the copper wiring layers 35 and 36 is used as a conductive layer, and a negative potential is applied from the vicinity of the outer periphery of the wafer while the aqueous solution of ruthenium chloride pentahydrate is used. Electroplating is performed with a plating solution. A ruthenium plate was used as the anode in the plating solution. By electrolytic plating, as shown in FIG.
A ruthenium film (second barrier metal layer) 37 having a thickness of 50 nm is uniformly formed on the wafer surface. Ruthenium is known to effectively function as a copper diffusion barrier (barrier film). By forming this on the copper wiring layers 35 and 36, it is possible to prevent thermal diffusion of copper to the interlayer insulating film 32. Can be done.

As shown in FIG. 4F, of the formed ruthenium film 37 and the TaN film 34, the one on the interlayer insulating film 32 is thereafter removed by CMP, so that the lower part and the side wall are removed by the TaN film 34. Then, copper wirings 35 and 36 whose upper portions are surrounded by a ruthenium film 37 can be formed.

The barrier performance can be further improved by subjecting the surface and the inside of the ruthenium to nitriding treatment, boring treatment, carbonizing treatment and silicidation treatment with nitrogen plasma or the like as necessary. Since ruthenium oxide is conductive, it can be oxidized.

[Fourth Embodiment] FIGS. 5 and 6 are sectional views showing the steps of manufacturing a semiconductor device according to a fourth embodiment of the present invention.

First, as shown in FIG. 5A, prior to forming a groove (depth: 1400 nm) in the interlayer insulating film, a conductive hard mask having a thickness of 8
A 0 nm tungsten film is formed. Tungsten film 4
After the formation of 1, a groove pattern is formed in a photoresist (not shown) by a normal lithography method, and the groove / hole 33 is formed in the tungsten 41 and the interlayer insulating film 32 by a dry etching method using this as a mask. If the photoresist is lost during the dry etching, a groove is formed in the interlayer insulating film using the patterned tungsten 41 as a mask. After the dry etching, if the photoresist remains, the photoresist is removed.

Next, as shown in FIG. 5B, a 50 nm-thick TiN (titanium nitride) film 54 is formed as a barrier layer by a sputtering method. Further, after forming a sputtered copper film 35 having a thickness of 200 nm by a sputtering method,
Electroconductive plated copper film 3 having a film thickness of 1700 nm using 5 as a conductive layer
6 is formed.

Next, as shown in FIG.
As a result, the extra sputtered copper film 35 and the electrolytic plated copper film 36 on the TiN film 54 are removed (damascene method). In the slurry in the CMP step, silicon oxide is used as abrasive grains and ammonium persulfate or the like is added. In this CMP process, the removal rate of tungsten is as slow as 1/20 of that of copper, so that the removal of the sputtered copper film 35 and the electrolytic plating copper film 36 is completed with the tungsten film 41 remaining. Here, a part of the TiN film may remain.

Next, as shown in FIG. 6D, only a portion of copper is selectively recessed and etched using a mixed solution of hydrochloric acid and hydrogen peroxide solution to form a surface of the sputtered copper film 35 and the electroplated copper film 36. Is retracted by about 300 nm.

In this state, the tungsten film 41 remaining between the copper wirings is used as a conductive layer, and electrolytic plating is performed with an aqueous solution of rhodium sulfate while applying a negative potential from around the outer periphery of the wafer. A platinum plate was used as the anode in the plating solution. As a result, as shown in FIG. 6E, a rhodium film 57 having a thickness of 50 nm is uniformly formed on the wafer surface. Rhodium is known to function effectively as a copper diffusion barrier (barrier film). By forming this over copper wiring, it is possible to prevent copper from thermally diffusing into an interlayer insulating film.

Next, as shown in FIG. 6F, the rhodium film 57, the tungsten film 41 and the TiN
By removing the film 54 by CMP, the lower and side walls are made of Ti.
A copper wiring in which the N film 54 and the upper part are surrounded by the rhodium film 57 can be formed.

The barrier performance can be further improved by subjecting the surface and the inside of the rhodium to nitriding treatment, boring treatment, carbonizing treatment and silicidation treatment with nitrogen plasma or the like as necessary.

The present invention is not limited to the above embodiment, but can be implemented in various modifications without departing from the scope of the invention.

[0058]

As described above, according to the present invention, recess etching is performed to retreat the surface of the wiring layer from the surface of the insulating film, and a barrier layer is formed. In the step of leaving the layer,
Even when the recess amount is increased to secure the remaining film thickness of the barrier layer, an intermediate layer that can be removed by a process different from that of the insulating film is formed in advance on the insulating film surface, and after the chemical mechanical polishing, By removing, it is possible to improve a step between the wiring surface and the insulating film surface and to avoid a problem caused by a step such as insufficient covering of the insulating film in a later step.

Also, in the step of flattening the wiring layer, the barrier metal layer or the conductive layer covering the side portions of the wiring is continuously left on the insulating layer, so that the barrier on the wiring can be formed inexpensively at a high speed by an electroplating process. Metal formation is possible, and the types of metal that can be formed are extremely wide as compared with the electroless method.
Further, since all the wiring forming processes by the damascene method can be performed by a wet method, processing can be continuously performed by the same apparatus, and a quick, inexpensive and simple process can be realized.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view showing a manufacturing process of a semiconductor device according to a first embodiment.

FIG. 2 is a process cross-sectional view showing a manufacturing process of a semiconductor device according to a second embodiment.

FIG. 3 is a process cross-sectional view showing a manufacturing process of a semiconductor device according to a third embodiment.

FIG. 4 is a process sectional view illustrating a manufacturing process of a semiconductor device according to a third embodiment;

FIG. 5 is a process cross-sectional view showing a manufacturing process of a semiconductor device according to a fourth embodiment.

FIG. 6 is a process cross-sectional view illustrating a manufacturing process of a semiconductor device according to a fourth embodiment.

[Explanation of symbols]

 Reference Signs List 11 ... Si substrate (semiconductor substrate) 12 ... Thermal oxide film 13 ... Silicon nitride film 14 ... Silicon oxide film 15 ... Carbon film (intermediate layer) 16 ... Groove 17 ... TaN film (first barrier metal layer) 18 ... Cu wiring Layer 19 recess 20 second TaN film (second barrier metal layer) 31 Si substrate (semiconductor substrate) 32 interlayer insulating film 33 groove / hole 34 TaN film (first barrier metal layer) 35 ... sputtered copper film 36 ... electroplated copper film 37 ... ruthenium film (second barrier metal layer) 41 ... tungsten film 54 ... TiN film 57 ... rhodium film

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Naofumi Kaneko 8th Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture F-term in the Toshiba Yokohama Office (reference) 5F033 HH07 HH11 HH32 HH33 MM01 MM05 MM12 MM13 PP15 PP27 PP33 QQ08 QQ09 QQ13 QQ19 QQ48 QQ49 RR04 RR06 RR12 SS11 SS21 XX20 XX24 XX33

Claims (6)

[Claims] A step of forming an intermediate layer on an insulating layer on a semiconductor substrate; a step of forming a groove in the insulating layer and the intermediate layer; and a first barrier metal along a surface of the intermediate layer and the groove. A step of forming a layer, a step of depositing a wiring layer on the first barrier metal layer so as to fill the groove, and a step of performing a planarization process on the surface of the wiring layer, Burying and forming a first barrier metal layer and a wiring layer; recessing the surface of the wiring layer from the surface of the insulating layer to form a recess; and forming a second portion along the surface of the intermediate layer and the recess. Forming a barrier metal layer, performing a planarization process on the surface of the second barrier metal layer to expose the surface of the intermediate layer, and selectively removing the intermediate layer to form the insulating layer. Exposing the surface of the layer. The method of manufacturing a semiconductor device to be. 2. The method of manufacturing a semiconductor device according to claim 1, wherein after the removal of the intermediate layer, chemical mechanical polishing is performed under a condition that the second barrier metal layer is polished. 3. The method according to claim 1, wherein the intermediate layer is at least one selected from a carbon film, a silicon nitride film, and a silicon oxide film. A step of forming a groove in the insulating layer on the semiconductor substrate; a step of forming a first barrier metal layer along the surface of the insulating layer and the groove; Depositing a wiring layer so as to fill the trench, and planarizing the surface of the wiring layer at least as far as the first barrier metal layer can be continuously left on the interlayer insulating film. Performing a step of burying a wiring layer in the groove; a step of recessing the surface of the wiring layer to form a recess; a step of forming a recess on the first barrier metal layer and the wiring layer; Forming a second barrier metal layer by an electrolytic plating method using the remaining first barrier metal layer; and forming a surface of the second barrier metal layer and the first barrier metal layer on the surface of the insulating layer. Planarizing until exposed. The method of manufacturing a semiconductor device according to claim and. 5. A step of forming a conductive layer on an insulating layer on a semiconductor substrate, a step of forming a groove in the conductive layer and the insulating layer, and a first barrier metal along a surface of the conductive layer and the groove. A step of forming a layer, a step of forming a wiring layer on the first barrier metal layer so as to fill the trench, at least as far as the conductive layer can be continuously left on the insulating layer. Performing a planarization process on the surface of the wiring layer to bury the wiring layer in the groove; and forming a recess by retreating the surface of the conductive layer from the surface of the insulating layer. Forming a second barrier metal layer on the conductive layer and the wiring layer by an electrolytic plating method using a conductive layer remaining on the insulating layer; and forming a surface of the second barrier metal layer and the conductive layer on the conductive layer and the wiring layer. , Flatten until the surface of the insulating layer is exposed A method of manufacturing a semiconductor device. 6. A method according to claim 4, wherein said wiring layer is formed by an electrolytic plating method.