JP2001273165A5 - - Google Patents

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Publication number
JP2001273165A5
JP2001273165A5 JP2001031392A JP2001031392A JP2001273165A5 JP 2001273165 A5 JP2001273165 A5 JP 2001273165A5 JP 2001031392 A JP2001031392 A JP 2001031392A JP 2001031392 A JP2001031392 A JP 2001031392A JP 2001273165 A5 JP2001273165 A5 JP 2001273165A5
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JP
Japan
Prior art keywords
microcode
state
microinstruction
emulated
reference model
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Withdrawn
Application number
JP2001031392A
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English (en)
Japanese (ja)
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JP2001273165A (ja
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Publication date
Priority claimed from US09/502,366 external-priority patent/US6625759B1/en
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Publication of JP2001273165A publication Critical patent/JP2001273165A/ja
Publication of JP2001273165A5 publication Critical patent/JP2001273165A5/ja
Withdrawn legal-status Critical Current

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JP2001031392A 2000-02-18 2001-02-07 中央処理装置の挙動モデルの細粒度妥当性を検証するための方法および装置 Withdrawn JP2001273165A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/502366 2000-02-18
US09/502,366 US6625759B1 (en) 2000-02-18 2000-02-18 Method and apparatus for verifying the fine-grained correctness of a behavioral model of a central processor unit

Publications (2)

Publication Number Publication Date
JP2001273165A JP2001273165A (ja) 2001-10-05
JP2001273165A5 true JP2001273165A5 (enExample) 2005-07-21

Family

ID=23997483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001031392A Withdrawn JP2001273165A (ja) 2000-02-18 2001-02-07 中央処理装置の挙動モデルの細粒度妥当性を検証するための方法および装置

Country Status (2)

Country Link
US (2) US6625759B1 (enExample)
JP (1) JP2001273165A (enExample)

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US7447621B1 (en) * 2003-09-29 2008-11-04 Sun Microsystems, Inc. PLI-less co-simulation of ISS-based verification systems in hardware simulators
US7606695B1 (en) * 2003-09-30 2009-10-20 Sun Microsystems, Inc. Self-checking simulations using dynamic data loading
US7613950B2 (en) * 2004-02-27 2009-11-03 Hewlett-Packard Development Company, L.P. Detecting floating point hardware failures
US20050262399A1 (en) * 2004-05-05 2005-11-24 Brown Adam C Aggregating and prioritizing failure signatures by a parsing program
US7373550B2 (en) * 2005-02-03 2008-05-13 Arm Limited Generation of a computer program to test for correct operation of a data processing apparatus
US8983823B1 (en) 2005-12-29 2015-03-17 The Mathworks, Inc. Verification harness for automatically generating a text-based representation of a graphical model
US9317628B1 (en) 2005-12-29 2016-04-19 The Mathworks, Inc. Automatic comparison and performance analysis between different implementations
US8041554B1 (en) * 2007-06-06 2011-10-18 Rockwell Collins, Inc. Method and system for the development of high-assurance microcode
US7908518B2 (en) * 2008-02-08 2011-03-15 International Business Machines Corporation Method, system and computer program product for failure analysis implementing automated comparison of multiple reference models
US8423968B2 (en) * 2008-02-11 2013-04-16 International Business Machines Corporation Template-based vertical microcode instruction trace generation
US8046639B1 (en) * 2010-07-29 2011-10-25 Oracle International Corporation Cycle accurate fault log modeling for a digital system
US20120079248A1 (en) * 2010-09-24 2012-03-29 Combs Jonathan D Aliased Parameter Passing Between Microcode Callers and Microcode Subroutines
US9582410B2 (en) * 2010-10-27 2017-02-28 International Business Machines Corporation Testing software on a computer system
US10177915B2 (en) * 2013-03-15 2019-01-08 Ologn Technologies Ag Systems, methods and apparatuses for device attestation based on speed of computation
US9329865B2 (en) 2013-06-11 2016-05-03 Intel Corporation Context control and parameter passing within microcode based instruction routines
EP3493051A1 (en) * 2017-11-30 2019-06-05 The MathWorks, Inc. System and methods for evaluating compliance of implementation code with a software architecture specification
DE102018003142A1 (de) 2017-12-13 2019-06-13 The Mathworks, Inc. Automatische Einstellung von Multitasking-Konfigurationen für ein Codeprüfsystem
US11120185B2 (en) * 2018-11-29 2021-09-14 International Business Machines Corporation Hardware incremental model checking verification

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JPH06105432B2 (ja) * 1989-06-01 1994-12-21 三菱電機株式会社 マイクロプロセッサ
US5438673A (en) * 1990-08-17 1995-08-01 Cray Research, Inc. Automatic interface for CPU real machine and logic simulator diagnostics
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KR100492007B1 (ko) * 1997-12-30 2005-08-29 매그나칩 반도체 유한회사 내부상태궤적비교에의한칩검증방법
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