JP2001264116A - Signal processing circuit of encoder and signal processing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To remove jitter which occurs when the detected signal of an encoder is made higher resolution using an electric interpolation circuit. SOLUTION: There are provided a first RS flip-flop 1 where A-phase signal is inputted in S while B-phase signal is inputted in R, a second RS flip-flop 2 where an inversion signal of B-phase is inputted in S while that of A-phase is inputted in R, a third RS flip-flop, a fourth RS flip-flop 4, a first AND circuit 5 where a logical product between a first RS flip-flop output signal and a second RS flip-flop output signal is provided, and a second AND circuit 6 where a logical product between a third RS flip-flop output signal an a fourth RS flip- flop output signal is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to signal processing of an encoder which outputs two-phase rectangular wave signals having phases different from each other by 90 degrees with respect to a displacement of a detection object, and more particularly to an edge of the rectangular wave signal. The present invention relates to a circuit for removing jitter generated in a section and a signal processing method thereof.

[0002]

2. Description of the Related Art As a noise removal circuit for an encoder signal, there is a method using a delay filter (conventional example 1). FIG. 3 is a block diagram of a conventional noise removal circuit. The input signal is sampled at the rising edge of the clock. In a three-input AND or three-input OR gate unit, three consecutive
It detects if the encoder signal changes during the clock. That is, these gate section outputs are output only when the same state is maintained for the rising edges of three clocks. As a result, instantaneous noise spikes generated at the edge and jitter shorter than two clock cycles are removed. Another conventional example is disclosed in Japanese Patent Application Laid-Open No. 9-25751.
6 (conventional example 2). FIG. 7 shows the connection diagram. FIG.
FIG. 7 is a waveform diagram for explaining the operation. One phase PA of a two-phase rectangular wave signal having a jitter at an edge is supplied to a D input terminal of a D flip-flop, and the other phase PB is a peak hold circuit composed of a diode D1, a capacitor C1, and a resistor R3. To supply. In this peak hold circuit, the jitter at the edge portion is removed, and the waveform becomes as shown by PD in FIG. This output signal PD is passed through the waveform shaping circuit to the above D signal.
It is supplied to the clock input of the flip-flop circuit. The signal Q in the direction of displacement from the output of the D flip-flop circuit
From the output of the waveform shaping circuit c, a signal PE having a displacement amount that does not include jitter can be extracted.

[0003]

In order to increase the resolution of the encoder signal, an electric interpolation circuit is used. The interpolation circuit converts a two-phase sine wave signal obtained from the sensor signal into a digital signal having a certain number of bits. FIG. 4 shows the relationship between the two-phase sine wave signals SA and SB input to the interpolation circuit and the dizil signal outputs B0 to B7. FIG. 5 is an enlarged view of the least significant bit B0 of the digital signal output shown in FIG. 4 and the bit B1 immediately above the least significant bit B0 in the horizontal axis direction. Since the sensor signal is a signal having a certain S / N, as shown in FIG. 5, in the digital signal output, the H / L of the signal has an uncertain portion at the bit switching point. On the other hand, to facilitate signal processing and reduce the number of output signals,
Using B0 and B1, conversion to a two-phase rectangular wave signal is also performed. Exclusive O of B0 and B1
By taking R, the A signal of the two-phase rectangular wave signal is converted to B signal
By using 1, a B signal having a phase different from that of the A signal by 90 degrees is generated. FIG. 6 shows the generated A signal and B signal. The uncertain portion of the digital signal appears at the edge of the two-phase rectangular wave signal (A signal, B signal) as shown in FIG. The jitter portion generated due to the above-described cause has a characteristic that the longer the period of the sensor signal becomes, the longer it becomes, and there is a problem that it cannot be completely removed by the delay filter of the first conventional example. In the second conventional example, jitter is removed by using a peak hold circuit, and a time for discharging a capacitor used in this circuit is required. If the discharge time is lengthened, high-frequency input signals cannot be handled, and if the discharge time is shortened, the peak hold characteristics deteriorate, and there is a problem that input signals in a wide frequency range cannot be handled. The present invention has been made in view of such a problem, and a jitter removing circuit and a signal processing method thereof capable of handling an input signal in a wide frequency range that cannot be handled by a jitter removing method using a delay filter or a peak hold circuit. The purpose is to provide. In particular, 9
When a detection signal having a phase difference of 0 degree is made to have a high resolution by using an electric interpolation circuit, jitter can be removed while maintaining the phase difference of the detection signal at 90 degrees.

[0004]

According to a first aspect of the present invention, there is provided an encoder for outputting two-phase rectangular wave signals having phases different from each other by 90 degrees with respect to a displacement of a detection object. In a signal processing circuit of an encoder for removing jitter generated at an edge portion of a rectangular wave signal,
Phase square wave signal and the inverted signal of the square wave signal
An AND signal of an output of two sets of RS flip-flops, which is an input signal of a flip-flop, an output of two sets of RS flip-flops out of the outputs of the four sets of RS flip-flops, , And outputs two-phase rectangular wave signals having a phase difference of 90 degrees without jitter at the edge portion.
Further, according to the invention of claim 2, the displacement of the detection object is
In the signal processing circuit of the encoder for removing the jitter generated at the edges of the A-phase and B-phase signals of the encoder that outputs the A-phase and B-phase signals having phases different from each other by 90 degrees,
A first RS flip-flop receiving the A-phase signal to the S input, the R-input of the B-phase signal; and a second RS flip-flop receiving the B-phase inverted signal to the S input and the A-phase inverted signal to the R input. R
An S flip-flop, a third RS flip-flop receiving the A-phase inverted signal to the S input, the B-phase signal R input, the B-phase inverted signal to the S input, and the A-phase signal applied to the R input. The input fourth RS flip-flop, the first RS flip-flop output signal and the second RS flip-flop.
A first AND circuit that takes a logical product of the flip-flop signal and a second AND circuit that takes a logical product of the third RS flip-flop output signal and the fourth RS flip-flop output signal Things. Claim 3
The described invention has a 90
In the signal processing method of the encoder for removing the jitter generated at the edge portions of the A-phase and B-phase signals of the encoder outputting the A-phase and B-phase signals having different phase phases, the S-input of the first RS flip-flop is Inputting the A-phase signal to the R input of the B-phase signal, inputting the inverted signal of the B phase to the S input of the second RS flip-flop, and inputting the inverted signal of the A phase to the R input; 3, the A-phase inverted signal is input to the S input of the RS flip-flop, and the B-phase signal is input to the R input, and the B-phase inverted signal is input to the S input of the fourth RS flip-flop. A phase signal is input to an R input, and the first RS flip-flop output signal and the second R
A signal obtained by ANDing with the S flip-flop signal is defined as a true A-phase signal, and a signal obtained by performing a logical AND between the third RS flip-flop output signal and the fourth RS flip-flop output signal is a true signal. This is a B-phase signal.

[0005]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a signal processing circuit diagram according to an embodiment of the present invention. FIG. 2 is a signal waveform diagram showing the operation of each unit. In FIG. 1, reference numerals 1 to 4 denote RS flip-flops constituted by NAND gates. The S input S1 of the RS flip-flop 1 receives the A signal of the two-phase rectangular wave signal having the jitter at the edge shown in FIG.
1, the B signal shown in FIG. The S input S2 of the RS flip-flop 2 has a B- signal which is an inverted signal of the B signal shown in FIG. 2D, and the R input R2 has an A which is an inverted signal of the A signal shown in FIG. A signal is input; Further, the S input S3 of the RS flip-flop 3
, An A signal is input to the R input R3, a B signal is input to the S input S4 of the RS flip-flop 4, and an A signal is input to the R input R4. RS flip-flop 1
The output Q1 'of FIG. 2 outputs the waveform shown in FIG.
The waveform shown by f in FIG. 2 is output to the output Q2 'of the S flip-flop 2. When the AND signal of both of them is taken by the AND gate 5, an output Ao having no jitter at the edge portion shown by i in FIG. 2 is obtained. The output Q3 of the RS flip-flop 3 outputs the waveform shown by g in FIG.
The waveform indicated by h in FIG. 2 is output to the output Q4 of the S flip-flop 4. When the AND signal of the both is taken by the AND gate 6, an output Bo having no jitter at the edge portion shown by j in FIG. 2 is obtained. Ao and Bo are rectangular wave signals having phases different from each other by 90 degrees. The combination of the input signal to the RS flip-flop and the combination of the output signal are not limited to the above embodiment. It is apparent that the same function as that of the embodiment can be obtained even if the RS flip-flop is configured by an OR gate.

[0006]

According to the present invention, there is provided an encoder for outputting a two-phase rectangular wave signal having a phase difference of 90 degrees with respect to the displacement of a detection object. In the signal processing circuit,
Phase square wave signal and the inverted signal of the square wave signal
An AND signal of an output of two sets of RS flip-flops, which is an input signal of a flip-flop, an output of two sets of RS flip-flops out of the outputs of the four sets of RS flip-flops, Therefore, a means for outputting a two-phase rectangular wave signal having a phase difference of 90 degrees without jitter at the edge portion is provided, so that a wide frequency range which cannot be dealt with by a jitter removing method using a delay filter or a peak hold circuit is provided. It is possible to provide a jitter elimination circuit that can handle input signals in a range and a signal processing method thereof. In particular, when a detection signal having a phase difference of 90 degrees from an encoder is made to have a high resolution by using an electrical interpolation circuit, jitter can be reliably removed while maintaining the phase difference of the detection signal at 90 degrees. realizable.

[Brief description of the drawings]

FIG. 1 is a signal processing circuit diagram according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram of each part showing an operation of the signal processing circuit of the present invention.

FIG. 3 is a block diagram of a conventional noise removing circuit (conventional example 1).

FIG. 4 is a diagram showing input / output signals of an interpolation circuit.

5 is an enlarged view of the least significant bit B0 shown in FIG. 4 and the bit B1 immediately above the least significant bit B0 in the horizontal axis direction.

FIG. 6 is a diagram illustrating a two-phase rectangular wave signal having a jitter at an edge portion.

FIG. 7 is a connection diagram of a conventional jitter elimination circuit (conventional example 2).

FIG. 8 is a signal waveform diagram of each section showing the operation of Conventional Example 2;

[Explanation of symbols]

 1-4 RS flip-flops 5-6 NAND gate a A signal b B signal c A-signal d B- signal e Signal of output Q1 'of RS flip-flop 1 f Signal of output Q2' of RS flip-flop 2 g RS flip-flop Signal of the output Q3 of the flip-flop h signal of the output Q4 of the RS flip-flop 4 i Ao signal j Bo signal

Claims (3)

[Claims] 1. With respect to the displacement of a detection object, 90
A signal processing circuit of an encoder for removing jitter generated at an edge portion of the rectangular wave signal of the encoder that outputs a two-phase rectangular wave signal having different degrees of phase, wherein the two-phase rectangular wave signal and the inversion of the rectangular wave signal are provided. The signal is used as an input signal of four sets of RS flip-flops, and the output A of two sets of RS flip-flops among the outputs of the four sets of RS flip-flops is used.
Means for outputting a two-phase rectangular wave signal having a 90-degree phase different from that of the two sets and having a 90-degree phase without jitter by taking an AND signal of the outputs of two different sets of RS flip-flops different from the two sets. A signal processing circuit for an encoder, comprising: 2. With respect to the displacement of the detection object, 90
A signal processing circuit of an encoder that removes jitter generated at the edges of the A-phase and B-phase signals of the encoder that outputs the A-phase and B-phase signals having different degrees of phase; A first RS flip-flop to which the phase signal is R input; a second RS flip-flop to which the B-phase inverted signal is input to the S input; and the A-phase inverted signal which is R input; A third RS flip-flop receiving the signal to the S input and the R input of the B-phase signal; a fourth RS flip-flop receiving the inverted signal of the B-phase to the S input and the R input of the A-phase signal; A first AND circuit for performing an AND operation of the first RS flip-flop output signal and the second RS flip-flop output signal; a third RS flip-flop output signal and the fourth RS flip-flop; Encoder signal processing circuit, characterized in that a second AND circuit for ANDing the flop output signal. 3. Displacement of the detection object is 90
In the signal processing method of the encoder for removing the jitter generated at the edge portion of the A-phase and B-phase signals of the encoder outputting the A-phase and B-phase signals having different phase phases, Inputting the A phase signal to the R input of the B phase signal, inputting the inverted signal of the B phase to the S input of the second RS flip-flop, and inputting the inverted signal of the A phase to the R input; The A-phase inverted signal is input to the S input of the third RS flip-flop, the B-phase signal is input to the R input, and the B-phase inverted signal is input to the S input of the fourth RS flip-flop. A phase signal is input to an R input, and a signal obtained by ANDing the first RS flip-flop output signal and the second RS flip-flop output signal is set as a true A-phase signal; Output signal and the Signal processing method of an encoder, wherein a signal of the logical product of the RS flip-flop output signal 4 and the true B-phase signal.